Near-threshold fatigue crack propagation behaviour of a cold-worked copper tested with distinct fa- tigue testing systems under different stress ratios has been investigated.The emphasis was placed on the evaluation o...Near-threshold fatigue crack propagation behaviour of a cold-worked copper tested with distinct fa- tigue testing systems under different stress ratios has been investigated.The emphasis was placed on the evaluation of crack closure effect as well as the effective fatigue threshold,It was found that the fatigue threshold for R=0 is higher than those for R=-1 and R=0.4,for which almost the same threshold value was derived.Compared with the conventional closure evaluation method,the pro- posed new closure evaluation method can generally interpret the dependence of the fatigue thresh- old on stress ratio and loading condition,and leads to a higher and relatively constant effective fa- tigue threshold of about 3 MPa·m^(1/2) for the cold-worked copper at different stress ratios and loading conditions.展开更多
SEM microfractography of near-threshold fatigue crack propagation were carried out in the dual-phase steels of 3 martensite morphologies and 6 volume fractions of martensite (V_m). All of them are featured by cyclic c...SEM microfractography of near-threshold fatigue crack propagation were carried out in the dual-phase steels of 3 martensite morphologies and 6 volume fractions of martensite (V_m). All of them are featured by cyclic cleavage characteristics in near-threshold region,i.e.,main- ly controlled by mode Ⅱ stress.In the higher ΔK regions,the fracture surfaces are character- ized by mixed modes including cyclic cleavage facets,two types of secondary cracks and striations,etc..The roughness-induced crack closure of fracture surface is attributed primarily to extreme high fatigue crack growth threshold values.展开更多
The fracture surface micromorphology in the near-threshold FCG region was studied in LD-10 aluminum alloy and Ti-6Al-4V allov.The SEM examinations reveal that the frac- ture surface of both alloys at low crack growth ...The fracture surface micromorphology in the near-threshold FCG region was studied in LD-10 aluminum alloy and Ti-6Al-4V allov.The SEM examinations reveal that the frac- ture surface of both alloys at low crack growth rates(1×10^(-7)-1×10^(-5)mm/cycle)takes on a cyclic facet appearance.The typical morphologies were either sawtoothedfacets or terraced facets for LD-10 aluminum alloy and isolated island facets for Ti-6Al-4V alloy.The mech- anism of near-threshold fatigue crack growth is explicated on the basis of experimental ob- servations.展开更多
When it comes to decreasing margins and increasing energy effi-ciency in near-threshold and sub-threshold processors,timing error resilience may be viewed as a potentially lucrative alternative to examine.On the other...When it comes to decreasing margins and increasing energy effi-ciency in near-threshold and sub-threshold processors,timing error resilience may be viewed as a potentially lucrative alternative to examine.On the other hand,the currently employed approaches have certain restrictions,including high levels of design complexity,severe time constraints on error consolidation and propagation,and uncontaminated architectural registers(ARs).The design of near-threshold circuits,often known as NT circuits,is becoming the approach of choice for the construction of energy-efficient digital circuits.As a result of the exponentially decreased driving current,there was a reduction in performance,which was one of the downsides.Numerous studies have advised the use of NT techniques to chip multiprocessors as a means to preserve outstanding energy efficiency while minimising performance loss.Over the past several years,there has been a clear growth in interest in the development of artificial intelligence hardware with low energy consumption(AI).This has resulted in both large corporations and start-ups producing items that compete on the basis of varying degrees of performance and energy use.This technology’s ultimate goal was to provide levels of efficiency and performance that could not be achieved with graphics processing units or general-purpose CPUs.To achieve this objective,the technology was created to integrate several processing units into a single chip.To accomplish this purpose,the hardware was designed with a number of unique properties.In this study,an Energy Effi-cient Hyperparameter Tuned Deep Neural Network(EEHPT-DNN)model for Variation-Tolerant Near-Threshold Processor was developed.In order to improve the energy efficiency of artificial intelligence(AI),the EEHPT-DNN model employs several AI techniques.The notion focuses mostly on the repercussions of embedded technologies positioned at the network’s edge.The presented model employs a deep stacked sparse autoencoder(DSSAE)model with the objective of creating a variation-tolerant NT processor.The time-consuming method of modifying hyperparameters through trial and error is substituted with the marine predators optimization algorithm(MPO).This method is utilised to modify the hyperparameters associated with the DSSAE model.To validate that the proposed EEHPT-DNN model has a higher degree of functionality,a full simulation study is conducted,and the results are analysed from a variety of perspectives.This was completed so that the enhanced performance could be evaluated and analysed.According to the results of the study that compared numerous DL models,the EEHPT-DNN model performed significantly better than the other models.展开更多
The demise of Dennard’s scaling has created both power and utilization wall challenges for computer systems.As transistors operating in the near-threshold region are able to obtain flexible trade-offs between power a...The demise of Dennard’s scaling has created both power and utilization wall challenges for computer systems.As transistors operating in the near-threshold region are able to obtain flexible trade-offs between power and performance,it is regarded as an alternative solution to the scaling challenge.A reduction in supply voltage will nevertheless generate significant reliability challenges,while maintaining an error-free system that generates high costs in both performance and energy consumption.The main purpose of research on computer architecture has therefore shifted from performance improvement to complex multi-objective optimization.In this paper,we propose a three-dimensional optimization approach which can effectively identify the best system configuration to establish a balance among performance,energy,and reliability.We use a dynamic programming algorithm to determine the proper voltage and approximate level based on three predictors:system performance,energy consumption,and output quality.We propose an output quality predictor which uses a hardware/software co-design fault injection platform to evaluate the impact of the error on output quality under near-threshold computing(NTC).Evaluation results demonstrate that our approach can lead to a 28% improvement in output quality with a 10% drop in overall energy efficiency;this translates to an approximately 20% average improvement in accuracy,power,and performance.展开更多
The load power range of modern processors is greatly enlarged because many advanced power management techniques are employed, such as dynamic voltage frequency scaling, Turbo Boosting, and near-threshold voltage （NTV...The load power range of modern processors is greatly enlarged because many advanced power management techniques are employed, such as dynamic voltage frequency scaling, Turbo Boosting, and near-threshold voltage （NTV） technologies. However, because the efficiency of power delivery varies greatly with different load conditions, conventional power delivery designs cannot maintain high efficiency over the entire voltage spectrum, and the gained power saving may be offset by power loss in power delivery. We propose SuperRange, a wide operational range power delivery unit. SuperRange complements the power delivery capability of on-chip voltage regulator and off-chip voltage regulator. On top of SuperRange, we analyze its power conversion characteristics and propose a voltage regulator （VR） aware power management algorithm. Moreover, as more and more cores have been integrated on a singe chip, multiple SuperRange units can serve as basic building blocks to build, in a highly scalable way, more powerful power delivery subsystem with larger power capacity. Experimental results show SuperRange unit offers lx and 1.3x higher power conversion efficiency （PCE） than other two conventional power delivery schemes at NTV region and exhibits an average 70% PCE over entire operational range. It also exhibits superior resilience to power-constrained systems.展开更多
基于条件预充电技术,设计了一种高速低功耗真单相时钟触发器。在存在冗余开关活动的关键路径中,通过增加场效应管和控制条件,控制内部节点的冗余预充电活动;通过消除冗余结构,消除冗余的场效应管,从而改善电路结构,降低功耗和总功耗延...基于条件预充电技术,设计了一种高速低功耗真单相时钟触发器。在存在冗余开关活动的关键路径中,通过增加场效应管和控制条件,控制内部节点的冗余预充电活动;通过消除冗余结构,消除冗余的场效应管,从而改善电路结构,降低功耗和总功耗延时积。通用电路分析程序(simulation program with integrated circuit emphasis,HSPICE)仿真结果表明,在100 MHz的工作频率与低阈值电压下,触发器功耗低至158.6127 nW、总功耗延时积低至0.048735 fJ,电路具有正确的逻辑功能,且在功耗、延迟方面均优于近几年提出的电路。展开更多
文摘Near-threshold fatigue crack propagation behaviour of a cold-worked copper tested with distinct fa- tigue testing systems under different stress ratios has been investigated.The emphasis was placed on the evaluation of crack closure effect as well as the effective fatigue threshold,It was found that the fatigue threshold for R=0 is higher than those for R=-1 and R=0.4,for which almost the same threshold value was derived.Compared with the conventional closure evaluation method,the pro- posed new closure evaluation method can generally interpret the dependence of the fatigue thresh- old on stress ratio and loading condition,and leads to a higher and relatively constant effective fa- tigue threshold of about 3 MPa·m^(1/2) for the cold-worked copper at different stress ratios and loading conditions.
文摘SEM microfractography of near-threshold fatigue crack propagation were carried out in the dual-phase steels of 3 martensite morphologies and 6 volume fractions of martensite (V_m). All of them are featured by cyclic cleavage characteristics in near-threshold region,i.e.,main- ly controlled by mode Ⅱ stress.In the higher ΔK regions,the fracture surfaces are character- ized by mixed modes including cyclic cleavage facets,two types of secondary cracks and striations,etc..The roughness-induced crack closure of fracture surface is attributed primarily to extreme high fatigue crack growth threshold values.
文摘The fracture surface micromorphology in the near-threshold FCG region was studied in LD-10 aluminum alloy and Ti-6Al-4V allov.The SEM examinations reveal that the frac- ture surface of both alloys at low crack growth rates(1×10^(-7)-1×10^(-5)mm/cycle)takes on a cyclic facet appearance.The typical morphologies were either sawtoothedfacets or terraced facets for LD-10 aluminum alloy and isolated island facets for Ti-6Al-4V alloy.The mech- anism of near-threshold fatigue crack growth is explicated on the basis of experimental ob- servations.
文摘When it comes to decreasing margins and increasing energy effi-ciency in near-threshold and sub-threshold processors,timing error resilience may be viewed as a potentially lucrative alternative to examine.On the other hand,the currently employed approaches have certain restrictions,including high levels of design complexity,severe time constraints on error consolidation and propagation,and uncontaminated architectural registers(ARs).The design of near-threshold circuits,often known as NT circuits,is becoming the approach of choice for the construction of energy-efficient digital circuits.As a result of the exponentially decreased driving current,there was a reduction in performance,which was one of the downsides.Numerous studies have advised the use of NT techniques to chip multiprocessors as a means to preserve outstanding energy efficiency while minimising performance loss.Over the past several years,there has been a clear growth in interest in the development of artificial intelligence hardware with low energy consumption(AI).This has resulted in both large corporations and start-ups producing items that compete on the basis of varying degrees of performance and energy use.This technology’s ultimate goal was to provide levels of efficiency and performance that could not be achieved with graphics processing units or general-purpose CPUs.To achieve this objective,the technology was created to integrate several processing units into a single chip.To accomplish this purpose,the hardware was designed with a number of unique properties.In this study,an Energy Effi-cient Hyperparameter Tuned Deep Neural Network(EEHPT-DNN)model for Variation-Tolerant Near-Threshold Processor was developed.In order to improve the energy efficiency of artificial intelligence(AI),the EEHPT-DNN model employs several AI techniques.The notion focuses mostly on the repercussions of embedded technologies positioned at the network’s edge.The presented model employs a deep stacked sparse autoencoder(DSSAE)model with the objective of creating a variation-tolerant NT processor.The time-consuming method of modifying hyperparameters through trial and error is substituted with the marine predators optimization algorithm(MPO).This method is utilised to modify the hyperparameters associated with the DSSAE model.To validate that the proposed EEHPT-DNN model has a higher degree of functionality,a full simulation study is conducted,and the results are analysed from a variety of perspectives.This was completed so that the enhanced performance could be evaluated and analysed.According to the results of the study that compared numerous DL models,the EEHPT-DNN model performed significantly better than the other models.
基金Project supported by the National Natural Science Foundation of China(Nos.62076168 and 61772350)Beijing Nova Program(No.Z181100006218093)the Research Fund from Beijing Innovation Center for Future Chips(No.KYJJ2018008)。
文摘The demise of Dennard’s scaling has created both power and utilization wall challenges for computer systems.As transistors operating in the near-threshold region are able to obtain flexible trade-offs between power and performance,it is regarded as an alternative solution to the scaling challenge.A reduction in supply voltage will nevertheless generate significant reliability challenges,while maintaining an error-free system that generates high costs in both performance and energy consumption.The main purpose of research on computer architecture has therefore shifted from performance improvement to complex multi-objective optimization.In this paper,we propose a three-dimensional optimization approach which can effectively identify the best system configuration to establish a balance among performance,energy,and reliability.We use a dynamic programming algorithm to determine the proper voltage and approximate level based on three predictors:system performance,energy consumption,and output quality.We propose an output quality predictor which uses a hardware/software co-design fault injection platform to evaluate the impact of the error on output quality under near-threshold computing(NTC).Evaluation results demonstrate that our approach can lead to a 28% improvement in output quality with a 10% drop in overall energy efficiency;this translates to an approximately 20% average improvement in accuracy,power,and performance.
基金This work is supported by the National Natural Science Foundation of China under Grant Nos. 61572470, 61532017, 61522406, 61432017, 61376043, and 61221062.
文摘The load power range of modern processors is greatly enlarged because many advanced power management techniques are employed, such as dynamic voltage frequency scaling, Turbo Boosting, and near-threshold voltage （NTV） technologies. However, because the efficiency of power delivery varies greatly with different load conditions, conventional power delivery designs cannot maintain high efficiency over the entire voltage spectrum, and the gained power saving may be offset by power loss in power delivery. We propose SuperRange, a wide operational range power delivery unit. SuperRange complements the power delivery capability of on-chip voltage regulator and off-chip voltage regulator. On top of SuperRange, we analyze its power conversion characteristics and propose a voltage regulator （VR） aware power management algorithm. Moreover, as more and more cores have been integrated on a singe chip, multiple SuperRange units can serve as basic building blocks to build, in a highly scalable way, more powerful power delivery subsystem with larger power capacity. Experimental results show SuperRange unit offers lx and 1.3x higher power conversion efficiency （PCE） than other two conventional power delivery schemes at NTV region and exhibits an average 70% PCE over entire operational range. It also exhibits superior resilience to power-constrained systems.
文摘基于条件预充电技术,设计了一种高速低功耗真单相时钟触发器。在存在冗余开关活动的关键路径中,通过增加场效应管和控制条件,控制内部节点的冗余预充电活动;通过消除冗余结构,消除冗余的场效应管,从而改善电路结构,降低功耗和总功耗延时积。通用电路分析程序(simulation program with integrated circuit emphasis,HSPICE)仿真结果表明,在100 MHz的工作频率与低阈值电压下,触发器功耗低至158.6127 nW、总功耗延时积低至0.048735 fJ,电路具有正确的逻辑功能,且在功耗、延迟方面均优于近几年提出的电路。
