Near-interface oxide traps （NIOTs） in 4H-SiC metal-oxide-semiconductor （MOS） structures fabricated with and without annealing in NO are systematically investigated in this paper. The properties of NIOTs in SiC MOS...Near-interface oxide traps （NIOTs） in 4H-SiC metal-oxide-semiconductor （MOS） structures fabricated with and without annealing in NO are systematically investigated in this paper. The properties of NIOTs in SiC MOS structures prepared with and without annealing in NO are studied and compared in detail. Two main categories of the NIOTs, the “slow” and “fast” NIOTs, are revealed and extracted. The densities of the “fast” NIOTs are determined to be 0.761011 cm-2 and 0.471011 cm-2 for the N2 post oxidation annealing （POA） sample and NO POA sample, respectively. The densities of “slow” NIOTs are 0.791011 cm-2 and 9.441011 cm-2 for the NO POA sample and N2 POA sample, respectively. It is found that the NO POA process only can significantly reduce “slow” NIOTs. However, it has a little effect on “fast” NIOTs. The negative and positive constant voltage stresses （CVS） reveal that electrons captured by those “slow” NIOTs and bulk oxide traps （BOTs） are hardly emitted by the constant voltage stress.展开更多
A two-dimensional electrical SiC MOS interface model including interface and near-interface traps is established based on the relevant tunneling and interface Shockley–Read–Hall model. The consistency between simula...A two-dimensional electrical SiC MOS interface model including interface and near-interface traps is established based on the relevant tunneling and interface Shockley–Read–Hall model. The consistency between simulation results and measured data in the different temperatures shows that this interface model can accurately describe the capture and emission performance for near-interface oxide traps, and can well explain the hysteresis-voltage response with increasing temperature, which is intensified by the interaction between deep oxide traps and shallow oxide traps. This also indicates that the near-interface traps result in an increase of threshold-voltage shift in SiC MOSFET with increasing temperature.展开更多
基金Project supported by the National Key Basic Research Program of China(Grant No.2015CB759600)the Natural Science Basic Research Plan in Shaanxi Province,China(Grant No.2017JM6003)the National Natural Science Foundation of China(Grant Nos.61774117 61404098 and 61274079)
文摘Near-interface oxide traps （NIOTs） in 4H-SiC metal-oxide-semiconductor （MOS） structures fabricated with and without annealing in NO are systematically investigated in this paper. The properties of NIOTs in SiC MOS structures prepared with and without annealing in NO are studied and compared in detail. Two main categories of the NIOTs, the “slow” and “fast” NIOTs, are revealed and extracted. The densities of the “fast” NIOTs are determined to be 0.761011 cm-2 and 0.471011 cm-2 for the N2 post oxidation annealing （POA） sample and NO POA sample, respectively. The densities of “slow” NIOTs are 0.791011 cm-2 and 9.441011 cm-2 for the NO POA sample and N2 POA sample, respectively. It is found that the NO POA process only can significantly reduce “slow” NIOTs. However, it has a little effect on “fast” NIOTs. The negative and positive constant voltage stresses （CVS） reveal that electrons captured by those “slow” NIOTs and bulk oxide traps （BOTs） are hardly emitted by the constant voltage stress.
基金Supported by the Science Challenge Project under Grant No TZ2018003
文摘A two-dimensional electrical SiC MOS interface model including interface and near-interface traps is established based on the relevant tunneling and interface Shockley–Read–Hall model. The consistency between simulation results and measured data in the different temperatures shows that this interface model can accurately describe the capture and emission performance for near-interface oxide traps, and can well explain the hysteresis-voltage response with increasing temperature, which is intensified by the interaction between deep oxide traps and shallow oxide traps. This also indicates that the near-interface traps result in an increase of threshold-voltage shift in SiC MOSFET with increasing temperature.
