In this paper, novel ultra low voltage (ULV) dual-rail NOR gates are presented which use the semi-floating-gate (SFG) structure to speed up the logic circuit. Higher speed in the lower supply voltages and robustness a...In this paper, novel ultra low voltage (ULV) dual-rail NOR gates are presented which use the semi-floating-gate (SFG) structure to speed up the logic circuit. Higher speed in the lower supply voltages and robustness against the input signal delay variations are the main advantages of the proposed gates in comparison to the previously reported domino dual-rail NOR gates. The simulation results in a typical TSMC 90 nm CMOS technology show that the proposed NOR gate is more than 20 times faster than conventional dual-rail NOR gate.展开更多
In this study, we propose complementary metal-oxide-semiconductor （CMOS） NOR logic gates consisting of silicon nanowire （NW） arrays on bendable substrates. A circuit consisting of two p-channel NW field-effect tra...In this study, we propose complementary metal-oxide-semiconductor （CMOS） NOR logic gates consisting of silicon nanowire （NW） arrays on bendable substrates. A circuit consisting of two p-channel NW field-effect transistors （NWFETs） in series and two n-channel NWFETs in parallel is constructed to operate a two- input CMOS NOR logic gate. The NOR logic gates operate at a low supply voltage of 1 V with a rail-to-rail logic swing and a high voltage gain of approximately -3.0. The exact NOR logic functionality is achieved owing to the superior electrical characteristics of the well-aligned p- and n-NWFETs, which are obtained using conventional Si-based CMOS technology. Moreover, the NOR logic gates exhibit stable characteristics and have good mechanical properties. The proposed bendable NW CMOS NOR logic gates are promising building blocks for future bendable integrated electronics.展开更多
This paper presents a 65-nm 1-Gb NOR-type floating-gate flash memory,in which the cell device and chip circuit are developed and optimized.In order to solve the speed problem of giga-level NOR flash in the deep submic...This paper presents a 65-nm 1-Gb NOR-type floating-gate flash memory,in which the cell device and chip circuit are developed and optimized.In order to solve the speed problem of giga-level NOR flash in the deep submicron process,the models of long bit-line and word-line are first given,by which the capacitive and resistive loads could be estimated.Based on that,the read path and key modules are optimized to enhance the chip access property and reliability.With the measurement results,the flash memory cell presents good endurance and retention properties,and the macro is operated with 1-ls/byte program speed and less than 50-ns read time under 3.3 V supply.展开更多
文摘In this paper, novel ultra low voltage (ULV) dual-rail NOR gates are presented which use the semi-floating-gate (SFG) structure to speed up the logic circuit. Higher speed in the lower supply voltages and robustness against the input signal delay variations are the main advantages of the proposed gates in comparison to the previously reported domino dual-rail NOR gates. The simulation results in a typical TSMC 90 nm CMOS technology show that the proposed NOR gate is more than 20 times faster than conventional dual-rail NOR gate.
文摘In this study, we propose complementary metal-oxide-semiconductor （CMOS） NOR logic gates consisting of silicon nanowire （NW） arrays on bendable substrates. A circuit consisting of two p-channel NW field-effect transistors （NWFETs） in series and two n-channel NWFETs in parallel is constructed to operate a two- input CMOS NOR logic gate. The NOR logic gates operate at a low supply voltage of 1 V with a rail-to-rail logic swing and a high voltage gain of approximately -3.0. The exact NOR logic functionality is achieved owing to the superior electrical characteristics of the well-aligned p- and n-NWFETs, which are obtained using conventional Si-based CMOS technology. Moreover, the NOR logic gates exhibit stable characteristics and have good mechanical properties. The proposed bendable NW CMOS NOR logic gates are promising building blocks for future bendable integrated electronics.
基金supported in part by the Ministry of Science and Technology of China (2010CB934200,2011CBA00600)the National Natural Science Foundation of China (61176073)+1 种基金the National Science and Technology Major Project of China (2009ZX02023-005)the Director’s Fund of Institute of Microelectronics,Chinese Academy of Science
文摘This paper presents a 65-nm 1-Gb NOR-type floating-gate flash memory,in which the cell device and chip circuit are developed and optimized.In order to solve the speed problem of giga-level NOR flash in the deep submicron process,the models of long bit-line and word-line are first given,by which the capacitive and resistive loads could be estimated.Based on that,the read path and key modules are optimized to enhance the chip access property and reliability.With the measurement results,the flash memory cell presents good endurance and retention properties,and the macro is operated with 1-ls/byte program speed and less than 50-ns read time under 3.3 V supply.
