In this paper, we propose a technique for lowering the latency of the communication in a NoC （network on chip）. The technique, which can support two qualities of service （QoS）, i.e., the guaranteed throughput （GT...In this paper, we propose a technique for lowering the latency of the communication in a NoC （network on chip）. The technique, which can support two qualities of service （QoS）, i.e., the guaranteed throughput （GT） and best effort （BE）, is based on splitting a wider link into narrower links to increase throughput and decrease latency in the NoC. In addition, to ease the synchronization and reduce the crosstalk, we use the l-of-4 encoding for the smaller buses. The use of the encoding in the proposed NoC architecture considerably lowers the latency for both BE and GT packets. In addition, the bandwidth is increased while the power consumption of the links is reduced.展开更多
This paper presents the result of experiments conducted in mesh networks on different routing algorithms, traffic generation schemes and switching schemes. A new network on chip (NoC) topology based on partial interco...This paper presents the result of experiments conducted in mesh networks on different routing algorithms, traffic generation schemes and switching schemes. A new network on chip (NoC) topology based on partial interconnection of mesh network is proposed and a routing algorithm supporting the proposed architecture is developed. The proposed architecture is similar to standard mesh networks, where four extra bidirectional channels are added which remove the congestion and hotspots compared to standard mesh networks with fewer channels. Significant improvement in delay (60% reduction) and throughput (60% increase) was observed using the proposed network and routing when compared with the ideal mesh networks. An increase in number of channels makes the switches expensive and could increase the area and power consumption. However, the proposed network can be useful in high speed applications with some compromise on area and power.展开更多
针对深度神经网络(deep neural network,DNN)模型在传统切片与映射方法中存在的资源调度和数据传输瓶颈问题,提出了一种基于片上网络(network on chip,NoC)加速器的高效DNN动态切片与智能映射优化算法。该算法通过动态切片技术灵活划分...针对深度神经网络(deep neural network,DNN)模型在传统切片与映射方法中存在的资源调度和数据传输瓶颈问题,提出了一种基于片上网络(network on chip,NoC)加速器的高效DNN动态切片与智能映射优化算法。该算法通过动态切片技术灵活划分DNN模型的计算任务,并结合智能映射策略优化NoC架构中的任务分配与数据流管理。实验结果表明,与传统方法相比,该算法在计算吞吐量、NoC传输时延、外部内存访问次数和计算能效等方面均显著提升,尤其在复杂模型上表现突出。展开更多
随着集成电路技术的飞速发展,其集成度和复杂度越来越高,导致芯片功耗问题日益严重。文章提出一套兼容片上网络(Net on Chip,NoC)总线的功耗管理总线,针对不同电源域进行低功耗管理,通过电源域开关协议将电源域状态同步到事务活动,且不...随着集成电路技术的飞速发展,其集成度和复杂度越来越高,导致芯片功耗问题日益严重。文章提出一套兼容片上网络(Net on Chip,NoC)总线的功耗管理总线,针对不同电源域进行低功耗管理,通过电源域开关协议将电源域状态同步到事务活动,且不影响系统其他部分的操作。实验结果表明,功耗管理总线具有低成本、协议简单、兼容性好、轻量级等优势。展开更多
基金Project supported by the Iranian National Science Foundation
文摘In this paper, we propose a technique for lowering the latency of the communication in a NoC （network on chip）. The technique, which can support two qualities of service （QoS）, i.e., the guaranteed throughput （GT） and best effort （BE）, is based on splitting a wider link into narrower links to increase throughput and decrease latency in the NoC. In addition, to ease the synchronization and reduce the crosstalk, we use the l-of-4 encoding for the smaller buses. The use of the encoding in the proposed NoC architecture considerably lowers the latency for both BE and GT packets. In addition, the bandwidth is increased while the power consumption of the links is reduced.
文摘This paper presents the result of experiments conducted in mesh networks on different routing algorithms, traffic generation schemes and switching schemes. A new network on chip (NoC) topology based on partial interconnection of mesh network is proposed and a routing algorithm supporting the proposed architecture is developed. The proposed architecture is similar to standard mesh networks, where four extra bidirectional channels are added which remove the congestion and hotspots compared to standard mesh networks with fewer channels. Significant improvement in delay (60% reduction) and throughput (60% increase) was observed using the proposed network and routing when compared with the ideal mesh networks. An increase in number of channels makes the switches expensive and could increase the area and power consumption. However, the proposed network can be useful in high speed applications with some compromise on area and power.
文摘针对深度神经网络(deep neural network,DNN)模型在传统切片与映射方法中存在的资源调度和数据传输瓶颈问题,提出了一种基于片上网络(network on chip,NoC)加速器的高效DNN动态切片与智能映射优化算法。该算法通过动态切片技术灵活划分DNN模型的计算任务,并结合智能映射策略优化NoC架构中的任务分配与数据流管理。实验结果表明,与传统方法相比,该算法在计算吞吐量、NoC传输时延、外部内存访问次数和计算能效等方面均显著提升,尤其在复杂模型上表现突出。
文摘随着集成电路技术的飞速发展,其集成度和复杂度越来越高,导致芯片功耗问题日益严重。文章提出一套兼容片上网络(Net on Chip,NoC)总线的功耗管理总线,针对不同电源域进行低功耗管理,通过电源域开关协议将电源域状态同步到事务活动,且不影响系统其他部分的操作。实验结果表明,功耗管理总线具有低成本、协议简单、兼容性好、轻量级等优势。
