Static phase offset (SPO) in conventional multiplying delay-locked loops (MDLLs) dramatically degrades the deterministic jitter performance. To overcome the issue, this paper presents a new SPO reduction technique for...Static phase offset (SPO) in conventional multiplying delay-locked loops (MDLLs) dramatically degrades the deterministic jitter performance. To overcome the issue, this paper presents a new SPO reduction technique for MDLLs. The technique is based on the observation that the SPO of MDLL is mainly caused by the non-idealities on charge pump (e.g. sink and source current mismatch), and control line (e.g. gate leakage of loop filter and voltage controlled delay line (VCDL) control circuit). With a high gain stage inserting between phase detector/phase frequency detector (PD/PFD) and charge pump, the equivalent SPO has been decreased by a factor equal to the gain of the gain stage. The effectiveness of the proposed technique is validated by a Simulink model of MDLL. The equivalent SPO is measured by the power level of reference spur.展开更多
A 3.5 times PLL clock frequency multiplier for low voltage different signal （LVDS） driver is presented. A novel adaptive charge pump can automatically switch the loop bandwidth and a voltage-controlled oscillator （...A 3.5 times PLL clock frequency multiplier for low voltage different signal （LVDS） driver is presented. A novel adaptive charge pump can automatically switch the loop bandwidth and a voltage-controlled oscillator （VCO） is designed with the aid of frequency ranges reuse technology. The circuit is implemented using 1st Silicon 0.25 μm mixed-signal complementary metal-oxide-semiconductor （CMOS） process. Simulation results show that the PLL clock frequency multiplier has very low phase noise and very short capture time .展开更多
In scaled CMOS processes, the single-event effects generate missing output pulses in Delay-Locked Loop (DLL). Due to its effective sequence detection of the missing pulses in the proposed Error Correction Circuit (ECC...In scaled CMOS processes, the single-event effects generate missing output pulses in Delay-Locked Loop (DLL). Due to its effective sequence detection of the missing pulses in the proposed Error Correction Circuit (ECC) and its portability to be applied to any DLL type, the ECC mitigates the impact of single-event effects and completes its operation with less design complexity without any concern about losing the information. The ECC has been implemented in 180 nm CMOS process and measured the accuracy of mitigation on simulations at LETs up to 100 MeV-cm<sup>2</sup>/mg. The robustness and portability of the mitigation technique are validated through the results obtained by implementing proposed ECC in XilinxArtix 7 FPGA.展开更多
In order to improve the performance of multipath mitigation in tracking Galileo signals, a new multipath mitigation method named early-late strobe correlator （ELSC） is proposed. By applying the strobe correlator use...In order to improve the performance of multipath mitigation in tracking Galileo signals, a new multipath mitigation method named early-late strobe correlator （ELSC） is proposed. By applying the strobe correlator used widely in global positioning system （GPS） scenarios to Galileo E1 signals, it can be found that the strobe correlator has an undesirable level of performance when the delay of multipath signals is about 0. 5 chip. Combining several strobe correlators, the ELSC can effectively mitigate the multipath effect especially for the multipath signals with the 0. 5 chip delay. The multipath error envelopes between the strobe correlator and the ELSC are compared for Galileo E1 signals. The simulation results indicate that the ELSC performs excellently on multipath mitigation, and can be applied in both Galileo scenarios and GPS scenarios.展开更多
文摘Static phase offset (SPO) in conventional multiplying delay-locked loops (MDLLs) dramatically degrades the deterministic jitter performance. To overcome the issue, this paper presents a new SPO reduction technique for MDLLs. The technique is based on the observation that the SPO of MDLL is mainly caused by the non-idealities on charge pump (e.g. sink and source current mismatch), and control line (e.g. gate leakage of loop filter and voltage controlled delay line (VCDL) control circuit). With a high gain stage inserting between phase detector/phase frequency detector (PD/PFD) and charge pump, the equivalent SPO has been decreased by a factor equal to the gain of the gain stage. The effectiveness of the proposed technique is validated by a Simulink model of MDLL. The equivalent SPO is measured by the power level of reference spur.
基金Supported by the National Key Pre-Research Project of China (413010701-3)
文摘A 3.5 times PLL clock frequency multiplier for low voltage different signal （LVDS） driver is presented. A novel adaptive charge pump can automatically switch the loop bandwidth and a voltage-controlled oscillator （VCO） is designed with the aid of frequency ranges reuse technology. The circuit is implemented using 1st Silicon 0.25 μm mixed-signal complementary metal-oxide-semiconductor （CMOS） process. Simulation results show that the PLL clock frequency multiplier has very low phase noise and very short capture time .
文摘In scaled CMOS processes, the single-event effects generate missing output pulses in Delay-Locked Loop (DLL). Due to its effective sequence detection of the missing pulses in the proposed Error Correction Circuit (ECC) and its portability to be applied to any DLL type, the ECC mitigates the impact of single-event effects and completes its operation with less design complexity without any concern about losing the information. The ECC has been implemented in 180 nm CMOS process and measured the accuracy of mitigation on simulations at LETs up to 100 MeV-cm<sup>2</sup>/mg. The robustness and portability of the mitigation technique are validated through the results obtained by implementing proposed ECC in XilinxArtix 7 FPGA.
基金The National Key Technology R&D Program of China during the 11th Five-Year Plan Period(No.2008BAJ11B05)
文摘In order to improve the performance of multipath mitigation in tracking Galileo signals, a new multipath mitigation method named early-late strobe correlator （ELSC） is proposed. By applying the strobe correlator used widely in global positioning system （GPS） scenarios to Galileo E1 signals, it can be found that the strobe correlator has an undesirable level of performance when the delay of multipath signals is about 0. 5 chip. Combining several strobe correlators, the ELSC can effectively mitigate the multipath effect especially for the multipath signals with the 0. 5 chip delay. The multipath error envelopes between the strobe correlator and the ELSC are compared for Galileo E1 signals. The simulation results indicate that the ELSC performs excellently on multipath mitigation, and can be applied in both Galileo scenarios and GPS scenarios.
