This article proposes a new general, highly efficient algorithm for extracting domain terminologies. This domain-independent algorithm with multi-layers of filters is a hybrid of statistic-oriented and rule-oriented m...This article proposes a new general, highly efficient algorithm for extracting domain terminologies. This domain-independent algorithm with multi-layers of filters is a hybrid of statistic-oriented and rule-oriented methods. Utilizing the features of domain terminologies and the characteristics that are unique to Chinese, this algorithm extracts domain terminologies by generating multi-word unit （MWU） candidates at first and then fihering the candidates through multi-strategies. Our test resuhs show that this algorithm is feasible and effective.展开更多
当代英语语法大师R.Quirk等在巨著A Grammar of Contemporary English(1972)中首次提出多词动词(Multi-word verbs)问题,随后继续探索,在A Compre-hensive Grammar of the English Language(1985)中进一步提出完整的多词动词分类体系,...当代英语语法大师R.Quirk等在巨著A Grammar of Contemporary English(1972)中首次提出多词动词(Multi-word verbs)问题,随后继续探索,在A Compre-hensive Grammar of the English Language(1985)中进一步提出完整的多词动词分类体系,很有概括性,解决了许多问题。但是,其中仍有值得商榷和改进之处,本文对此进行了讨论。展开更多
This paper introduced a novel high performance algorithm and VLSI architectures for achieving bit plane coding （BPC） in word level sequential and parallel mode. The proposed BPC algorithm adopts the techniques of co...This paper introduced a novel high performance algorithm and VLSI architectures for achieving bit plane coding （BPC） in word level sequential and parallel mode. The proposed BPC algorithm adopts the techniques of coding pass prediction and parallel ＆ pipeline to reduce the number of accessing memory and to increase the ability of concurrently processing of the system, where all the coefficient bits of a code block could be coded by only one scan. A new parallel bit plane architecture （PA） was proposed to achieve word-level sequential coding. Moreover, an efficient high-speed architecture （HA） was presented to achieve multi-word parallel coding. Compared to the state of the art, the proposed PA could reduce the hardware cost more efficiently, though the throughput retains one coefficient coded per clock. While the proposed HA could perform coding for 4 coefficients belonging to a stripe column at one intra-clock cycle, so that coding for an NxN code-block could be completed in approximate N2/4 intra-clock cycles. Theoretical analysis and experimental results demonstrate that the proposed designs have high throughput rate with good performance in terms of speedup to cost, which can be good alternatives for low power applications.展开更多
Secure computing paradigms impose new architectural challenges for general-purpose processors. Cryptographic processing is needed for secure communications, storage, and computations. We identify two categories of ope...Secure computing paradigms impose new architectural challenges for general-purpose processors. Cryptographic processing is needed for secure communications, storage, and computations. We identify two categories of operations in symmetric-key and public-key cryptographic algorithms that are not common in previous general-purpose workloads： advanced bit operations within a word and multi-word operations. We define MOMR （Multiple Operands Multiple Results） execution or datarich execution as a unified solution to both challenges. It allows arbitrary n-bit permutations to be achieved in one or two cycles, rather than O（n） cycles as in existing RISC processors. It also enables significant acceleration of multiword multiplications needed by public-key ciphers. We propose two implementations of MOMR： one employs only hardware changes while the other uses Instruction Set Architecture （ISA） support. We show that MOMR execution leverages available resources in typical multi-issue processors with minimal additional cost. Multi-issue processors enhanced with MOMR units provide additional speedup over standard multi-issue processors with the same datapath. MOMR is a general architectural solution for word-oriented processor architectures to incorporate datarich operations.展开更多
基金Supported by the National Natural Science Foundation of China(Grant No. 60496326)
文摘This article proposes a new general, highly efficient algorithm for extracting domain terminologies. This domain-independent algorithm with multi-layers of filters is a hybrid of statistic-oriented and rule-oriented methods. Utilizing the features of domain terminologies and the characteristics that are unique to Chinese, this algorithm extracts domain terminologies by generating multi-word unit （MWU） candidates at first and then fihering the candidates through multi-strategies. Our test resuhs show that this algorithm is feasible and effective.
文摘当代英语语法大师R.Quirk等在巨著A Grammar of Contemporary English(1972)中首次提出多词动词(Multi-word verbs)问题,随后继续探索,在A Compre-hensive Grammar of the English Language(1985)中进一步提出完整的多词动词分类体系,很有概括性,解决了许多问题。但是,其中仍有值得商榷和改进之处,本文对此进行了讨论。
基金the Natural Science Foundation of Hubei Province (Grant No. 2006ABA370)Civil Research Project of State Defense (Grant No. C1120061304)+1 种基金National Natural Science Foundation of China (Grant No. 60572048)National High Technology Research and Develop-ment of China (863 Program) (Grant No. 2004AA119010-6)
文摘This paper introduced a novel high performance algorithm and VLSI architectures for achieving bit plane coding （BPC） in word level sequential and parallel mode. The proposed BPC algorithm adopts the techniques of coding pass prediction and parallel ＆ pipeline to reduce the number of accessing memory and to increase the ability of concurrently processing of the system, where all the coefficient bits of a code block could be coded by only one scan. A new parallel bit plane architecture （PA） was proposed to achieve word-level sequential coding. Moreover, an efficient high-speed architecture （HA） was presented to achieve multi-word parallel coding. Compared to the state of the art, the proposed PA could reduce the hardware cost more efficiently, though the throughput retains one coefficient coded per clock. While the proposed HA could perform coding for 4 coefficients belonging to a stripe column at one intra-clock cycle, so that coding for an NxN code-block could be completed in approximate N2/4 intra-clock cycles. Theoretical analysis and experimental results demonstrate that the proposed designs have high throughput rate with good performance in terms of speedup to cost, which can be good alternatives for low power applications.
文摘Secure computing paradigms impose new architectural challenges for general-purpose processors. Cryptographic processing is needed for secure communications, storage, and computations. We identify two categories of operations in symmetric-key and public-key cryptographic algorithms that are not common in previous general-purpose workloads： advanced bit operations within a word and multi-word operations. We define MOMR （Multiple Operands Multiple Results） execution or datarich execution as a unified solution to both challenges. It allows arbitrary n-bit permutations to be achieved in one or two cycles, rather than O（n） cycles as in existing RISC processors. It also enables significant acceleration of multiword multiplications needed by public-key ciphers. We propose two implementations of MOMR： one employs only hardware changes while the other uses Instruction Set Architecture （ISA） support. We show that MOMR execution leverages available resources in typical multi-issue processors with minimal additional cost. Multi-issue processors enhanced with MOMR units provide additional speedup over standard multi-issue processors with the same datapath. MOMR is a general architectural solution for word-oriented processor architectures to incorporate datarich operations.
