A multi-bit antifuse-type one-time programmable （OTP） memory is designed, which has a smaller area and a shorter programming time compared with the conventional single-bit antifuse-type OTP memory. While the convent...A multi-bit antifuse-type one-time programmable （OTP） memory is designed, which has a smaller area and a shorter programming time compared with the conventional single-bit antifuse-type OTP memory. While the conventional antifuse-type OTP memory can store a bit per cell, a proposed OTP memory can store two consecutive bits per cell through a data compression technique. The 1 kbit OTP memory designed with Magnachip 0.18 μm CMOS （complementary metal-oxide semiconductor） process is 34% smaller than the conventional single-bit antifuse-type OTP memory since the sizes of cell array and row decoder are reduced. And the programming time of the proposed OTP memory is nearly 50% smaller than that of the conventional counterpart since two consecutive bytes can be compressed and programmed into eight OTP cells at once. The layout area is 214 μm× 327 μ,, and the read current is simulated to be 30.4 μA.展开更多
Differential detection of continuous phase modulation suffers from significant intersymbol interference. To reduce bit error rate, multi-branch fractional multi-bit differential detection (MFMDD) with decision feed-ba...Differential detection of continuous phase modulation suffers from significant intersymbol interference. To reduce bit error rate, multi-branch fractional multi-bit differential detection (MFMDD) with decision feed-back is proposed. By introducing decision feedback in multi-bit differential detected signals, severe inter-symbol interference can be removed. Simulation results show that the proposed structure can greatly im-proves the performance compared with MFMDD without decision feedback, and the performance of 9 FMDD is very near to the performance of the coherent detection.展开更多
For the processor working in the radiation environment in space, it tends to suffer from the single event effect on circuits and system failures, due to cosmic rays and high energy particle radiation. Therefore, the r...For the processor working in the radiation environment in space, it tends to suffer from the single event effect on circuits and system failures, due to cosmic rays and high energy particle radiation. Therefore, the reliability of the processor has become an increasingly serious issue. The BCH-based error correction code can correct multibit errors, but it introduces large latency overhead. This paper proposes a hybrid error correction approach that combines BCH and EDAC to correct both multi-bit and single-bit errors for caches with low cost. The proposed technique can correct up to four-bit error, and correct single-bit error in one cycle. Evaluation results show that, the proposed hybrid error-correction scheme can improve the performance of cache accesses up to 20% compared to the pure BCH scheme.展开更多
In order to overcome the bit-to-bit interference of the traditional multi-level NAND type device, this paper firstly proposes a novel multi-bit non-uniform channel charge trapping memory （NUC-CTM） device with virtua...In order to overcome the bit-to-bit interference of the traditional multi-level NAND type device, this paper firstly proposes a novel multi-bit non-uniform channel charge trapping memory （NUC-CTM） device with virtual-source NAND-type array architecture, which can effectively restrain the second-bit effect （SBE） and provide 3-bit per cell capability. Owing to the n- buffer region, the SBE induced threshold voltage window shift can be reduced to less than 400 mV and the minimum threshold voltage window between neighboring levels is larger than 750 mV for reliable 3-bit operation. A silicon-rich SiON is also investigated as a trapping layer to improve the retention reliability of the NUC-CTM.展开更多
本文研究了基于1-比特模数转换器(Analog to Digital Converters,ADCs)的大规模多输入多输出(Multiple Input Multiple Output,MIMO)系统上行链路的多用户频率同步问题,其中多个单天线用户与配置大规模天线阵列的基站采用正交频分复用(O...本文研究了基于1-比特模数转换器(Analog to Digital Converters,ADCs)的大规模多输入多输出(Multiple Input Multiple Output,MIMO)系统上行链路的多用户频率同步问题,其中多个单天线用户与配置大规模天线阵列的基站采用正交频分复用(Orthogonal Frequency Division Multiplexing,OFDM)技术进行通信.针对多用户角度不重叠的场景,本文利用接收波束成形网络进行多用户干扰消除,从混叠的多用户信号中提取出目标用户的信息,进而对载波频偏(Carrier Frequency Offset,CFO)进行估计.其次,考虑1-比特ADC导致的量化噪声对系统性能的影响,理论推导了基站接收端处的信噪比(Signal-Noise Ratio,SNR).为了提升系统的性能,基于理论SNR对波束成形网络进行了优化设计.最后,计算机仿真结果显示了所提出的频偏估计算法与其他现有算法相比具有更好的性能.展开更多
Over the last few decades, several all-optical circuits have been proposed to meet the need of high-speed data processing. In some information processing architectures, the role of various analog and digital data comp...Over the last few decades, several all-optical circuits have been proposed to meet the need of high-speed data processing. In some information processing architectures, the role of various analog and digital data comparisons is very important. In this letter, we proposed a multi-bit data comparison scheme. The scheme is based on the switching property of optical nonlinear material. Ultrafast operational speed larger than gigahertz can be expected from this all-optical scheme.展开更多
基金Project supported by the 2nd Stage of Brain KoreaProject supported by the Korea Research Foundation
文摘A multi-bit antifuse-type one-time programmable （OTP） memory is designed, which has a smaller area and a shorter programming time compared with the conventional single-bit antifuse-type OTP memory. While the conventional antifuse-type OTP memory can store a bit per cell, a proposed OTP memory can store two consecutive bits per cell through a data compression technique. The 1 kbit OTP memory designed with Magnachip 0.18 μm CMOS （complementary metal-oxide semiconductor） process is 34% smaller than the conventional single-bit antifuse-type OTP memory since the sizes of cell array and row decoder are reduced. And the programming time of the proposed OTP memory is nearly 50% smaller than that of the conventional counterpart since two consecutive bytes can be compressed and programmed into eight OTP cells at once. The layout area is 214 μm× 327 μ,, and the read current is simulated to be 30.4 μA.
文摘Differential detection of continuous phase modulation suffers from significant intersymbol interference. To reduce bit error rate, multi-branch fractional multi-bit differential detection (MFMDD) with decision feed-back is proposed. By introducing decision feedback in multi-bit differential detected signals, severe inter-symbol interference can be removed. Simulation results show that the proposed structure can greatly im-proves the performance compared with MFMDD without decision feedback, and the performance of 9 FMDD is very near to the performance of the coherent detection.
文摘For the processor working in the radiation environment in space, it tends to suffer from the single event effect on circuits and system failures, due to cosmic rays and high energy particle radiation. Therefore, the reliability of the processor has become an increasingly serious issue. The BCH-based error correction code can correct multibit errors, but it introduces large latency overhead. This paper proposes a hybrid error correction approach that combines BCH and EDAC to correct both multi-bit and single-bit errors for caches with low cost. The proposed technique can correct up to four-bit error, and correct single-bit error in one cycle. Evaluation results show that, the proposed hybrid error-correction scheme can improve the performance of cache accesses up to 20% compared to the pure BCH scheme.
基金Project supported by the National Basic Research Program of China(No.2006CB302700)
文摘In order to overcome the bit-to-bit interference of the traditional multi-level NAND type device, this paper firstly proposes a novel multi-bit non-uniform channel charge trapping memory （NUC-CTM） device with virtual-source NAND-type array architecture, which can effectively restrain the second-bit effect （SBE） and provide 3-bit per cell capability. Owing to the n- buffer region, the SBE induced threshold voltage window shift can be reduced to less than 400 mV and the minimum threshold voltage window between neighboring levels is larger than 750 mV for reliable 3-bit operation. A silicon-rich SiON is also investigated as a trapping layer to improve the retention reliability of the NUC-CTM.
文摘本文研究了基于1-比特模数转换器(Analog to Digital Converters,ADCs)的大规模多输入多输出(Multiple Input Multiple Output,MIMO)系统上行链路的多用户频率同步问题,其中多个单天线用户与配置大规模天线阵列的基站采用正交频分复用(Orthogonal Frequency Division Multiplexing,OFDM)技术进行通信.针对多用户角度不重叠的场景,本文利用接收波束成形网络进行多用户干扰消除,从混叠的多用户信号中提取出目标用户的信息,进而对载波频偏(Carrier Frequency Offset,CFO)进行估计.其次,考虑1-比特ADC导致的量化噪声对系统性能的影响,理论推导了基站接收端处的信噪比(Signal-Noise Ratio,SNR).为了提升系统的性能,基于理论SNR对波束成形网络进行了优化设计.最后,计算机仿真结果显示了所提出的频偏估计算法与其他现有算法相比具有更好的性能.
文摘Over the last few decades, several all-optical circuits have been proposed to meet the need of high-speed data processing. In some information processing architectures, the role of various analog and digital data comparisons is very important. In this letter, we proposed a multi-bit data comparison scheme. The scheme is based on the switching property of optical nonlinear material. Ultrafast operational speed larger than gigahertz can be expected from this all-optical scheme.
