We consider the problem of detecting the community structure in a complex network, groups of nodes with a higher-than-average density of edges connecting them. In this paper we use the simulated annealing strategy to ...We consider the problem of detecting the community structure in a complex network, groups of nodes with a higher-than-average density of edges connecting them. In this paper we use the simulated annealing strategy to maximize the modularity, which has been indicated as a robust benefit function, associating with a shortest-path-based k-means iterative procedure for network partition. The proposed algorithm can not only find the communities, but also identify the nodes which occupy central positions under the metric of the shortest path within the communities to which they belong. The optimal number of communities can be automatically determined without any prior knowledge about the network structure. The applications to both artificial and real-world networks demonstrate the effectiveness of our algorithm.展开更多
Static Random Access Memory(SRAM) based Field Programmable Gate Array(FPGA) is widely applied in the field of aerospace, whose anti-SEU(Single Event Upset) capability becomes more and more important. To improve anti-F...Static Random Access Memory(SRAM) based Field Programmable Gate Array(FPGA) is widely applied in the field of aerospace, whose anti-SEU(Single Event Upset) capability becomes more and more important. To improve anti-FPGA SEU capability, the registers of the circuit netlist are tripled and divided into three categories in this study. By the packing algorithm, the registers of triple modular redundancy are loaded into different configurable logic block. At the same time, the packing algorithm considers the effect of large fan-out nets. The experimental results show that the algorithm successfully realize the packing of the register of Triple Modular Redundancy(TMR). Comparing with Timing Versatile PACKing(TVPACK), the algorithm in this study is able to obtain a 11% reduction of the number of the nets in critical path, and a 12% reduction of the time delay in critical path on average when TMR is not considered. Especially, some critical path delay of circuit can be improved about 33%.展开更多
基金Supported by the National Natural Science Foundation of China(Grant No.10771085)
文摘We consider the problem of detecting the community structure in a complex network, groups of nodes with a higher-than-average density of edges connecting them. In this paper we use the simulated annealing strategy to maximize the modularity, which has been indicated as a robust benefit function, associating with a shortest-path-based k-means iterative procedure for network partition. The proposed algorithm can not only find the communities, but also identify the nodes which occupy central positions under the metric of the shortest path within the communities to which they belong. The optimal number of communities can be automatically determined without any prior knowledge about the network structure. The applications to both artificial and real-world networks demonstrate the effectiveness of our algorithm.
基金Supported by the National Natural Science Foundation of China(No.61106033)
文摘Static Random Access Memory(SRAM) based Field Programmable Gate Array(FPGA) is widely applied in the field of aerospace, whose anti-SEU(Single Event Upset) capability becomes more and more important. To improve anti-FPGA SEU capability, the registers of the circuit netlist are tripled and divided into three categories in this study. By the packing algorithm, the registers of triple modular redundancy are loaded into different configurable logic block. At the same time, the packing algorithm considers the effect of large fan-out nets. The experimental results show that the algorithm successfully realize the packing of the register of Triple Modular Redundancy(TMR). Comparing with Timing Versatile PACKing(TVPACK), the algorithm in this study is able to obtain a 11% reduction of the number of the nets in critical path, and a 12% reduction of the time delay in critical path on average when TMR is not considered. Especially, some critical path delay of circuit can be improved about 33%.
