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An LFSR-based address generator using optimized address partition for low power memory BIST 被引量:1
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作者 YU Zhi-guo LI Qing-qing +1 位作者 FENG Yang GU Xiao-feng 《Journal of Measurement Science and Instrumentation》 CAS CSCD 2020年第3期205-210,共6页
Power consumption in test mode is much higher than that in normal mode,which is prone to causing circuit damage and reducing the yield of chips.To reduce the power dissipation efficiently,a modified linear feedback sh... Power consumption in test mode is much higher than that in normal mode,which is prone to causing circuit damage and reducing the yield of chips.To reduce the power dissipation efficiently,a modified linear feedback shift register(LFSR)is designed to decrease switching activity dramatically during the generation of address sequences for memory built-in self-test(MBIST).The address models are generated by a blend of two address generators with an optimized address partition and two distinct controlled clock signals.An address generator circuit for MBIST of 64 k×32 static random access memory(SRAM)is designed to illustrate the proposed scheme.Experimental results show that when the address bus size is 16 bits,compared with the traditional LFSR,the proposed LFSR can reduce the switching activity and dynamic power by 71.1%and 68.2%,respectively,with low area overhead. 展开更多
关键词 address sequence linear feedback shift register(LFSR) memory built-in self-test(mbist) address generator switching activity
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