This paper presents a standard scalable and reconfigurable design for testability (SR DfT) in order to increase ac- cessibility to deeply embedded A/MS cores and to limit application of costly off-chip mixed-signal te...This paper presents a standard scalable and reconfigurable design for testability (SR DfT) in order to increase ac- cessibility to deeply embedded A/MS cores and to limit application of costly off-chip mixed-signal testers. SR DfT is an oscilla- tion-based wrapper compatible with digital embedded core-based SoC test methodologies. The impact of the optimized oscilla- tion-based wrapper design on MS SoC testing is evaluated in two directions: area and test time. Experimental results are presented for several SoCs from the ITC’02 test benchmarks with inclusion of eight analog filters.展开更多
This paper presents modified version of a realistic test tool suitable to Design For Testability （DFT） and Built-ln Self Test （BIST） environments. A comprehensive tool is developed in the form of a test simulator....This paper presents modified version of a realistic test tool suitable to Design For Testability （DFT） and Built-ln Self Test （BIST） environments. A comprehensive tool is developed in the form of a test simulator. The simulator is capable of providing a required goal of test for the Circuit Under Test （CUT）. The simulator uses the approach of fault diagnostics with fault grading procedures to provide the optimum tests. The current version of the simulator embeds features of exhaustive and pseudo-random test generation schemes along with the search solutions of cost effective test goals. The simulator provides facilities of realizing all possible pseudo-random sequence generators with all possible combinations of seeds. The tool is developed on a common Personal Computer （PC） platform and hence no special software is required. Thereby, it is a low cost tool hence economical. The tool is very much suitable for determining realistic test sequences for a targeted goal of testing for any CUT. The developed tool incorporates flexible Graphical User Interface （GUI） procedures and can be operated without any special programming skill. The tool is debugged and tested with the results of many bench mark circuits. Further, this developed tool can be utilized for educational purposes for many courses such as fault-tolerant computing, fault diagnosis, digital electronics, and safe-reliable-testable digital logic designs.展开更多
文摘This paper presents a standard scalable and reconfigurable design for testability (SR DfT) in order to increase ac- cessibility to deeply embedded A/MS cores and to limit application of costly off-chip mixed-signal testers. SR DfT is an oscilla- tion-based wrapper compatible with digital embedded core-based SoC test methodologies. The impact of the optimized oscilla- tion-based wrapper design on MS SoC testing is evaluated in two directions: area and test time. Experimental results are presented for several SoCs from the ITC’02 test benchmarks with inclusion of eight analog filters.
文摘This paper presents modified version of a realistic test tool suitable to Design For Testability （DFT） and Built-ln Self Test （BIST） environments. A comprehensive tool is developed in the form of a test simulator. The simulator is capable of providing a required goal of test for the Circuit Under Test （CUT）. The simulator uses the approach of fault diagnostics with fault grading procedures to provide the optimum tests. The current version of the simulator embeds features of exhaustive and pseudo-random test generation schemes along with the search solutions of cost effective test goals. The simulator provides facilities of realizing all possible pseudo-random sequence generators with all possible combinations of seeds. The tool is developed on a common Personal Computer （PC） platform and hence no special software is required. Thereby, it is a low cost tool hence economical. The tool is very much suitable for determining realistic test sequences for a targeted goal of testing for any CUT. The developed tool incorporates flexible Graphical User Interface （GUI） procedures and can be operated without any special programming skill. The tool is debugged and tested with the results of many bench mark circuits. Further, this developed tool can be utilized for educational purposes for many courses such as fault-tolerant computing, fault diagnosis, digital electronics, and safe-reliable-testable digital logic designs.
