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温度对14nm FinFET SRAM单粒子效应的影响
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作者 谭钧元 郭刚 +4 位作者 张付强 江宜蓓 陈启明 韩金华 秦丰迪 《半导体技术》 北大核心 2026年第1期87-93,共7页
由于鳍式场效应晶体管静态随机存储器(FinFET SRAM)特有的鳍片电荷共享机制,其对单粒子效应(SEE)呈现出与传统平面器件截然不同的敏感特性。利用TCAD仿真构建14 nm FinFET SRAM模型并结合重离子实验加以验证,研究了温度对14 nm FinFET S... 由于鳍式场效应晶体管静态随机存储器(FinFET SRAM)特有的鳍片电荷共享机制,其对单粒子效应(SEE)呈现出与传统平面器件截然不同的敏感特性。利用TCAD仿真构建14 nm FinFET SRAM模型并结合重离子实验加以验证,研究了温度对14 nm FinFET SRAM电荷收集机制的影响。结果表明,随着温度的升高,高线性能量转移(LET)离子诱导的电荷收集过程逐渐减弱,多节点电荷收集现象也会逐渐减弱,且当环境温度达到125℃临界值时,敏感节点会出现收集电荷的雪崩式累积现象。此外,随着温度的升高,器件的翻转截面从1.27×10^(-3)cm^(2)增大到1.81×10^(-3)cm^(2),增大了约43%,且在高温下翻转截面的增大趋势愈发显著,该结果与仿真结果良好吻合。 展开更多
关键词 鳍式场效应晶体管静态随机存储器(FinFET sram) 单粒子效应(SEE) 电荷收集 TCAD 温度
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基于FPGA的QDR Ⅱ+型同步SRAM测试系统的设计与实现
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作者 石珂 张萌 +1 位作者 张新港 孙杰杰 《电子与封装》 2026年第2期19-26,共8页
四倍数据速率(QDR)Ⅱ+型同步静态随机存取存储器(SRAM)是一种高可靠性、高速、低功耗的新型存储器,广泛应用于工业以太网、物联网、交换机、服务器等网络设备。相比于传统的双倍数据速率(DDR)存储器,QDR存储器的数据输入和输出总线相互... 四倍数据速率(QDR)Ⅱ+型同步静态随机存取存储器(SRAM)是一种高可靠性、高速、低功耗的新型存储器,广泛应用于工业以太网、物联网、交换机、服务器等网络设备。相比于传统的双倍数据速率(DDR)存储器,QDR存储器的数据输入和输出总线相互独立,并且能够分别在时钟的上升沿和下降沿对数据进行操作,使得QDRⅡ+型同步SRAM能够拥有更高的数据吞吐量。同时因为没有了复杂的动态刷新逻辑,其功耗相对于DDR器件也显著降低,更加适合高速通信和高速网络的应用。但是,超高的工作频率与超大的存储深度使得QDRⅡ+型同步SRAM的板级性能评估和应用成为一个急需解决的问题。以Cypress公司的CY7C1645KV18芯片为对象,通过设计一套以Xilinx公司XC7K325T FPGA为主控的单板测试系统,对QDRⅡ+型同步SRAM的板级特性进行有效的评估。 展开更多
关键词 QDRⅡ+型同步sram FPGA 板级测试 CY7C1645KV18
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Uniform Attractors for the Kirchhoff Type Suspension Bridge Equation with Nonlinear Damping and Memory Term
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作者 Ling XU Yanni WANG 《Journal of Mathematical Research with Applications》 2026年第1期71-86,共16页
The goal of this paper is to investigate the long-time dynamics of solutions to a Kirchhoff type suspension bridge equation with nonlinear damping and memory term.For this problem we establish the well-posedness and e... The goal of this paper is to investigate the long-time dynamics of solutions to a Kirchhoff type suspension bridge equation with nonlinear damping and memory term.For this problem we establish the well-posedness and existence of uniform attractor under some suitable assumptions on the nonlinear term g(u),the nonlinear damping f(u_(t))and the external force h(x,t).Specifically,the asymptotic compactness of the semigroup is verified by the energy reconstruction method. 展开更多
关键词 uniform attractor Kirchhoff type suspension bridge equation nonlinear damping memory term
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Restoration of Extrasynaptic/Synaptic GABA_(A)R-α5 Localization Improves Sevoflurane-Induced Early Memory Impairment in Aged Mice
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作者 Mengxue Zhang Xiaokun Wang +5 位作者 Zhun Wang Jinpeng Dong Sixuan Wang Ying Dong Changyu Jiang Yiqing Yin 《Neuroscience Bulletin》 2026年第2期301-318,共18页
GABA_(A) receptors containingα5-subunits(GABA_(A)R-α5)cluster at both extrasynaptic and synaptic locations,interacting with the scaffold proteins radixin and gephyrin,respectively,and the re-localization of GABA_(A... GABA_(A) receptors containingα5-subunits(GABA_(A)R-α5)cluster at both extrasynaptic and synaptic locations,interacting with the scaffold proteins radixin and gephyrin,respectively,and the re-localization of GABA_(A)R-α5 influences GABAergic transmission.Here,we found that when early spatial memory deficits occurred in aged mice at 24 h after sevoflurane anesthesia,there was a re-localization of GABA_(A)R-α5 that enhanced tonic inhibition and reduced the decay kinetics of miniature inhibitory postsynaptic currents in the hippocampal CA1 region.Mechanistically,increased phosphorylation of radixin at threonine 564(Thr564)mediates the re-localization of GABA_(A)R-α5.Acute treatment with the selective extrasynaptic GABA_(A)R-α5 antagonist S44819 restored the GABA_(A)R-α5-mediated inhibitory currents by reversing radixin phosphorylation-dependent GABA_(A)R-α5 re-localization,then improved the sevoflurane-induced spatial memory impairment in aged mice.Our results suggest that the localization of GABA_(A)R-α5 altered by sevoflurane is linked to unbalanced GABAergic transmission,which induces early memory impairment in aged mice.Modulating the GABA_(A)R-α5 localization might be a novel strategy to improve memory after sevoflurane exposure. 展开更多
关键词 Aging SEVOFLURANE memory GABA_(A)R-α5 HIPPOCAMPUS
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Real-time decision support for bolter recovery safety:Long short-term memory network-driven aircraft sequencing
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作者 Wei Han Changjiu Li +4 位作者 Xichao Su Yong Zhang Fang Guo Tongtong Yu Xuan Li 《Defence Technology(防务技术)》 2026年第2期184-205,共22页
The highly dynamic nature,strong uncertainty,and coupled multiple safety constraints inherent in carrier aircraft recovery operations pose severe challenges for real-time decision-making.Addressing bolter scenarios,th... The highly dynamic nature,strong uncertainty,and coupled multiple safety constraints inherent in carrier aircraft recovery operations pose severe challenges for real-time decision-making.Addressing bolter scenarios,this study proposes an intelligent decision-making framework based on a deep long short-term memory Q-network.This framework transforms the real-time sequencing for bolter recovery problem into a partially observable Markov decision process.It employs a stacked long shortterm memory network to accurately capture the long-range temporal dependencies of bolter event chains and fuel consumption.Furthermore,it integrates a prioritized experience replay training mechanism to construct a safe and adaptive scheduling system capable of millisecond-level real-time decision-making.Experimental demonstrates that,within large-scale mass recovery scenarios,the framework achieves zero safety violations in static environments and maintains a fuel safety violation rate below 10%in dynamic scenarios,with single-step decision times at the millisecond level.The model exhibits strong generalization capability,effectively responding to unforeseen emergent situations—such as multiple bolters and fuel emergencies—without requiring retraining.This provides robust support for efficient carrier-based aircraft recovery operations. 展开更多
关键词 Carrier-based aircraft Recovery scheduling Deep reinforcement learning Long short-term memory networks Dynamic real-time decision-making
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新型低电压SRAM读写辅助电路设计
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作者 刘勇 彭春雨 《中国集成电路》 2025年第1期54-58,64,共6页
随着微处理器对低功耗与高能效需求的增长,SRAM作为其主要功耗与面积来源,优化SRAM功耗至关重要。降低电源电压是降低功耗的重要方法,但也会严重影响SRAM的读写性能。针对此问题,本文提出了一种新型读写辅助电路结构,该结构可以增强写... 随着微处理器对低功耗与高能效需求的增长,SRAM作为其主要功耗与面积来源,优化SRAM功耗至关重要。降低电源电压是降低功耗的重要方法,但也会严重影响SRAM的读写性能。针对此问题,本文提出了一种新型读写辅助电路结构,该结构可以增强写入能力和加快位线放电速度。此电路通过在写入期间将字线电压先升至欠驱电压后升至过驱电压,以在确保稳定性的同时加强写能力;在读取时,轻微提高字线电压至高于VDD电压,从而加快位线放电速度,增大两条位线电压差值,从而提高SRAM的可靠性。仿真结果表明,提出的结构可以将最小工作电压降低至0.4V,相比未使用辅助电路的结构写能力提升一倍以上,字线打开相同的一段时间,两条位线电压差值可以增加40%以上。相比于传统结构在各自最小电压下功耗可降低20%以上,而相比于在标准电压下的传统结构,功耗可降低70%以上,且只增大3%的面积。 展开更多
关键词 低电压 低功耗 静态随机存取存储器(sram) 读写辅助电路
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A review on SRAM-based computing in-memory:Circuits,functions,and applications 被引量:5
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作者 Zhiting Lin Zhongzhen Tong +8 位作者 Jin Zhang Fangming Wang Tian Xu Yue Zhao Xiulong Wu Chunyu Peng Wenjuan Lu Qiang Zhao Junning Chen 《Journal of Semiconductors》 EI CAS CSCD 2022年第3期22-46,共25页
Artificial intelligence(AI)processes data-centric applications with minimal effort.However,it poses new challenges to system design in terms of computational speed and energy efficiency.The traditional von Neumann arc... Artificial intelligence(AI)processes data-centric applications with minimal effort.However,it poses new challenges to system design in terms of computational speed and energy efficiency.The traditional von Neumann architecture cannot meet the requirements of heavily datacentric applications due to the separation of computation and storage.The emergence of computing inmemory(CIM)is significant in circumventing the von Neumann bottleneck.A commercialized memory architecture,static random-access memory(SRAM),is fast and robust,consumes less power,and is compatible with state-of-the-art technology.This study investigates the research progress of SRAM-based CIM technology in three levels:circuit,function,and application.It also outlines the problems,challenges,and prospects of SRAM-based CIM macros. 展开更多
关键词 static random-access memory(sram) artificial intelligence(AI) von Neumann bottleneck computing in-memory(CIM) convolutional neural network(CNN)
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A Low Power SRAM/SOI Memory Cell Design
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作者 于洋 赵骞 邵志标 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2006年第2期318-322,共5页
A modified four transistor (4T) self-body-bias structured SRAM/SOI memory cell is proposed. The structure is designed and its parameters are obtained by performance simulation and analysis with TSUPREM4 and MEDICI.T... A modified four transistor (4T) self-body-bias structured SRAM/SOI memory cell is proposed. The structure is designed and its parameters are obtained by performance simulation and analysis with TSUPREM4 and MEDICI.The structure saves area and its process is simplified by using the body resistor with buried p^+ channel beneath the nMOS gate instead of the pMOS of 6T CMOS SRAM. Furthermore, this structure can operate safely with a 0.5V supply voltage, which may be prevalent in the near future. Finally, compared to conventional 6T CMOS SRAM,this structure's transient responses are normal and its power dissipation is 10 times smaller. 展开更多
关键词 sram/SOI memory cell self body bias low power
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混洗SRAM:SRAM中的并行按位数据混洗 被引量:1
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作者 张敦博 曾灵灵 +2 位作者 王若曦 王耀华 沈立 《计算机研究与发展》 北大核心 2025年第1期75-89,共15页
向量处理单元(vector processing unit,VPU)已被广泛应用于神经网络、信号处理和高性能计算等处理器设计中,但其总体性能仍受限于专门用于对齐数据的混洗操作.传统上,处理器使用其数据混洗单元来处理混洗操作.然而,使用数据混洗单元来... 向量处理单元(vector processing unit,VPU)已被广泛应用于神经网络、信号处理和高性能计算等处理器设计中,但其总体性能仍受限于专门用于对齐数据的混洗操作.传统上,处理器使用其数据混洗单元来处理混洗操作.然而,使用数据混洗单元来处理混洗指令将带来昂贵的数据移动开销,并且数据混洗单元只能串行混洗数据.事实上,混洗操作只会改变数据的布局,理想情况下混洗操作应在内存中完成.随着存内计算技术的发展,SRAM不仅可以作为存储部件,同时还能作为计算单元.为了实现存内混洗,提出了混洗SRAM,它可以在SRAM体中逐位地并行混洗多个向量.混洗SRAM的关键思想是利用SRAM体中位线的数据移动能力来改变数据的布局.这样SRAM体中位于同一位线上不同数据的相同位可以同时被移动,从而使混洗操作拥有高度的并行性.通过适当的数据布局和向量混洗扩展指令的支持,混洗SRAM可以高效地处理常用的混洗操作.评测结果表明,对于常用的混洗操作,混洗SRAM可以实现平均28倍的性能增益,对于FFT,AlexNet,VggNet等实际的应用,可以实现平均3.18倍的性能增益.混洗SRAM相较于传统SRAM的面积开销仅增加了4.4%. 展开更多
关键词 向量单指令多数据体系结构 静态随机访问存储器 混洗操作 向量内存 存内计算
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基于多元混合编码的SRAM数字存算一体宏设计
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作者 郭瑞琦 杨卓航 +4 位作者 陈销丰 王磊 王扬 胡杨 尹首一 《计算机工程与科学》 北大核心 2025年第12期2099-2107,共9页
存算一体芯片技术被认为是有望解决处理器芯片“存储墙”瓶颈,大幅提升人工智能算力能效和算力密度的关键技术和重要解决方案。提出了一款新型的数字式SRAM存算一体宏单元架构,利用权重数据、激励数据混合编码的方式优化功耗开销,提升... 存算一体芯片技术被认为是有望解决处理器芯片“存储墙”瓶颈,大幅提升人工智能算力能效和算力密度的关键技术和重要解决方案。提出了一款新型的数字式SRAM存算一体宏单元架构,利用权重数据、激励数据混合编码的方式优化功耗开销,提升芯片能效;并针对核心加法树电路进行了一系列电路层级的优化,提升芯片的面积效率。在TSMC28nm工艺库下,对所提出的数字式SRAM存算单元进行了仿真验证,测试模型为ResNet20。结果显示,在0.9V,250MHz下,混合编码优化可以提升2.17倍的能效;通过加法树优化可以将存算一体单元的面积减少14.2%;处理ResNet20模型时,256×64的存算阵列可以实现20.83TOPS/W能效。 展开更多
关键词 人工智能 sram 数字存算一体 混合编码 加法树优化
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SRAM型FPGA微系统故障分析及测试覆盖性研究
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作者 张宇飞 华更新 +3 位作者 赵亚飞 刘群 张帆 李勇 《微电子学与计算机》 2025年第10期158-167,共10页
基于系统级封装(System in a Package, SiP)技术的SRAM型FPGA微系统广泛应用于航天领域。由于微系统复杂的封装结构,限制了大多数传统失效分析设备与分析方式的应用。针对微系统器件的故障诊断困难、测试流程复杂等可靠性问题,开展了常... 基于系统级封装(System in a Package, SiP)技术的SRAM型FPGA微系统广泛应用于航天领域。由于微系统复杂的封装结构,限制了大多数传统失效分析设备与分析方式的应用。针对微系统器件的故障诊断困难、测试流程复杂等可靠性问题,开展了常见故障分析研究。对SRAM配置固有缺陷和FPGA内部配置刷新电路异常等典型故障的产生机理进行了深入分析和总结。结合理论分析和问题现象,提出了配置位回读校验测试及比对、辅助电源VCC, AUX电流参数一致性控制等测试筛选方法,有效提升了测试覆盖性。利用相应测试手段和数据分析方法,可精准定位失效机理与失效部位,对后续宇航用SRAM型FPGA微系统应用及筛选有重要意义。 展开更多
关键词 sram型FPGA 微系统 故障分析 测试覆盖性
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一款基于PKUCNTFET工艺的SRAM编译器
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作者 王景麟 陈祉延 +1 位作者 袁珩洲 陈小文 《集成电路与嵌入式系统》 2025年第11期47-53,共7页
碳基电子器件凭借高载流子迁移率成为突破硅基集成电路物理极限的重要路径。然而,其核心工艺平台(如PKUCNTFET)尚未成熟,设计规则与传统硅基工艺差异显著,导致现有硅基SRAM编译器无法复用。SRAM作为处理器关键部件,在碳基研发中仍依赖... 碳基电子器件凭借高载流子迁移率成为突破硅基集成电路物理极限的重要路径。然而,其核心工艺平台(如PKUCNTFET)尚未成熟,设计规则与传统硅基工艺差异显著,导致现有硅基SRAM编译器无法复用。SRAM作为处理器关键部件,在碳基研发中仍依赖耗时的手工设计,严重制约了碳基处理器与存储器的开发。文中首次提出并实现了一款面向碳基工艺的可重构SRAM编译器,创新性地采用全定制单元设计,构建基本复用器件模块,并基于模块化架构(参数解析→电路生成→版图输出)实现全流程自动化。通过集成Hanan网格算法优化多层互连,结合A*搜索与通孔碰撞检测降低布线延迟,有效解决了碳基工艺适配与多工作模式灵活配置的核心挑战。实验结果表明,编译器生成的SRAM阵列通过严格LVS/DRC检查,支持单端口读/写、双端口同步读/写及一读一写三种可配置工作模式,可自动生成8~256位宽、64~4096位深度的阵列,并覆盖27个PVT工艺角的Liberty时序建模,为碳基集成电路的实验室开发提供了高效、自主可控的存储解决方案。 展开更多
关键词 碳基集成电路 sram编译器 sram存储器 可重构架构
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多重散射对40nm SRAM和3D-SRAM单粒子翻转的影响
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作者 罗云龙 李刚 张宇 《安徽大学学报(自然科学版)》 北大核心 2025年第1期53-60,共8页
基于RPP(rectangular parallelepiped)模型,利用Geant4软件包,构建了一个40 nm SRAM器件模型用于单粒子翻转效应模拟,通过Weibull函数拟合得到σ_(sat)和LET_(th)分别为8.98×10^(-9)cm^(2)·bit^(-1)和0.084 MeV/(mg·cm^(... 基于RPP(rectangular parallelepiped)模型,利用Geant4软件包,构建了一个40 nm SRAM器件模型用于单粒子翻转效应模拟,通过Weibull函数拟合得到σ_(sat)和LET_(th)分别为8.98×10^(-9)cm^(2)·bit^(-1)和0.084 MeV/(mg·cm^(-2)).基于3D-IC技术设计了一种新的3D-SRAM器件,通过Geant4进行了建模和单粒子翻转模拟,结果表明,在同一3D-SRAM器件中上层单元对下层单元有防护作用.通过改变覆盖层中的高Z材料,发现高Z材料可以有效地减少Fe离子在射程末端的多重散射,且Ta的效果优于W.在同一3D-SRAM器件中,下层单元(die3)的多重散射截面峰值更低. 展开更多
关键词 GEANT4 单粒子翻转 多重散射 3D-sram
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ROM SRAM混合存内计算架构综述 被引量:1
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作者 杜禧瑞 尹国栋 +4 位作者 陈一鸣 曾令安 于天熠 杨华中 李学清 《集成电路与嵌入式系统》 2025年第8期10-22,共13页
神经网络是人工智能的代表性算法,然而其庞大的参数量对其在边缘端的硬件部署提出了新的挑战。在边缘端,一方面,为了应用的灵活性,要求计算硬件能够通过模型参数的微调来实现网络在任务间的迁移;另一方面,为了计算能效和性能,需要实现... 神经网络是人工智能的代表性算法,然而其庞大的参数量对其在边缘端的硬件部署提出了新的挑战。在边缘端,一方面,为了应用的灵活性,要求计算硬件能够通过模型参数的微调来实现网络在任务间的迁移;另一方面,为了计算能效和性能,需要实现大容量的片上存储以减少片外访存开销。近期提出的ROM-SRAM混合存内计算架构是在成熟CMOS工艺下很有潜力的一种方案。得益于高密度ROM存内计算,神经网络的大部分权重可以部署在片内而不依赖片外访存;与此同时,SRAM存内计算可以为基于高密度ROM的边缘端存内计算提供灵活性。为了扩展ROM-SRAM混合存内计算架构设计和应用的空间,需要进一步提高ROM存内计算的密度以支持更大的网络,并探索通过少量SRAM存内计算获得更大灵活性的方案。文中介绍了几种常见的提升ROM存内计算密度的方法,以及基于ROM-SRAM混合存内计算架构的神经网络微调以提升灵活性的方法,并讨论了超大规模神经网络的部署方案和长序列大语言模型中遇到的动态矩阵乘瓶颈的解决方案,展望了ROM-SRAM混合存内计算架构广阔的设计空间和应用前景。 展开更多
关键词 人工智能 神经网络加速器 存内计算 只读存储器 集成电路
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面向模拟SRAM存算一体芯片的数字接口设计 被引量:1
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作者 孔鹤霖 魏知行 +1 位作者 陈挺然 潘彪 《集成电路与嵌入式系统》 2025年第7期1-8,共8页
针对模拟存算一体芯片设计中仿真验证难题,提出一种创新的数字接口设计方案,旨在提高大规模计算场景下的仿真效率。该方案分析SRAM存算一体原理,将SPICE模型与数字控制电路结合,利用数字方法完成模拟存算一体设计的仿真验证,从而提升开... 针对模拟存算一体芯片设计中仿真验证难题,提出一种创新的数字接口设计方案,旨在提高大规模计算场景下的仿真效率。该方案分析SRAM存算一体原理,将SPICE模型与数字控制电路结合,利用数字方法完成模拟存算一体设计的仿真验证,从而提升开发效率。为验证方案的有效性,构建评估体系,对比数字接口仿真与传统模拟电路仿真。结果显示,新方案仿真速度提升2倍以上,配置效率提升1000倍以上,优势显著。该研究获得科技部重点研发计划(2021YFB3601300)支持,已在180nm工艺节点完成流片验证,证实了数字接口设计方案在大规模计算场景下仿真存算一体设计的效率优势。 展开更多
关键词 神经网络 存算一体 数模混合仿真 模拟sram
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Comprehensive performance analysis of CMOS and CNTFET based 8T SRAM cell
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作者 Mahamudul Hassan Fuad Md Faysal Nayan +2 位作者 Sheikh Shahrier Noor Rahbaar Yeassin Russel Reza Mahmud 《Journal of Electronic Science and Technology》 2025年第2期31-44,共14页
In recent years,carbon nanotube field effect transistor(CNTFET)has become an attractive alternative to silicon for designing high-performance,highly stable,and low-power static random access memory(SRAM).SRAM serves a... In recent years,carbon nanotube field effect transistor(CNTFET)has become an attractive alternative to silicon for designing high-performance,highly stable,and low-power static random access memory(SRAM).SRAM serves as a cache memory in computers and many portable devices.Carbon nanotubes(CNTs),because of their exceptional transport capabilities,outstanding thermal conductivities,and impressive current handling capacities,have demonstrated great potential as an alternative device to the standard complementary metal-oxide-semiconductor(CMOS).The SRAM cell design using CNTFET is being compared to SRAM cell designs built using traditional CMOS technology.This paper presents the comprehensive analysis of CMOS&CNTFET based 8T SRAM cell design.Because of the nanoscale size,ballistic transport,and higher carrier mobility of the semiconducting nanotubes in CNTFET,it is integrated into the 8T SRAM cell.The approach incorporates several nonidealities,including the presence of quantum confinement consequences in the peripheral and transverse prescriptions,acoustic and transparent photon diffraction in the region surrounding the channel,as well as the screening effects by parallel CNTs in CNTFETs with multiple CNTs.By incorporating Stanford University CNTFET model in CADENCE(virtuoso)32 nm simulation,we have found that CNTFET SRAM cell is 4 times faster in terms of write/read delay and the write/read power delay product(PDP)value is almost 5 times lower compared to CMOS based SRAM.We have also analyzed the effect of temperature&different tube positions of CNTs on the performance evaluation of the 8T SRAM cell. 展开更多
关键词 Carbon nanotube field effect transistor(CNTFET) Power delay product(PDP) Static random access memory(sram) Temperature Tube position Write/read delay
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Back-gate bias and supply voltage dependency on the single-event upset susceptibility of 6 T CSOI-SRAM
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作者 Li-Wen Yao Jin-Hu Yang +12 位作者 Yu-Zhu Liu Bo Li Yang Jiao Shi-Wei Zhao Qi-Yu Chen Xin-Yu Li Tian-Qi Wang Fan-Yu Liu Jian-Tou Gao Jian-Li Liu Xing-Ji Li Jie Liu Pei-Xiong Zhao 《Nuclear Science and Techniques》 2025年第9期105-115,共11页
This paper explores the impact of back-gate bias (V_(soi)) and supply voltage (V_(DD)) on the single-event upset (SEU) cross section of 0.18μm configurable silicon-on-insulator static random-access memory (SRAM) unde... This paper explores the impact of back-gate bias (V_(soi)) and supply voltage (V_(DD)) on the single-event upset (SEU) cross section of 0.18μm configurable silicon-on-insulator static random-access memory (SRAM) under high linear energy transfer heavyion experimentation.The experimental findings demonstrate that applying a negative back-gate bias to NMOS and a positive back-gate bias to PMOS enhances the SEU resistance of SRAM.Specifically,as the back-gate bias for N-type transistors(V_(nsoi)) decreases from 0 to-10 V,the SEU cross section decreases by 93.23%,whereas an increase in the back-gate bias for P-type transistors (V_(psoi)) from 0 to 10 V correlates with an 83.7%reduction in SEU cross section.Furthermore,a significant increase in the SEU cross section was observed with increase in supply voltage,as evidenced by a 159%surge at V_(DD)=1.98 V compared with the nominal voltage of 1.8 V.To explore the physical mechanisms underlying these experimental data,we analyzed the dependence of the critical charge of the circuit and the collected charge on the bias voltage by simulating SEUs using technology computer-aided design. 展开更多
关键词 Single-event upset(SEU) Static random-access memory(sram) Back-gate voltage Supply voltage
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Streamlined photonic reservoir computer with augmented memory capabilities 被引量:4
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作者 Changdi Zhou Yu Huang +5 位作者 Yigong Yang Deyu Cai Pei Zhou Kuenyao Lau Nianqiang Li Xiaofeng Li 《Opto-Electronic Advances》 2025年第1期45-57,共13页
Photonic platforms are gradually emerging as a promising option to encounter the ever-growing demand for artificial intelligence,among which photonic time-delay reservoir computing(TDRC)is widely anticipated.While suc... Photonic platforms are gradually emerging as a promising option to encounter the ever-growing demand for artificial intelligence,among which photonic time-delay reservoir computing(TDRC)is widely anticipated.While such a computing paradigm can only employ a single photonic device as the nonlinear node for data processing,the performance highly relies on the fading memory provided by the delay feedback loop(FL),which sets a restriction on the extensibility of physical implementation,especially for highly integrated chips.Here,we present a simplified photonic scheme for more flexible parameter configurations leveraging the designed quasi-convolution coding(QC),which completely gets rid of the dependence on FL.Unlike delay-based TDRC,encoded data in QC-based RC(QRC)enables temporal feature extraction,facilitating augmented memory capabilities.Thus,our proposed QRC is enabled to deal with time-related tasks or sequential data without the implementation of FL.Furthermore,we can implement this hardware with a low-power,easily integrable vertical-cavity surface-emitting laser for high-performance parallel processing.We illustrate the concept validation through simulation and experimental comparison of QRC and TDRC,wherein the simpler-structured QRC outperforms across various benchmark tasks.Our results may underscore an auspicious solution for the hardware implementation of deep neural networks. 展开更多
关键词 photonic reservoir computing machine learning vertical-cavity surface-emitting laser quasi-convolution coding augmented memory capabilities
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纳米级SRAM多位翻转检纠错方法实现
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作者 薛国凤 安军社 周昌义 《哈尔滨工业大学学报》 北大核心 2025年第9期39-45,共7页
为解决纳米级SRAM(100 nm以内工艺)在航天工程应用中出现的多位翻转问题,依据纳米级SRAM的翻转特性,在传统串行编译码的基础上优化改进,采用并行编译码的方式,实现了基于RS(12,8,4)码的纳米级SRAM的加固方法,在单时钟节拍内实现编译码... 为解决纳米级SRAM(100 nm以内工艺)在航天工程应用中出现的多位翻转问题,依据纳米级SRAM的翻转特性,在传统串行编译码的基础上优化改进,采用并行编译码的方式,实现了基于RS(12,8,4)码的纳米级SRAM的加固方法,在单时钟节拍内实现编译码输出。以FPGA为平台,验证该加固方法的延时和纠错能力。测试结果表明:与Xilinx自带的可检二纠一汉明码的块RAM相比,本文提出的方法访问延时相近,但纠错能力是汉明码的5~8倍;与FUEC-QUAEC、CLC等编译码方法相比,将连续5 bit翻转错误的纠正率提高到100%。采用并行编译码实现的基于RS(12,8,4)码加固方法可用于纳米级SRAM抗多位翻转加固,以较小的延时代价实现纠正一个码字(48 bit)内任意两个符号(最多8 bit)内的错误,可完全纠正空间单粒子环境中出现的单个字内连续5 bit翻转的错误。该加固方法可扩展应用到CPU外部存储器的访问控制以及CPU内部cache的加固,以解决现有航天处理器采用检二纠一码无法纠正其cache多位翻转错误的问题。 展开更多
关键词 单粒子效应 多位翻转 RS编码 纳米级sram
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Regulator of G protein signaling 6 mediates exercise-induced recovery of hippocampal neurogenesis,learning,and memory in a mouse model of Alzheimer’s disease 被引量:1
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作者 Mackenzie M.Spicer Jianqi Yang +5 位作者 Daniel Fu Alison N.DeVore Marisol Lauffer Nilufer S.Atasoy Deniz Atasoy Rory A.Fisher 《Neural Regeneration Research》 SCIE CAS 2025年第10期2969-2981,共13页
Hippocampal neuronal loss causes cognitive dysfunction in Alzheimer’s disease.Adult hippocampal neurogenesis is reduced in patients with Alzheimer’s disease.Exercise stimulates adult hippocampal neurogenesis in rode... Hippocampal neuronal loss causes cognitive dysfunction in Alzheimer’s disease.Adult hippocampal neurogenesis is reduced in patients with Alzheimer’s disease.Exercise stimulates adult hippocampal neurogenesis in rodents and improves memory and slows cognitive decline in patients with Alzheimer’s disease.However,the molecular pathways for exercise-induced adult hippocampal neurogenesis and improved cognition in Alzheimer’s disease are poorly understood.Recently,regulator of G protein signaling 6(RGS6)was identified as the mediator of voluntary running-induced adult hippocampal neurogenesis in mice.Here,we generated novel RGS6fl/fl;APP_(SWE) mice and used retroviral approaches to examine the impact of RGS6 deletion from dentate gyrus neuronal progenitor cells on voluntary running-induced adult hippocampal neurogenesis and cognition in an amyloid-based Alzheimer’s disease mouse model.We found that voluntary running in APP_(SWE) mice restored their hippocampal cognitive impairments to that of control mice.This cognitive rescue was abolished by RGS6 deletion in dentate gyrus neuronal progenitor cells,which also abolished running-mediated increases in adult hippocampal neurogenesis.Adult hippocampal neurogenesis was reduced in sedentary APP_(SWE) mice versus control mice,with basal adult hippocampal neurogenesis reduced by RGS6 deletion in dentate gyrus neural precursor cells.RGS6 was expressed in neurons within the dentate gyrus of patients with Alzheimer’s disease with significant loss of these RGS6-expressing neurons.Thus,RGS6 mediated voluntary running-induced rescue of impaired cognition and adult hippocampal neurogenesis in APP_(SWE) mice,identifying RGS6 in dentate gyrus neural precursor cells as a possible therapeutic target in Alzheimer’s disease. 展开更多
关键词 adult hippocampal neurogenesis Alzheimer’s disease dentate gyrus EXERCISE learning/memory neural precursor cells regulator of G protein signaling 6(RGS6)
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