以磁盘冗余阵列(Redundant Array of Inexpensive Disks,RAID)技术中新出现的P-code编码为主要对象,进行了其构造方法、编码及译码算法的详细分析,并首次运用位矩阵(Binary Distribution Matrix,BDM)的方法分析和研究了P-code码。在此...以磁盘冗余阵列(Redundant Array of Inexpensive Disks,RAID)技术中新出现的P-code编码为主要对象,进行了其构造方法、编码及译码算法的详细分析,并首次运用位矩阵(Binary Distribution Matrix,BDM)的方法分析和研究了P-code码。在此基础上,对当前主要RAID-6编码的扩展即更多磁盘数量的容错问题进行了总结与探讨,提出了P-code等垂直最大距离可分码(Maximum Distance Separable,MDS)的扩展将是该领域未来研究的新方向和难点。展开更多
In the light of the increasingly serious I/O bottleneck problem, the paper puts forward a method named RAID-M (RAID Matrix) to build high performance mass storage from cheap PC components based on the idea of multi-ch...In the light of the increasingly serious I/O bottleneck problem, the paper puts forward a method named RAID-M (RAID Matrix) to build high performance mass storage from cheap PC components based on the idea of multi-channel I/O and parallel access. Theoretical analyses prove that different RAID-M configurations vary their performance, space utilization and reliability, meeting various application goals. Experiments show that both the sequential read performance and sequential write performance of a RAID-M prototype machine have broken through the limitation of 32 bit/33 MHz PCI bus.展开更多
文摘以磁盘冗余阵列(Redundant Array of Inexpensive Disks,RAID)技术中新出现的P-code编码为主要对象,进行了其构造方法、编码及译码算法的详细分析,并首次运用位矩阵(Binary Distribution Matrix,BDM)的方法分析和研究了P-code码。在此基础上,对当前主要RAID-6编码的扩展即更多磁盘数量的容错问题进行了总结与探讨,提出了P-code等垂直最大距离可分码(Maximum Distance Separable,MDS)的扩展将是该领域未来研究的新方向和难点。
基金the National Natural Science Foundation of China(Grant No.60403043) the Doctorate Foundation of Tsinghua University.
文摘In the light of the increasingly serious I/O bottleneck problem, the paper puts forward a method named RAID-M (RAID Matrix) to build high performance mass storage from cheap PC components based on the idea of multi-channel I/O and parallel access. Theoretical analyses prove that different RAID-M configurations vary their performance, space utilization and reliability, meeting various application goals. Experiments show that both the sequential read performance and sequential write performance of a RAID-M prototype machine have broken through the limitation of 32 bit/33 MHz PCI bus.
