The circuit testable realizations of multiple-valued functions are studied in this letter. First of all,it is shown that one vector detects all skew faults in multiplication modulo circuits or in addi-tion modulo circ...The circuit testable realizations of multiple-valued functions are studied in this letter. First of all,it is shown that one vector detects all skew faults in multiplication modulo circuits or in addi-tion modulo circuits,and n+1 vectors detect all skew faults in the circuit realization of multiple-valued functions with n inputs. Secondly,min(max) bridging fault test sets with n+2 vectors are pre-sented for the circuit realizations of multiple-valued logic functions. Finally,a tree structure is used instead of cascade structure to reduce the delay in the circuit realization,it is shown that three vec-tors are sufficient to detect all single stuck-at faults in the tree structure realization of multiple-valued logic functions.展开更多
Correlation-immunity is an important concept in cryptology. In ref. [1] Siegenthaler introduced the mathematical definition of correlation-immunity and used the correlation-immunity order of logic functions as a measu...Correlation-immunity is an important concept in cryptology. In ref. [1] Siegenthaler introduced the mathematical definition of correlation-immunity and used the correlation-immunity order of logic functions as a measure for cipher systems to defend against correlation attacks. In terms of Walsh transform, the correlation immunity of binary-valued logic functions, i.e. Boolean functions, was studied in ref. [2], and a展开更多
There are many kinds of special relationships between multiple-valued logical func-tions and their variables, and they are difficult to be judged from their expressions. In thispaper, some sufficient and necessary con...There are many kinds of special relationships between multiple-valued logical func-tions and their variables, and they are difficult to be judged from their expressions. In thispaper, some sufficient and necessary conditions of the independence and statistical independenceof multiple-valued logical functions on their variables are given. Some conditions of algebraicindependence of multiple-valued logical functions on some of their variables and the way to de-generate a function to the greatest extent are proposed, and some applications of these resultsare indicated. All the results are studied by using Chrestenson spectral techniques.展开更多
The single fault and multiple fault detections for multiple-valued logic circuits are studied in this paper. Firstly, it is shown that the cardinality of optimal single fault test set for fanout-free m-valued circuits...The single fault and multiple fault detections for multiple-valued logic circuits are studied in this paper. Firstly, it is shown that the cardinality of optimal single fault test set for fanout-free m-valued circuits with n primary inputs is not more than n + 1, for linear tree circuits is two, and for multiplication modulo circuits is two if n is an odd number or if n is an even number and m ＞ 3, where the optimal test set of a circuit has minimal number of test vectors. Secondly,it is indicated that the cardinality of optimal multiple fault test set for linear tree circuits with n primary inputs is 1 + [n/(m - 1)], for multiplication modulo circuits is n+ 1, for fanout-free circuits that consist of 2-input linear tree circuits and 2-input multiplication modulo circuits is not greater than n+ 1, where [x] denotes the smallest integer greater than or equal to x. Finally,the single fault location approaches of linear tree circuits and multiplication modulo circuits are presented, and all faults in the two types of circuits can be located by using a test set with n + 1 vectors.展开更多
A new AB^2 operation in Galois Field GF(24)is presented and its systolic realization based on multiple-valued logic(MVL)is proposed.The systolic structure of the operation employs multiple-valued current mode(MVCM)by ...A new AB^2 operation in Galois Field GF(24)is presented and its systolic realization based on multiple-valued logic(MVL)is proposed.The systolic structure of the operation employs multiple-valued current mode(MVCM)by using dynamic source-coupled logic(SCL)to reduce the transistor and wire counts,and the initial delay.The performance is evaluated by HSPICE simulation with 0.18.μm CMOS technology.A comparison is conducted between our proposed implementation and those reported in the literature.The transistor counts,the wire counts and the initial delay in our MVL design show savings of about 23%,45%,and 72%,in comparison with the corresponding binary CMOS implementation.The systolic architecture proposed is simple,regular,and modular,well suited for very large scale integration(VLSI)implementation.The combination of MVCM circuits and relevant algorithms based on MVL seems to be a potential solution for high performance arithmetic operations in GF(2^k).展开更多
In this paper, the author analyzed some cryptographic properties of a class of logical functions, f(x,y)=(q(x),...,q(x))·y+h(x),over Galois rings and residue rings, presented the relationship between the characte...In this paper, the author analyzed some cryptographic properties of a class of logical functions, f(x,y)=(q(x),...,q(x))·y+h(x),over Galois rings and residue rings, presented the relationship between the character spectrum of f(x,y) and the character speetrum of q(x),h(x) and the relationship between the cryptographic properties of f(x,y) and the cryptographic properties of h(x).展开更多
Fuzzy logic controller adopting unevenly-distributed membership function was presented with the purpose of enhancing performance of the temperature control precision and robustness for the chamber cooling system.Histo...Fuzzy logic controller adopting unevenly-distributed membership function was presented with the purpose of enhancing performance of the temperature control precision and robustness for the chamber cooling system.Histogram equalization and noise detection were performed to modify the evenly-distributed membership functions of error and error change rate into unevenly-distributed membership functions.Then,the experimental results with evenly and unevenly distributed membership functions were compared under the same outside environment conditions.The experimental results show that the steady-state error is reduced around 40% and the noise disturbance is rejected successfully even though noise range is 60% of the control precision range.The control precision is improved by reducing the steady-state error and the robustness is enhanced by rejecting noise disturbance through the fuzzy logic controller with unevenly-distributed membership function.Moreover,the system energy efficiency and lifetime of electronic expansion valve(EEV) installed in chamber cooling system are improved by adopting the unevenly-distributed membership function.展开更多
In this paper,w e provide a novel scheme to solve the motion planning problem of multi-agent systems under high-level task specifications.First,linear temporal logic is applied to express the global task specification...In this paper,w e provide a novel scheme to solve the motion planning problem of multi-agent systems under high-level task specifications.First,linear temporal logic is applied to express the global task specification.Then an efficient and decentralized algorithm is proposed to decom pose it into local tasks.M oreover,w e use control barrier function to synthesize the local controller for each agent under the linear temporal logic motion plan with safety constraint.Finally,simulation results show the effectiveness and efficiency of our proposed scheme.展开更多
In this paper,we study a special class of fractal interpolation functions,and give their Haar-wavelet expansions.On the basis of the expansions,we investigate the H(o|¨)lder smoothness of such functions and their...In this paper,we study a special class of fractal interpolation functions,and give their Haar-wavelet expansions.On the basis of the expansions,we investigate the H(o|¨)lder smoothness of such functions and their logical derivatives of order α.展开更多
This paper discusses the definition and properties of multivalued symmetric functions, points out that a multivalued symmetric function can be decomposed according to the value of the function j. The subfunction Lj co...This paper discusses the definition and properties of multivalued symmetric functions, points out that a multivalued symmetric function can be decomposed according to the value of the function j. The subfunction Lj corresponding to j must be a symmetric function, and it may be expressed as the sum of products form of degenerated multivalued fundamental symmetric functions. Based on this consideration, the circuit realization for the multivalued symmetric functions based on full adders is proposed.展开更多
This paper discusses the best affine approach （BAA） of multi-output m-valued logical functions. First, it gives the spectra of rate of accordance between multi-output m-valued logical functions and their affine func...This paper discusses the best affine approach （BAA） of multi-output m-valued logical functions. First, it gives the spectra of rate of accordance between multi-output m-valued logical functions and their affine functions, then analyzes the BAA of multi-output m-valued logical functions and finally gives the spectral characteristics of BAA of multi-output m-valued logical functions.展开更多
The paper consists in the use of some logical functions decomposition algorithms with application in the implementation of classical circuits like SSI, MSI and PLD. The decomposition methods use the Boolean matrix cal...The paper consists in the use of some logical functions decomposition algorithms with application in the implementation of classical circuits like SSI, MSI and PLD. The decomposition methods use the Boolean matrix calculation. It is calculated the implementation costs emphasizing the most economical solutions. One important aspect of serial decomposition is the task of selecting “best candidate” variables for the G function. Decomposition is essentially a process of substituting two or more input variables with a lesser number of new variables. This substitutes results in the reduction of the number of rows in the truth table. Hence, we look for variables which are most likely to reduce the number of rows in the truth table as a result of decomposition. Let us consider an input variable purposely avoiding all inter-relationships among the input variables. The only available parameter to evaluate its activity is the number of “l”s or “O”s that it has in the truth table. If the variable has only “1” s or “0” s, it is the “best candidate” for decomposition, as it is practically redundant.展开更多
The circuit testable realization and its fault detection for logic functions with ESOP （EXOR-Sum-Of-Products） expressions are studied. First of all, for the testable realization by using XOR gate cascade, a test set...The circuit testable realization and its fault detection for logic functions with ESOP （EXOR-Sum-Of-Products） expressions are studied. First of all, for the testable realization by using XOR gate cascade, a test set with 2n ＋ m ＋ 1 vectors for the detections of AND bridging faults and a test set with 2n ＋ m vectors for the detections of OR bridging faults are presented. Secondly, for the testable realization by using ）（OR gate tree, a test set with 2n ＋ m vectors for the detections of AND bridging faults and a test set with 3n ＋ m ＋ 1 vectors for the detections of OR bridging faults are presented. Finally, a single fault test set with n ＋ 5 vectors for the XOR gate tree realization is presented. Where n is the number of input variables and m is the number of product terms in a logic function.展开更多
Based on the definition of a logic structure feature to relate logically functional requirements to geometric representation independent upon detailed geometric representation, this paper presents an idea of logical s...Based on the definition of a logic structure feature to relate logically functional requirements to geometric representation independent upon detailed geometric representation, this paper presents an idea of logical structure modeling for computer aided conceptual design and makes attempt to establish a representation formalism of logic structure modeling. The definition and representation of logical structure feature are given and an assembly module definition for supporting top down conceptual design is also proposed. The proposed scheme contributes to several aspects of conceptual design research, especially to provide elementarily a formal methodology for computer aided conceptual design system development and operation.展开更多
基金Supported by the National Natural Science Foundation of China (No.60006002)the Education Department of Guangdong Province of China (No.02019).
文摘The circuit testable realizations of multiple-valued functions are studied in this letter. First of all,it is shown that one vector detects all skew faults in multiplication modulo circuits or in addi-tion modulo circuits,and n+1 vectors detect all skew faults in the circuit realization of multiple-valued functions with n inputs. Secondly,min(max) bridging fault test sets with n+2 vectors are pre-sented for the circuit realizations of multiple-valued logic functions. Finally,a tree structure is used instead of cascade structure to reduce the delay in the circuit realization,it is shown that three vec-tors are sufficient to detect all single stuck-at faults in the tree structure realization of multiple-valued logic functions.
基金Project supported by the National Natural Science FoundationDoctoral Programme Foundation of Institutions of Higher Education
文摘Correlation-immunity is an important concept in cryptology. In ref. [1] Siegenthaler introduced the mathematical definition of correlation-immunity and used the correlation-immunity order of logic functions as a measure for cipher systems to defend against correlation attacks. In terms of Walsh transform, the correlation immunity of binary-valued logic functions, i.e. Boolean functions, was studied in ref. [2], and a
文摘There are many kinds of special relationships between multiple-valued logical func-tions and their variables, and they are difficult to be judged from their expressions. In thispaper, some sufficient and necessary conditions of the independence and statistical independenceof multiple-valued logical functions on their variables are given. Some conditions of algebraicindependence of multiple-valued logical functions on some of their variables and the way to de-generate a function to the greatest extent are proposed, and some applications of these resultsare indicated. All the results are studied by using Chrestenson spectral techniques.
基金Supported by the National Natural Science Foundation of China (No.60006002) Education Department of Guangdong Province of China (No. Z02019)
文摘The single fault and multiple fault detections for multiple-valued logic circuits are studied in this paper. Firstly, it is shown that the cardinality of optimal single fault test set for fanout-free m-valued circuits with n primary inputs is not more than n + 1, for linear tree circuits is two, and for multiplication modulo circuits is two if n is an odd number or if n is an even number and m ＞ 3, where the optimal test set of a circuit has minimal number of test vectors. Secondly,it is indicated that the cardinality of optimal multiple fault test set for linear tree circuits with n primary inputs is 1 + [n/(m - 1)], for multiplication modulo circuits is n+ 1, for fanout-free circuits that consist of 2-input linear tree circuits and 2-input multiplication modulo circuits is not greater than n+ 1, where [x] denotes the smallest integer greater than or equal to x. Finally,the single fault location approaches of linear tree circuits and multiplication modulo circuits are presented, and all faults in the two types of circuits can be located by using a test set with n + 1 vectors.
基金National Natural Science Foundation of China(61801027)。
文摘A new AB^2 operation in Galois Field GF(24)is presented and its systolic realization based on multiple-valued logic(MVL)is proposed.The systolic structure of the operation employs multiple-valued current mode(MVCM)by using dynamic source-coupled logic(SCL)to reduce the transistor and wire counts,and the initial delay.The performance is evaluated by HSPICE simulation with 0.18.μm CMOS technology.A comparison is conducted between our proposed implementation and those reported in the literature.The transistor counts,the wire counts and the initial delay in our MVL design show savings of about 23%,45%,and 72%,in comparison with the corresponding binary CMOS implementation.The systolic architecture proposed is simple,regular,and modular,well suited for very large scale integration(VLSI)implementation.The combination of MVCM circuits and relevant algorithms based on MVL seems to be a potential solution for high performance arithmetic operations in GF(2^k).
文摘In this paper, the author analyzed some cryptographic properties of a class of logical functions, f(x,y)=(q(x),...,q(x))·y+h(x),over Galois rings and residue rings, presented the relationship between the character spectrum of f(x,y) and the character speetrum of q(x),h(x) and the relationship between the cryptographic properties of f(x,y) and the cryptographic properties of h(x).
文摘Fuzzy logic controller adopting unevenly-distributed membership function was presented with the purpose of enhancing performance of the temperature control precision and robustness for the chamber cooling system.Histogram equalization and noise detection were performed to modify the evenly-distributed membership functions of error and error change rate into unevenly-distributed membership functions.Then,the experimental results with evenly and unevenly distributed membership functions were compared under the same outside environment conditions.The experimental results show that the steady-state error is reduced around 40% and the noise disturbance is rejected successfully even though noise range is 60% of the control precision range.The control precision is improved by reducing the steady-state error and the robustness is enhanced by rejecting noise disturbance through the fuzzy logic controller with unevenly-distributed membership function.Moreover,the system energy efficiency and lifetime of electronic expansion valve(EEV) installed in chamber cooling system are improved by adopting the unevenly-distributed membership function.
基金This work was partially supported by the National Natural Science Foundation of China(No.51475334)the National Key Research and Development Program of Science and Technology of China(No.2018YFB1305304)the Shanghai Science and Technology Pilot Project(No.19511132100).
文摘In this paper,w e provide a novel scheme to solve the motion planning problem of multi-agent systems under high-level task specifications.First,linear temporal logic is applied to express the global task specification.Then an efficient and decentralized algorithm is proposed to decom pose it into local tasks.M oreover,w e use control barrier function to synthesize the local controller for each agent under the linear temporal logic motion plan with safety constraint.Finally,simulation results show the effectiveness and efficiency of our proposed scheme.
文摘In this paper,we study a special class of fractal interpolation functions,and give their Haar-wavelet expansions.On the basis of the expansions,we investigate the H(o|¨)lder smoothness of such functions and their logical derivatives of order α.
文摘This paper discusses the definition and properties of multivalued symmetric functions, points out that a multivalued symmetric function can be decomposed according to the value of the function j. The subfunction Lj corresponding to j must be a symmetric function, and it may be expressed as the sum of products form of degenerated multivalued fundamental symmetric functions. Based on this consideration, the circuit realization for the multivalued symmetric functions based on full adders is proposed.
基金Supported by the Opening Research Foundation of the State Key Laboratory of Information Security (2005-01-02)
文摘This paper discusses the best affine approach （BAA） of multi-output m-valued logical functions. First, it gives the spectra of rate of accordance between multi-output m-valued logical functions and their affine functions, then analyzes the BAA of multi-output m-valued logical functions and finally gives the spectral characteristics of BAA of multi-output m-valued logical functions.
文摘The paper consists in the use of some logical functions decomposition algorithms with application in the implementation of classical circuits like SSI, MSI and PLD. The decomposition methods use the Boolean matrix calculation. It is calculated the implementation costs emphasizing the most economical solutions. One important aspect of serial decomposition is the task of selecting “best candidate” variables for the G function. Decomposition is essentially a process of substituting two or more input variables with a lesser number of new variables. This substitutes results in the reduction of the number of rows in the truth table. Hence, we look for variables which are most likely to reduce the number of rows in the truth table as a result of decomposition. Let us consider an input variable purposely avoiding all inter-relationships among the input variables. The only available parameter to evaluate its activity is the number of “l”s or “O”s that it has in the truth table. If the variable has only “1” s or “0” s, it is the “best candidate” for decomposition, as it is practically redundant.
基金Supported by the National Natural Science Foundation of China (No.60006002)the Education Department of Guangdong Province of China (No.02019).
文摘The circuit testable realization and its fault detection for logic functions with ESOP （EXOR-Sum-Of-Products） expressions are studied. First of all, for the testable realization by using XOR gate cascade, a test set with 2n ＋ m ＋ 1 vectors for the detections of AND bridging faults and a test set with 2n ＋ m vectors for the detections of OR bridging faults are presented. Secondly, for the testable realization by using ）（OR gate tree, a test set with 2n ＋ m vectors for the detections of AND bridging faults and a test set with 3n ＋ m ＋ 1 vectors for the detections of OR bridging faults are presented. Finally, a single fault test set with n ＋ 5 vectors for the XOR gate tree realization is presented. Where n is the number of input variables and m is the number of product terms in a logic function.
文摘Based on the definition of a logic structure feature to relate logically functional requirements to geometric representation independent upon detailed geometric representation, this paper presents an idea of logical structure modeling for computer aided conceptual design and makes attempt to establish a representation formalism of logic structure modeling. The definition and representation of logical structure feature are given and an assembly module definition for supporting top down conceptual design is also proposed. The proposed scheme contributes to several aspects of conceptual design research, especially to provide elementarily a formal methodology for computer aided conceptual design system development and operation.
