Multi-Threshold CMOS(MTCMOS) is an effective technique for controlling leakage power with low delay overhead.However the large magnitude of ground bouncing noise induced by the sleep to active mode transition may caus...Multi-Threshold CMOS(MTCMOS) is an effective technique for controlling leakage power with low delay overhead.However the large magnitude of ground bouncing noise induced by the sleep to active mode transition may cause signal integrity problem in MTCMOS circuits.We propose a methodology for reducing ground bouncing noise under the wake-up delay constraint.An improved two-stage parallel power gating structure that can suppress the ground bouncing noise through turn on sets of sleep transistors consecutively is proposed.The size of each sleep transistor is optimized by a novel sizing algorithm based on a simple discharging model.Simulation results show that the proposed techniques achieve at least 23% improvement in the product of the peak amplitude of ground bouncing noise and the wake-up time when compared with other existing techniques.展开更多
In this paper we have investigated the single phase sleep signal modulation technique,step-wise V_（gs）technique and the three-phase reactivation technique to evaluate the noise characteristics of multi-threshold CMO...In this paper we have investigated the single phase sleep signal modulation technique,step-wise V_（gs）technique and the three-phase reactivation technique to evaluate the noise characteristics of multi-threshold CMOS circuits used in communication systems.The stacking technique is also implemented in this paper for the sleep transistor.The stacking approach helps to minimize leakage power.The mode transition noise minimization techniques have been applied to 32-bit dynamic TSPC adder with stacked sleep transistors in a standard 45-nm CMOS process.The reactivation noise,delay and energy consumption of all the three techniques have been evaluated.It has been shown that the three phase modulation technique significantly minimizes the reactivation delay when the peak noise level is maintained the same for all three techniques.The three phase modulation technique shows 67.3%and 35%reduction in delay compared to the single phase and step-wise Vgs modulation techniques respectively.The reactivation energy is also suppressed by 49.3%and 39.14%with respect to the single-phase and stepwise Vgs techniques.展开更多
Multi-threshold complementary metal-oxide- semiconductor （MTCMOS） is ofbn used to reduce the leakage current in idle circuit. Ground bounce noise produced during a transition mode （sleep-to-active） is an important...Multi-threshold complementary metal-oxide- semiconductor （MTCMOS） is ofbn used to reduce the leakage current in idle circuit. Ground bounce noise produced during a transition mode （sleep-to-active） is an important challenge in MTCMOS. In this paper, various noise-aware combinational MTCMOS circuit was used to evaluate the ground bounce noise. An intermediate mode was applied in the sleep-to-active mode transition to reduce the charge stored on virtual lines to real ground. The dependence of ground bounce noise on voltage, transistor size and temperature was investigated with different MTCMOS circuit technique. The peak amplitude of ground bounce noise was reduced up to 78.82%. The leakage current of the circuit was decreased up to 99.73% and the active power of the circuit was reduced up to 62.32%. Simulation of multiplier with different MTCMOS circuit techniques was performed on 45nm CMOS technology.展开更多
基金Supported by the National Natural Science Foundation of China (No. 6087001)
文摘Multi-Threshold CMOS(MTCMOS) is an effective technique for controlling leakage power with low delay overhead.However the large magnitude of ground bouncing noise induced by the sleep to active mode transition may cause signal integrity problem in MTCMOS circuits.We propose a methodology for reducing ground bouncing noise under the wake-up delay constraint.An improved two-stage parallel power gating structure that can suppress the ground bouncing noise through turn on sets of sleep transistors consecutively is proposed.The size of each sleep transistor is optimized by a novel sizing algorithm based on a simple discharging model.Simulation results show that the proposed techniques achieve at least 23% improvement in the product of the peak amplitude of ground bouncing noise and the wake-up time when compared with other existing techniques.
文摘In this paper we have investigated the single phase sleep signal modulation technique,step-wise V_（gs）technique and the three-phase reactivation technique to evaluate the noise characteristics of multi-threshold CMOS circuits used in communication systems.The stacking technique is also implemented in this paper for the sleep transistor.The stacking approach helps to minimize leakage power.The mode transition noise minimization techniques have been applied to 32-bit dynamic TSPC adder with stacked sleep transistors in a standard 45-nm CMOS process.The reactivation noise,delay and energy consumption of all the three techniques have been evaluated.It has been shown that the three phase modulation technique significantly minimizes the reactivation delay when the peak noise level is maintained the same for all three techniques.The three phase modulation technique shows 67.3%and 35%reduction in delay compared to the single phase and step-wise Vgs modulation techniques respectively.The reactivation energy is also suppressed by 49.3%and 39.14%with respect to the single-phase and stepwise Vgs techniques.
文摘Multi-threshold complementary metal-oxide- semiconductor （MTCMOS） is ofbn used to reduce the leakage current in idle circuit. Ground bounce noise produced during a transition mode （sleep-to-active） is an important challenge in MTCMOS. In this paper, various noise-aware combinational MTCMOS circuit was used to evaluate the ground bounce noise. An intermediate mode was applied in the sleep-to-active mode transition to reduce the charge stored on virtual lines to real ground. The dependence of ground bounce noise on voltage, transistor size and temperature was investigated with different MTCMOS circuit technique. The peak amplitude of ground bounce noise was reduced up to 78.82%. The leakage current of the circuit was decreased up to 99.73% and the active power of the circuit was reduced up to 62.32%. Simulation of multiplier with different MTCMOS circuit techniques was performed on 45nm CMOS technology.
