The authors will focus on the study of the design of Multiprocessor Systems on Chip （MPSoC）, specifically in the context of improving the performance of applications located on the MPSoC architecture. The objective ...The authors will focus on the study of the design of Multiprocessor Systems on Chip （MPSoC）, specifically in the context of improving the performance of applications located on the MPSoC architecture. The objective of this research is to study the problems of transition from a pure software implementation for an embodiment admitting one or more hardware components and to develop a methodology for automatic generation of migration of a software task into a hardware component in MPSoC. The transformation of a software task into a hardware task led to many changes, hardware part （connection, the requirement of an interrupt controller...）, software part （at least one task, I/O （I/O）, synchronization...） and an architectural point of view, the remarkable aspects of data storage. The experiment is done on the MJPEG decoder to illustrate the effectiveness of the authors＇ tool for automatic generation of migration.展开更多
The network-on-chip （NoC） design methodology is an important trend for large system-on-chip designs to reduce the bandwidth and power constraints in traditional synchronous bus architectures. In the design of packet...The network-on-chip （NoC） design methodology is an important trend for large system-on-chip designs to reduce the bandwidth and power constraints in traditional synchronous bus architectures. In the design of packet-based NoC, the packet-length plays an important role in the NoC throughput, latency, and energy consumption. The appropriate NoC packet-length was selected based on simulation and analysis of the packet-length effect on NoC for variable average data block length （ADBL） configuration parameters. A trade-off curve among throughput, latency, and energy consumption was developed and shows that the optimum packet length increases as the ADBL increases.展开更多
An instruction level parallel computing paradigm and a unified architecture for an array processor(AP) on a chip(SoC) are presented in this paper.Here "APU SoC" is short for "an AP SoC for the unified a...An instruction level parallel computing paradigm and a unified architecture for an array processor(AP) on a chip(SoC) are presented in this paper.Here "APU SoC" is short for "an AP SoC for the unified architecture".The MISD/MIMD architecture for instruction level parallel computing is unified with the SIMD architecture for data level parallel computing.As a result,all the computing can be implemented on an APU SoC.The APU SoC offers the rationale of an array structure for development in current technology,yet simplicity for the hardware(chip) and software(program) parallel designs.Just as a single processor chip can replace many function module chips,the APU SoC can replace the single-core/multi-core/many-core CPU chip for TLP computing and the ASIC/ASSP/FPGA/RC device array chip for Operation Level Parallel computing.展开更多
文摘The authors will focus on the study of the design of Multiprocessor Systems on Chip （MPSoC）, specifically in the context of improving the performance of applications located on the MPSoC architecture. The objective of this research is to study the problems of transition from a pure software implementation for an embodiment admitting one or more hardware components and to develop a methodology for automatic generation of migration of a software task into a hardware component in MPSoC. The transformation of a software task into a hardware task led to many changes, hardware part （connection, the requirement of an interrupt controller...）, software part （at least one task, I/O （I/O）, synchronization...） and an architectural point of view, the remarkable aspects of data storage. The experiment is done on the MJPEG decoder to illustrate the effectiveness of the authors＇ tool for automatic generation of migration.
基金Supported by the National Natural Science Foundation of China(No. 90607009)the National High-Tech Research and Development (863) Program of China (No. 2008AA01Z107)the Na-tional Key Basic Research and Development (973) Program of China (No. 2007CB310701)
文摘The network-on-chip （NoC） design methodology is an important trend for large system-on-chip designs to reduce the bandwidth and power constraints in traditional synchronous bus architectures. In the design of packet-based NoC, the packet-length plays an important role in the NoC throughput, latency, and energy consumption. The appropriate NoC packet-length was selected based on simulation and analysis of the packet-length effect on NoC for variable average data block length （ADBL） configuration parameters. A trade-off curve among throughput, latency, and energy consumption was developed and shows that the optimum packet length increases as the ADBL increases.
文摘An instruction level parallel computing paradigm and a unified architecture for an array processor(AP) on a chip(SoC) are presented in this paper.Here "APU SoC" is short for "an AP SoC for the unified architecture".The MISD/MIMD architecture for instruction level parallel computing is unified with the SIMD architecture for data level parallel computing.As a result,all the computing can be implemented on an APU SoC.The APU SoC offers the rationale of an array structure for development in current technology,yet simplicity for the hardware(chip) and software(program) parallel designs.Just as a single processor chip can replace many function module chips,the APU SoC can replace the single-core/multi-core/many-core CPU chip for TLP computing and the ASIC/ASSP/FPGA/RC device array chip for Operation Level Parallel computing.
