Metal–insulator–semiconductor(MOS) capacitor is a key structure for high performance MOS field transistors(MOSFETs), requiring low leakage current, high breakdown voltage, and low interface states. In this paper, β...Metal–insulator–semiconductor(MOS) capacitor is a key structure for high performance MOS field transistors(MOSFETs), requiring low leakage current, high breakdown voltage, and low interface states. In this paper, β-Ga_(2)O_(3) MOS capacitors were fabricated with ALD deposited Al_(2)O_(3) using H_(2)O or ozone(O_(3)) as precursors. Compared with the Al_(2)O_(3) gate dielectric with H_(2)O as ALD precursor, the leakage current for the O_(3) precursor case is decreased by two orders of magnitude, while it keeps the same level at the fixed charges, interface state density, and border traps. The SIMS tests show that Al_(2)O_(3) with O_(3) as precursor contains more carbon impurities. The current transport mechanism analysis suggests that the C–H complex in Al_(2)O_(3) with O_(3) precursor serves as deep energy trap to reduce the leakage current. These results indicate that the Al_(2)O_(3)/β-Ga_(2)O_(3)MOS capacitor using the O_(3) precursor has a low leakage current and holds potential for application in β-Ga_(2)O_(3) MOSFETs.展开更多
We investigate the effect of ozone(O_(3))oxidation of silicon carbide(SiC)on the flat-band voltage(Vfb)stability of SiC metal–oxide–semiconductor(MOS)capacitors.The SiC MOS capacitors are produced by O_(3)oxidation,...We investigate the effect of ozone(O_(3))oxidation of silicon carbide(SiC)on the flat-band voltage(Vfb)stability of SiC metal–oxide–semiconductor(MOS)capacitors.The SiC MOS capacitors are produced by O_(3)oxidation,and their Vfbstability under frequency variation,temperature variation,and bias temperature stress are evaluated.Secondary ion mass spectroscopy(SIMS),atomic force microscopy(AFM),and x-ray photoelectron spectroscopy(XPS)indicate that O_(3)oxidation can adjust the element distribution near SiC/SiO_(2)interface,improve SiC/SiO_(2)interface morphology,and inhibit the formation of near-interface defects,respectively.In addition,we elaborate the underlying mechanism through which O_(3)oxidation improves the Vfbstability of SiC MOS capacitors by using the measurement results and O_(3)oxidation kinetics.展开更多
Trichloroethylene （TCE） pretreatment of Si surface prior to HfO2 deposition is employed to fabricate HfO2 gatedielectric MOS capacitors. Influence of this processing procedure on interlayer growth, HfO2/Si interface...Trichloroethylene （TCE） pretreatment of Si surface prior to HfO2 deposition is employed to fabricate HfO2 gatedielectric MOS capacitors. Influence of this processing procedure on interlayer growth, HfO2/Si interface properties, gate-oxide leakage and device reliability is investigated. Among the surface pretreatments in NH3, NO, N2O and TCE ambients, the TCE pretreatment gives the least interlayer growths the lowest interface-state density, the smallest gate leakage and the highest reliability. All these improvements should be ascribed to the passivation effects of Cl2 and HC1 on the structural defects in the interlayer and at the interface, and also their gettering effects on the ion contamination in the gate dielectric.展开更多
MOS capacitors with hafnium oxynitride（HfON）gate dielectrics were fabricated on Ge and Si substrates using the RF reactive magnetron sputtering method.A large amount of fixed charges and interface traps exist at the...MOS capacitors with hafnium oxynitride（HfON）gate dielectrics were fabricated on Ge and Si substrates using the RF reactive magnetron sputtering method.A large amount of fixed charges and interface traps exist at the Ge/HfON interface.HRTEM and XPS analyses show that Ge oxides were grown and diffused into HfON after post metal annealing.A Si nitride interfacial layer was inserted between Ge and HfON as diffusion barrier.Using this method,well behaved capacitance–voltage and current–voltage characteristics were obtained.Finally hystereses are compared under different process conditions and possible causes are discussed.展开更多
In this paper, we investigate multi-scale methods for the inverse modeling in 1-D Metal-Oxide-Silicon (MOS) capacitor. First, the mathematical model of the device is given and the numerical simulation for the forward ...In this paper, we investigate multi-scale methods for the inverse modeling in 1-D Metal-Oxide-Silicon (MOS) capacitor. First, the mathematical model of the device is given and the numerical simulation for the forward problem of the model is implemented using finite element method with adaptive moving mesh. Then numerical analysis of these parameters in the model for the inverse problem is presented. Some matrix analysis tools are applied to explore the parameters' sensitivities. And third, the parameters are extracted using Levenberg-Marquardt optimization method. The essential difficulty arises from the effect of multi-scale physical difference of the parameters. We explore the relationship between the parameters' sensitivities and the sequence for optimization, which can seriously affect the final inverse modeling results. An optimal sequence can efficiently overcome the multi-scale problem of these parameters. Numerical experiments show the efficiency of the proposed methods.展开更多
SCAs （Switched Capacitor Arrays） have a wide range of uses, especially in high energy physics, nuclear science and astrophysics experiments. This paper presents a method of using a MOS capacitor as a sampling capaci...SCAs （Switched Capacitor Arrays） have a wide range of uses, especially in high energy physics, nuclear science and astrophysics experiments. This paper presents a method of using a MOS capacitor as a sampling capacitor to gain larger capacitance with small capacitor area in SCA design. It studies the non-ideal effects of the MOS capacitor and comes up with ways to reduce these adverse effects. A prototype SCA ASIC which uses a MOS capacitor to store the samples has been designed and tested to verify this method. The SCA integrates 32 channels and each has 64 cells and a readout amplifier. The stored voltage is converted to a pair of differential currents （~ 4 mA max） and multiplexed to the output. All the functionalities have been verified. The power consumption is less than 2 mW/ch. The INL of all the cells in one channel are better than 0.39%. The equivalent input noise of the SCA has been tested to be 2.2 mV with 625 kHz full-scale sine wave as input, sampling at 40 MSPS （Mega-samples per Second） and reading out at 5 MHz. The effective resolution is 8.8 bits considering 1 V dynamic range. The maximum sampling rate reaches up to 50 MSPS and readout rate of 15 MHz to keep noise smaller than 2.5 mV. The test results validate the feasibility of the MOS capacitor.展开更多
The high frequency CV curves of MOS capacitor have been studied. It is shown that semiclassical model is a good approximation to quantum model and approaches to classical model when the oxide layer is thick. This conc...The high frequency CV curves of MOS capacitor have been studied. It is shown that semiclassical model is a good approximation to quantum model and approaches to classical model when the oxide layer is thick. This conclusion provides us an efficient （semiclassical） model including quantum mechanical effects to do parameter extraction for ultrathin oxide device. Here the effective extracting strategy is designed and numerical experiments demonstrate the validity of the strategy.展开更多
This paper investigates the capacitance-voltage （C-V） measurement on fully silicided （FUSI） gated metal-oxide-semiconductor （MOS） capacitors and the applicability of MOS capacitor models. When the oxide leakage ...This paper investigates the capacitance-voltage （C-V） measurement on fully silicided （FUSI） gated metal-oxide-semiconductor （MOS） capacitors and the applicability of MOS capacitor models. When the oxide leakage current of an MOS capacitor is large, two-element parallel or series model cannot be used to obtain its real C-V characteristic. A three-element model simultaneously consisting of parallel conductance and series resistance or a four-element model with further consideration of a series inductance should be used. We employed the threeelement and the four-element models with the help of two-frequency technique to measure the Ni FUSI gated MOS capacitors. The results indicate that the capacitance of the MOS capacitors extracted by the three-element model still shows some frequency dispersion, while that extracted by the four-element model is close to the real capacitance, showing little frequency dispersion. The obtained capacitance can be used to calculate the dielectric thickness with quantum effect correction by NCSU C-V program. We also investigated the influence of MOS capacitor＇s area on the measurement accuracy. The results indicate that the decrease of capacitor area can reduce the dissipation factor and improve the measurement accuracy. As a result, the frequency dispersion of the measured capacitance is significantly reduced, and real C-V characteristic can be obtained directly by the series model. In addition, this paper investigates the quasi-static C-V measurement and the photonic high-frequency C-V measurement on Ni FUSI metal gated MOS capacitor with a thin leaky oxide. The results indicate that the large tunneling current through the gate oxide significantly perturbs the accurate measurement of the displacement current, which is essential for the quasi-static C-V measurement. On the other hand, the photonic high-frequency C-V measurement can bypass the leakage problem, and get reliable low-frequency C-V characteristic, which can be used to evaluate whether the full silicidation has completed or not, and to extract the interface trap density of the SiO2/Si interface.展开更多
N-type and p-type 6H-SiC metal oxide semiconductor (MOS) capacitor samples are fabricated with a typical method,and the high frequency capacitor voltage (C-V) curves of these samples are measured at temperatures rangi...N-type and p-type 6H-SiC metal oxide semiconductor (MOS) capacitor samples are fabricated with a typical method,and the high frequency capacitor voltage (C-V) curves of these samples are measured at temperatures ranging from 293 to 533 K.There exists huge difference between the n-type and p-type samples.Flat-band voltage shift of the n-type sample becomes larger with temperature rising,but that of the p-type sample have very little change.This may be caused by the residual Al in the p-type oxide.Both types of the SiC samples follow the same rule of flat-band voltage changing with temperature.But their mechanisms are different as temperature is above 453 K.Of both types the p-type SiC is more suitable for high temperature applications.展开更多
The frequency dependence of admittance measurements （capacitance–voltage （C–V ） and conductance–voltage （G/ω–V ）） of Au/SnO2 /n-Si （MOS） capacitors was investigated by taking into account the effects of t...The frequency dependence of admittance measurements （capacitance–voltage （C–V ） and conductance–voltage （G/ω–V ）） of Au/SnO2 /n-Si （MOS） capacitors was investigated by taking into account the effects of the interface states （N ss ） and series resistance （Rs ） at room temperature. Admittance measurements were carried out in frequency and bias voltage ranges of 1 kHz–1 MHz and （ 5V）–（＋9V）, respectively. The values of N ss and R s were determined by using a conductance method and estimating from the admittance measurements of the MOS capacitors. At low frequencies, the interface states can follow the AC signal and yield excess capacitance and conductance. In addition, the parallel conductance （G p /ω） versus log（f） curves at various voltages include a peak due to the presence of interface states. It is observed that the N ss and their time constant （τ） range from 1.23 ×10 12 eV-1 ·cm-2 to 1.47 ×10 12 eV-1 ·cm-2 and from 7.29 ×10-5 s to 1.81 ×10-5s, respectively.展开更多
The impact of nitridation and sulfur passivation for Ino.s3Gao.47As surfaces on the A1/A1203/InGaAs MOS capacitors properties was investigated by comparing the characteristics of frequency dispersion and hysteresis, c...The impact of nitridation and sulfur passivation for Ino.s3Gao.47As surfaces on the A1/A1203/InGaAs MOS capacitors properties was investigated by comparing the characteristics of frequency dispersion and hysteresis, calculating the Dit and ANbt values, and analyzing the interface traps and the leakage current. The results showed that both of the methods could form a passivation-layer on the InGaAs surface. The samples treated by N2 plasma could obtain good interface properties with the smallest frequency dispersion in the accumulation region, and the best hysteresis characteristics and good I-V properties were presented. Also the samples with （NH4）ESx treatment showed the smallest frequency dispersion near the flat-band region and a minimum Dit value of 2.6 x10^11 cm-2 eV-1.展开更多
An MOS （metal oxide semiconductor） capacitor structure with double-layer heterogeneous nanocrystals consisting of semiconductor and metal embedded in a gate oxide for nonvolatile memory applications has been fabrica...An MOS （metal oxide semiconductor） capacitor structure with double-layer heterogeneous nanocrystals consisting of semiconductor and metal embedded in a gate oxide for nonvolatile memory applications has been fabricated and characterized. By combining vacuum electron-beam co-evaporated Si nanocrystals and self-assembled Ni nanocrystals in a SiO2 matrix, an MOS capacitor with double-layer heterogeneous nanocrystals can have larger charge storage capacity and improved retention characteristics compared to one with single-layer nanocrystals. The upper metal nanocrystals as an additional charge trap layer enable the direct tunneling mechanism to enhance the flat voltage shift and prolong the retention time.展开更多
The Ge metal-oxide-semiconductor (MOS) capacitors were fabricated with HfO2 as gate dielectric.AlON,NdON,and NdAlON were deposited between the gate dielectric and the Ge substrate as the interfacial passivation layer ...The Ge metal-oxide-semiconductor (MOS) capacitors were fabricated with HfO2 as gate dielectric.AlON,NdON,and NdAlON were deposited between the gate dielectric and the Ge substrate as the interfacial passivation layer (IPL).The electrical properties (such as capacitance-voltage (C-V) and gate leakage current density versus gate voltage (J_(g)-V_(g))) were measured by HP4284A precision LCR meter and HP4156A semiconductor parameter analyzer.The chemical states and interfacial quality of the high-k/Ge interface were investigated by X-ray photoelectron spectroscopy (XPS).The experimental results show that the sample with the NdAlON as IPL exhibits the excellent interfacial and electrical properties.These should be attributed to an effective suppression of the Ge suboxide and HfGeOx interlayer,and an enhanced blocking role against inter-diffusion of the elements during annealing by the NdAlON IPL.展开更多
In order to investigate the characteristics and mechanisms of subthreshold voltage hysteresis(ΔV_(th,sub)) of 4 H-SiC metal-oxide-semiconductor field-effect transistors(MOSFETs),4 H-SiC planar and trench MOSFETs and ...In order to investigate the characteristics and mechanisms of subthreshold voltage hysteresis(ΔV_(th,sub)) of 4 H-SiC metal-oxide-semiconductor field-effect transistors(MOSFETs),4 H-SiC planar and trench MOSFETs and corresponding P-type planar and trench metal-oxide-semiconductor(MOS) capacitors are fabricated and characterized.Compared with planar MOSFEF,the trench MOSFET shows hardly larger ΔV_(th,sub) in wide temperature range from 25 0 C to 300 0 C.When operating temperature range is from 25 ℃ to 300 ℃,the off-state negative V_(gs) of planar and trench MOSFETs should be safely above-4 V and-2 V,respectively,to alleviate the effect of ΔV_(th,sub) on the normal operation.With the help of P-type planar and trench MOS capacitors,it is confirmed that the obvious ΔV_(th,sub) of 4 H-SiC MOSFET originates from the high density of the hole interface traps between intrinsic Fermi energy level(E_(i)) and valence band(E_(v)).The maximumΔV_(th,sub) of trench MOSFET is about twelve times larger than that of planar MOSFET,owing to higher density of interface states(D_(it)) between E_(i) and E_(v).These research results will be very helpful for the application of 4 H-SiC MOSFET and the improvement of ΔV_(th,sub) of 4 H-SiC MOSFET,especially in 4 H-SiC trench MOSFET.展开更多
The purpose of this work relates to study on the characteristics of ultra thin gate oxide (2 5nm thickness) and the effect of metal Al,Zr,and Ta contamination on GOI.The controlled metallic contamination experiments...The purpose of this work relates to study on the characteristics of ultra thin gate oxide (2 5nm thickness) and the effect of metal Al,Zr,and Ta contamination on GOI.The controlled metallic contamination experiments are carried out by depositing a few ppm contaminated metal and low pH solutions on the wafers.The maximum metal surface concentration is controlled at about 10 12 cm -2 level in order to simulate metal contamination during ultra clean processing.A ramped current stress for intrinsic charge to breakdown measurements with gate injection mode is used to examine the characteristics of these ultra thin gate oxides and the effect of metal contamination on GOI.It is the first time to investigate the influence of metal Zr and Ta contamination on 2 5nm ultra thin gate oxide.It is demonstrated that there is little effect of Al contamination on GOI,while Zr contamination is the most detrimental to GOI,and early breakdown has happened to wafers contaminated by Ta.展开更多
An ultrathin SrTiO3 dielectric layer is optimized through Al doping to solve the problems existing in development of ultra-high-k oxide MOS capacitors.Through post-deposition annealing,Al doping induces changes in the...An ultrathin SrTiO3 dielectric layer is optimized through Al doping to solve the problems existing in development of ultra-high-k oxide MOS capacitors.Through post-deposition annealing,Al doping induces changes in the electronic structure of SrTiO3,thereby effectively reducing leakage current to <10^-8 A/cm^2 at 0.5 MV/cm but maintains good capacitance values(ε> 80) of ultrathin SrTMO3 MOS capacitors.Strontium titanate(SrTiO3) is a high-k material but its bandgap is smaller than that of other oxide dielectrics(e.g.,SiO2,Al2 O3).Consequently,an ultrathin SrTiO3 film may have a high tunneling leakage current,which is not suitable for capacitor-based applications.To improve the performance of metal-oxide-semiconductor(MOS) capacitors using SrTiO3,an approach based on homogenous and uniform aluminum doping to SrTiO3 through co-sputtering is introduced.The bandgap of a pristine SrTiO3 film showed an increase of 0.5 eV after Al doping.Furthermore,Al doping decreased the leakage current of SrTiO3/Si-based MOS capacitors by more than five orders of magnitude(at the level of nanoampere per square centimeter).Importantly,a dielectric constant of 81.3 and equivalent oxide thickness less than 5 A were achieved in an 8-nm-thick Al-doped SrTiO3 film owing to changes in its crystal structure and conduction band edge electronic structure.Thus,the obtained data show the effectiveness of the proposed approach for solving the problems existing in the development of ultra-high-k oxide MOS capacitors.展开更多
The surface oxidation of silicon （Si） wafers by atomic oxygen radical anions （O- anions） and the preparation of metal-oxide-semiconductor （MOS） capacitors on the O-oxidized Si substrates have been examined for t...The surface oxidation of silicon （Si） wafers by atomic oxygen radical anions （O- anions） and the preparation of metal-oxide-semiconductor （MOS） capacitors on the O-oxidized Si substrates have been examined for the first time. The O- anions are generated from a recently developed O- storage-emission material of [Ca24Al2sO64]^4＋·4O^- （Cl2A7-O^- for short）. After it has been irradiated by an O- anion bean： （0.5 μA/cm^2） at 300℃ for 1-10 hours, the Si wafer achieves an oxide layer with a thickness ranging from 8 to 32 nm. X-ray photoelectron spectroscopy （XPS） results reveal that the oxide layer is of a mixture of SiO2, Si2 O3, and Si2O distributed in different oxidation depths. The features of the MOS capacitor of 〈Al electrode/SiOx/Si〉 are investigated by measuring capacitance-voltage （C - V） and current-voltage （I - V） curves. The oxide charge density is about 6.0 × 10^1 cm^-2 derived from the （C - V curves. The leakage current density is in the order of 10^-6 A/cm^2 below 4 MV/cm, obtained from the I - V curves. The O- anions formed by present method would have potential applications to the oxidation and the surface-modification of materials together with the preparation of semiconductor devices.展开更多
We study a series of（HfO2）x（Al2O3）1-x /4H-SiC MOS capacitors. It is shown that the conduction band offset of HfO2 is 0.5 e V and the conduction band offset of Hf AlO is 1.11–1.72 e V. The conduction band offsets...We study a series of（HfO2）x（Al2O3）1-x /4H-SiC MOS capacitors. It is shown that the conduction band offset of HfO2 is 0.5 e V and the conduction band offset of Hf AlO is 1.11–1.72 e V. The conduction band offsets of（Hf O2）x（Al2O3）1-x are increased with the increase of the Al composition, and the（HfO2）x（Al2O3）1-x offer acceptable barrier heights（〉 1 e V）for both electrons and holes. With a higher conduction band offset,（Hf O2）x（Al2O3）1-x/4H-SiC MOS capacitors result in a ～ 3 orders of magnitude lower gate leakage current at an effective electric field of 15 MV/cm and roughly the same effective breakdown field of ～ 25 MV/cm compared to HfO2. Considering the tradeoff among the band gap, the band offset, and the dielectric constant, we conclude that the optimum Al2O3 concentration is about 30% for an alternative gate dielectric in 4H-Si C power MOS-based transistors.展开更多
LaON,LaTiO and LaTiON films are deposited as gate dielectrics by incorporating N or/and Ti into La_2O_3 using the sputtering method to fabricate Ge MOS capacitors,and the electrical properties of the devices are caref...LaON,LaTiO and LaTiON films are deposited as gate dielectrics by incorporating N or/and Ti into La_2O_3 using the sputtering method to fabricate Ge MOS capacitors,and the electrical properties of the devices are carefully examined.LaON/Ge capacitors exhibit the best interface quality,gate leakage property and device reliability,but a smaller k value（14.9）.LaTiO/Ge capacitors exhibit a higher k value（22.7）,but a deteriorated interface quality,gate leakage property and device reliability.LaTiON/Ge capacitors exhibit the highest k value（24.6）,and a relatively better interface quality（3.1×10^（11） eV^（-1）cm^（-2））,gate leakage property（3.6 × 10^（-3） A/cm^2 at V_g = 1V＋V_（fb）） and device reliability.Therefore,LaTiON is more suitable for high performance Ge MOS devices as a gate dielectric than LaON and LaTiO materials.展开更多
The effect of Al incorporation on the effective work function（EWF） of TiN metal gate was systematically investigated.Metal-oxide-semiconductor（MOS） capacitors with W/TiN/Al/TiN gate stacks were used to fulfill thi...The effect of Al incorporation on the effective work function（EWF） of TiN metal gate was systematically investigated.Metal-oxide-semiconductor（MOS） capacitors with W/TiN/Al/TiN gate stacks were used to fulfill this purpose.Different thickness ratios of Al to TiN and different post metal annealing（PMA） conditions were employed.Significant shift of work function towards to Si conduction band was observed,which was suitable for NMOS and the magnitude of shift depends on the processing conditions.展开更多
基金Project supported in part by the Science and Technology Development Plan Project of Jilin Province, China (Grant No. YDZJ202303CGZH022)the National Key Research and Development Program of China (Grant No. 2024YFE0205300)+1 种基金the National Natural Science Foundation of China (Grant No. 62471504)the Open Fund of the State Key Laboratory of Optoelectronic Materials and Technologies (Sun Yat-Sen University) (Grant No. OEMT-2023KF-05)。
文摘Metal–insulator–semiconductor(MOS) capacitor is a key structure for high performance MOS field transistors(MOSFETs), requiring low leakage current, high breakdown voltage, and low interface states. In this paper, β-Ga_(2)O_(3) MOS capacitors were fabricated with ALD deposited Al_(2)O_(3) using H_(2)O or ozone(O_(3)) as precursors. Compared with the Al_(2)O_(3) gate dielectric with H_(2)O as ALD precursor, the leakage current for the O_(3) precursor case is decreased by two orders of magnitude, while it keeps the same level at the fixed charges, interface state density, and border traps. The SIMS tests show that Al_(2)O_(3) with O_(3) as precursor contains more carbon impurities. The current transport mechanism analysis suggests that the C–H complex in Al_(2)O_(3) with O_(3) precursor serves as deep energy trap to reduce the leakage current. These results indicate that the Al_(2)O_(3)/β-Ga_(2)O_(3)MOS capacitor using the O_(3) precursor has a low leakage current and holds potential for application in β-Ga_(2)O_(3) MOSFETs.
基金Project supported by the National Natural Science Foundation of China(Grant No.61874017)。
文摘We investigate the effect of ozone(O_(3))oxidation of silicon carbide(SiC)on the flat-band voltage(Vfb)stability of SiC metal–oxide–semiconductor(MOS)capacitors.The SiC MOS capacitors are produced by O_(3)oxidation,and their Vfbstability under frequency variation,temperature variation,and bias temperature stress are evaluated.Secondary ion mass spectroscopy(SIMS),atomic force microscopy(AFM),and x-ray photoelectron spectroscopy(XPS)indicate that O_(3)oxidation can adjust the element distribution near SiC/SiO_(2)interface,improve SiC/SiO_(2)interface morphology,and inhibit the formation of near-interface defects,respectively.In addition,we elaborate the underlying mechanism through which O_(3)oxidation improves the Vfbstability of SiC MOS capacitors by using the measurement results and O_(3)oxidation kinetics.
基金Project supported by the National Natural Science Foundation of China （Grant No 60376019）.
文摘Trichloroethylene （TCE） pretreatment of Si surface prior to HfO2 deposition is employed to fabricate HfO2 gatedielectric MOS capacitors. Influence of this processing procedure on interlayer growth, HfO2/Si interface properties, gate-oxide leakage and device reliability is investigated. Among the surface pretreatments in NH3, NO, N2O and TCE ambients, the TCE pretreatment gives the least interlayer growths the lowest interface-state density, the smallest gate leakage and the highest reliability. All these improvements should be ascribed to the passivation effects of Cl2 and HC1 on the structural defects in the interlayer and at the interface, and also their gettering effects on the ion contamination in the gate dielectric.
基金supported by the State Key Development Program for Basic Research of China(No.2006CB302704)
文摘MOS capacitors with hafnium oxynitride（HfON）gate dielectrics were fabricated on Ge and Si substrates using the RF reactive magnetron sputtering method.A large amount of fixed charges and interface traps exist at the Ge/HfON interface.HRTEM and XPS analyses show that Ge oxides were grown and diffused into HfON after post metal annealing.A Si nitride interfacial layer was inserted between Ge and HfON as diffusion barrier.Using this method,well behaved capacitance–voltage and current–voltage characteristics were obtained.Finally hystereses are compared under different process conditions and possible causes are discussed.
基金This project is supported by Motorola (China) Electronics Ltd. and the work of Pingwen Zhang is also partially supported by Special Funds for Major State Basic Research Projects of China G1999032804.
文摘In this paper, we investigate multi-scale methods for the inverse modeling in 1-D Metal-Oxide-Silicon (MOS) capacitor. First, the mathematical model of the device is given and the numerical simulation for the forward problem of the model is implemented using finite element method with adaptive moving mesh. Then numerical analysis of these parameters in the model for the inverse problem is presented. Some matrix analysis tools are applied to explore the parameters' sensitivities. And third, the parameters are extracted using Levenberg-Marquardt optimization method. The essential difficulty arises from the effect of multi-scale physical difference of the parameters. We explore the relationship between the parameters' sensitivities and the sequence for optimization, which can seriously affect the final inverse modeling results. An optimal sequence can efficiently overcome the multi-scale problem of these parameters. Numerical experiments show the efficiency of the proposed methods.
基金Supported by National Natural Science Foundation of China(11375100)Strategic Pioneer Program on Space Sciences,Chinese Academy of Sciences(XDA04060606-06)State Key Laboratory of Particle Detection and Electronics
文摘SCAs （Switched Capacitor Arrays） have a wide range of uses, especially in high energy physics, nuclear science and astrophysics experiments. This paper presents a method of using a MOS capacitor as a sampling capacitor to gain larger capacitance with small capacitor area in SCA design. It studies the non-ideal effects of the MOS capacitor and comes up with ways to reduce these adverse effects. A prototype SCA ASIC which uses a MOS capacitor to store the samples has been designed and tested to verify this method. The SCA integrates 32 channels and each has 64 cells and a readout amplifier. The stored voltage is converted to a pair of differential currents （~ 4 mA max） and multiplexed to the output. All the functionalities have been verified. The power consumption is less than 2 mW/ch. The INL of all the cells in one channel are better than 0.39%. The equivalent input noise of the SCA has been tested to be 2.2 mV with 625 kHz full-scale sine wave as input, sampling at 40 MSPS （Mega-samples per Second） and reading out at 5 MHz. The effective resolution is 8.8 bits considering 1 V dynamic range. The maximum sampling rate reaches up to 50 MSPS and readout rate of 15 MHz to keep noise smaller than 2.5 mV. The test results validate the feasibility of the MOS capacitor.
基金This work is partially supported by National Science Foundation of China for Distinguished Young Scholars 10225103 and 90207009.
文摘The high frequency CV curves of MOS capacitor have been studied. It is shown that semiclassical model is a good approximation to quantum model and approaches to classical model when the oxide layer is thick. This conclusion provides us an efficient （semiclassical） model including quantum mechanical effects to do parameter extraction for ultrathin oxide device. Here the effective extracting strategy is designed and numerical experiments demonstrate the validity of the strategy.
基金supported by the National Natural Science Foundation of China (Nos. 60576029, 90607018)the Science and TechnologyCommittee of Shanghai Municipality (No. 07QA14004)+1 种基金the Shanghai-Applied Materials Research Development Fund (No. 07SA06)Fok Ying Tong Education Foundation (No. 114006).
文摘This paper investigates the capacitance-voltage （C-V） measurement on fully silicided （FUSI） gated metal-oxide-semiconductor （MOS） capacitors and the applicability of MOS capacitor models. When the oxide leakage current of an MOS capacitor is large, two-element parallel or series model cannot be used to obtain its real C-V characteristic. A three-element model simultaneously consisting of parallel conductance and series resistance or a four-element model with further consideration of a series inductance should be used. We employed the threeelement and the four-element models with the help of two-frequency technique to measure the Ni FUSI gated MOS capacitors. The results indicate that the capacitance of the MOS capacitors extracted by the three-element model still shows some frequency dispersion, while that extracted by the four-element model is close to the real capacitance, showing little frequency dispersion. The obtained capacitance can be used to calculate the dielectric thickness with quantum effect correction by NCSU C-V program. We also investigated the influence of MOS capacitor＇s area on the measurement accuracy. The results indicate that the decrease of capacitor area can reduce the dissipation factor and improve the measurement accuracy. As a result, the frequency dispersion of the measured capacitance is significantly reduced, and real C-V characteristic can be obtained directly by the series model. In addition, this paper investigates the quasi-static C-V measurement and the photonic high-frequency C-V measurement on Ni FUSI metal gated MOS capacitor with a thin leaky oxide. The results indicate that the large tunneling current through the gate oxide significantly perturbs the accurate measurement of the displacement current, which is essential for the quasi-static C-V measurement. On the other hand, the photonic high-frequency C-V measurement can bypass the leakage problem, and get reliable low-frequency C-V characteristic, which can be used to evaluate whether the full silicidation has completed or not, and to extract the interface trap density of the SiO2/Si interface.
文摘N-type and p-type 6H-SiC metal oxide semiconductor (MOS) capacitor samples are fabricated with a typical method,and the high frequency capacitor voltage (C-V) curves of these samples are measured at temperatures ranging from 293 to 533 K.There exists huge difference between the n-type and p-type samples.Flat-band voltage shift of the n-type sample becomes larger with temperature rising,but that of the p-type sample have very little change.This may be caused by the residual Al in the p-type oxide.Both types of the SiC samples follow the same rule of flat-band voltage changing with temperature.But their mechanisms are different as temperature is above 453 K.Of both types the p-type SiC is more suitable for high temperature applications.
文摘The frequency dependence of admittance measurements （capacitance–voltage （C–V ） and conductance–voltage （G/ω–V ）） of Au/SnO2 /n-Si （MOS） capacitors was investigated by taking into account the effects of the interface states （N ss ） and series resistance （Rs ） at room temperature. Admittance measurements were carried out in frequency and bias voltage ranges of 1 kHz–1 MHz and （ 5V）–（＋9V）, respectively. The values of N ss and R s were determined by using a conductance method and estimating from the admittance measurements of the MOS capacitors. At low frequencies, the interface states can follow the AC signal and yield excess capacitance and conductance. In addition, the parallel conductance （G p /ω） versus log（f） curves at various voltages include a peak due to the presence of interface states. It is observed that the N ss and their time constant （τ） range from 1.23 ×10 12 eV-1 ·cm-2 to 1.47 ×10 12 eV-1 ·cm-2 and from 7.29 ×10-5 s to 1.81 ×10-5s, respectively.
基金supported by the National Natural Science Foundation of China(Nos.61274077,61474031,61464003)the Guangxi Natural Science Foundation(Nos.2013GXNSFGA019003,2013GXNSFAA019335)+2 种基金the Project(No.9140C140101140C14069)the Innovation Project of GUET Graduate Education(No.YJCXS201529)the National Science&Technology Major Project of China(No.2011ZX02708-003)
文摘The impact of nitridation and sulfur passivation for Ino.s3Gao.47As surfaces on the A1/A1203/InGaAs MOS capacitors properties was investigated by comparing the characteristics of frequency dispersion and hysteresis, calculating the Dit and ANbt values, and analyzing the interface traps and the leakage current. The results showed that both of the methods could form a passivation-layer on the InGaAs surface. The samples treated by N2 plasma could obtain good interface properties with the smallest frequency dispersion in the accumulation region, and the best hysteresis characteristics and good I-V properties were presented. Also the samples with （NH4）ESx treatment showed the smallest frequency dispersion near the flat-band region and a minimum Dit value of 2.6 x10^11 cm-2 eV-1.
基金Project supported by the National Natural Science Foundation of China(No.60776058)the State Key Development Program for Basic Research of China (Nos.2007CB935400,2006CB302700)
文摘An MOS （metal oxide semiconductor） capacitor structure with double-layer heterogeneous nanocrystals consisting of semiconductor and metal embedded in a gate oxide for nonvolatile memory applications has been fabricated and characterized. By combining vacuum electron-beam co-evaporated Si nanocrystals and self-assembled Ni nanocrystals in a SiO2 matrix, an MOS capacitor with double-layer heterogeneous nanocrystals can have larger charge storage capacity and improved retention characteristics compared to one with single-layer nanocrystals. The upper metal nanocrystals as an additional charge trap layer enable the direct tunneling mechanism to enhance the flat voltage shift and prolong the retention time.
基金Funded by the National Natural Science Foundation of China (No. 61704113)the Higher Vocational Brand Mayer in Guangdong Province (No.610103)the Educational Science Planning Project of Guangdong Province (Higher Education Special)。
文摘The Ge metal-oxide-semiconductor (MOS) capacitors were fabricated with HfO2 as gate dielectric.AlON,NdON,and NdAlON were deposited between the gate dielectric and the Ge substrate as the interfacial passivation layer (IPL).The electrical properties (such as capacitance-voltage (C-V) and gate leakage current density versus gate voltage (J_(g)-V_(g))) were measured by HP4284A precision LCR meter and HP4156A semiconductor parameter analyzer.The chemical states and interfacial quality of the high-k/Ge interface were investigated by X-ray photoelectron spectroscopy (XPS).The experimental results show that the sample with the NdAlON as IPL exhibits the excellent interfacial and electrical properties.These should be attributed to an effective suppression of the Ge suboxide and HfGeOx interlayer,and an enhanced blocking role against inter-diffusion of the elements during annealing by the NdAlON IPL.
基金Project supported by the National Key Research and Development Program of China(Grant No.2017YFB0903203)the National Natural Science Foundation of China(Grant No.62004033)China Postdoctoral Science Foundation(Grant No.2020M683287)。
文摘In order to investigate the characteristics and mechanisms of subthreshold voltage hysteresis(ΔV_(th,sub)) of 4 H-SiC metal-oxide-semiconductor field-effect transistors(MOSFETs),4 H-SiC planar and trench MOSFETs and corresponding P-type planar and trench metal-oxide-semiconductor(MOS) capacitors are fabricated and characterized.Compared with planar MOSFEF,the trench MOSFET shows hardly larger ΔV_(th,sub) in wide temperature range from 25 0 C to 300 0 C.When operating temperature range is from 25 ℃ to 300 ℃,the off-state negative V_(gs) of planar and trench MOSFETs should be safely above-4 V and-2 V,respectively,to alleviate the effect of ΔV_(th,sub) on the normal operation.With the help of P-type planar and trench MOS capacitors,it is confirmed that the obvious ΔV_(th,sub) of 4 H-SiC MOSFET originates from the high density of the hole interface traps between intrinsic Fermi energy level(E_(i)) and valence band(E_(v)).The maximumΔV_(th,sub) of trench MOSFET is about twelve times larger than that of planar MOSFET,owing to higher density of interface states(D_(it)) between E_(i) and E_(v).These research results will be very helpful for the application of 4 H-SiC MOSFET and the improvement of ΔV_(th,sub) of 4 H-SiC MOSFET,especially in 4 H-SiC trench MOSFET.
文摘The purpose of this work relates to study on the characteristics of ultra thin gate oxide (2 5nm thickness) and the effect of metal Al,Zr,and Ta contamination on GOI.The controlled metallic contamination experiments are carried out by depositing a few ppm contaminated metal and low pH solutions on the wafers.The maximum metal surface concentration is controlled at about 10 12 cm -2 level in order to simulate metal contamination during ultra clean processing.A ramped current stress for intrinsic charge to breakdown measurements with gate injection mode is used to examine the characteristics of these ultra thin gate oxides and the effect of metal contamination on GOI.It is the first time to investigate the influence of metal Zr and Ta contamination on 2 5nm ultra thin gate oxide.It is demonstrated that there is little effect of Al contamination on GOI,while Zr contamination is the most detrimental to GOI,and early breakdown has happened to wafers contaminated by Ta.
基金This work was supported by National Research Foundation of Korea[NRF-2019R1A2C2003804 and 2018H1D3A1A02074733]of the Ministry of Science and ICTRepublic of Korea and the technology development program(G21S272158901)funded by the Ministry of SMEs and Startups,Republic of Korea.This work was also supported by Ajou University.
文摘An ultrathin SrTiO3 dielectric layer is optimized through Al doping to solve the problems existing in development of ultra-high-k oxide MOS capacitors.Through post-deposition annealing,Al doping induces changes in the electronic structure of SrTiO3,thereby effectively reducing leakage current to <10^-8 A/cm^2 at 0.5 MV/cm but maintains good capacitance values(ε> 80) of ultrathin SrTMO3 MOS capacitors.Strontium titanate(SrTiO3) is a high-k material but its bandgap is smaller than that of other oxide dielectrics(e.g.,SiO2,Al2 O3).Consequently,an ultrathin SrTiO3 film may have a high tunneling leakage current,which is not suitable for capacitor-based applications.To improve the performance of metal-oxide-semiconductor(MOS) capacitors using SrTiO3,an approach based on homogenous and uniform aluminum doping to SrTiO3 through co-sputtering is introduced.The bandgap of a pristine SrTiO3 film showed an increase of 0.5 eV after Al doping.Furthermore,Al doping decreased the leakage current of SrTiO3/Si-based MOS capacitors by more than five orders of magnitude(at the level of nanoampere per square centimeter).Importantly,a dielectric constant of 81.3 and equivalent oxide thickness less than 5 A were achieved in an 8-nm-thick Al-doped SrTiO3 film owing to changes in its crystal structure and conduction band edge electronic structure.Thus,the obtained data show the effectiveness of the proposed approach for solving the problems existing in the development of ultra-high-k oxide MOS capacitors.
基金Project supported by the National Natural Science Foundation of China (Grant No 50772107)the National High Technology Development Program of China (Grant No 2006AA05Z118)
文摘The surface oxidation of silicon （Si） wafers by atomic oxygen radical anions （O- anions） and the preparation of metal-oxide-semiconductor （MOS） capacitors on the O-oxidized Si substrates have been examined for the first time. The O- anions are generated from a recently developed O- storage-emission material of [Ca24Al2sO64]^4＋·4O^- （Cl2A7-O^- for short）. After it has been irradiated by an O- anion bean： （0.5 μA/cm^2） at 300℃ for 1-10 hours, the Si wafer achieves an oxide layer with a thickness ranging from 8 to 32 nm. X-ray photoelectron spectroscopy （XPS） results reveal that the oxide layer is of a mixture of SiO2, Si2 O3, and Si2O distributed in different oxidation depths. The features of the MOS capacitor of 〈Al electrode/SiOx/Si〉 are investigated by measuring capacitance-voltage （C - V） and current-voltage （I - V） curves. The oxide charge density is about 6.0 × 10^1 cm^-2 derived from the （C - V curves. The leakage current density is in the order of 10^-6 A/cm^2 below 4 MV/cm, obtained from the I - V curves. The O- anions formed by present method would have potential applications to the oxidation and the surface-modification of materials together with the preparation of semiconductor devices.
基金supported by the National Natural Science Foundation of China(Grant Nos.51272202 and 61234006)the Science Project of State Grid,China(Grant No.SGRI-WD-71-14-004)
文摘We study a series of（HfO2）x（Al2O3）1-x /4H-SiC MOS capacitors. It is shown that the conduction band offset of HfO2 is 0.5 e V and the conduction band offset of Hf AlO is 1.11–1.72 e V. The conduction band offsets of（Hf O2）x（Al2O3）1-x are increased with the increase of the Al composition, and the（HfO2）x（Al2O3）1-x offer acceptable barrier heights（〉 1 e V）for both electrons and holes. With a higher conduction band offset,（Hf O2）x（Al2O3）1-x/4H-SiC MOS capacitors result in a ～ 3 orders of magnitude lower gate leakage current at an effective electric field of 15 MV/cm and roughly the same effective breakdown field of ～ 25 MV/cm compared to HfO2. Considering the tradeoff among the band gap, the band offset, and the dielectric constant, we conclude that the optimum Al2O3 concentration is about 30% for an alternative gate dielectric in 4H-Si C power MOS-based transistors.
基金supported by the National Natural Science Foundation of China(No.61274112)the Natural Science Foundation of Hubei Province(No.2011CDB165)the Scientific Research Program of Huanggang Normal University(No.2012028803)
文摘LaON,LaTiO and LaTiON films are deposited as gate dielectrics by incorporating N or/and Ti into La_2O_3 using the sputtering method to fabricate Ge MOS capacitors,and the electrical properties of the devices are carefully examined.LaON/Ge capacitors exhibit the best interface quality,gate leakage property and device reliability,but a smaller k value（14.9）.LaTiO/Ge capacitors exhibit a higher k value（22.7）,but a deteriorated interface quality,gate leakage property and device reliability.LaTiON/Ge capacitors exhibit the highest k value（24.6）,and a relatively better interface quality（3.1×10^（11） eV^（-1）cm^（-2））,gate leakage property（3.6 × 10^（-3） A/cm^2 at V_g = 1V＋V_（fb）） and device reliability.Therefore,LaTiON is more suitable for high performance Ge MOS devices as a gate dielectric than LaON and LaTiO materials.
基金Project supported by the Important National Science & Technology Specific Projects of China(No.2009ZX02035)the National Natural Science Foundation of China(Nos.61176091,50932001)
文摘The effect of Al incorporation on the effective work function（EWF） of TiN metal gate was systematically investigated.Metal-oxide-semiconductor（MOS） capacitors with W/TiN/Al/TiN gate stacks were used to fulfill this purpose.Different thickness ratios of Al to TiN and different post metal annealing（PMA） conditions were employed.Significant shift of work function towards to Si conduction band was observed,which was suitable for NMOS and the magnitude of shift depends on the processing conditions.
