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基于缩短极化码的MLC NAND Flash差错控制技术研究 被引量:6
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作者 郭锐 王美洁 王杰 《电子与信息学报》 EI CSCD 北大核心 2017年第7期1658-1665,共8页
为了提高MLC NAND Flash的抗误码性能,该文提出一种基于优化缩短极化码的MLC NAND Flash差错控制方法。优化缩短极化码通过优化删减图样得到,首先通过比特翻转重排序的方式得到基本删减图样,进而选择具有更低信道容量的冻结比特组成优... 为了提高MLC NAND Flash的抗误码性能,该文提出一种基于优化缩短极化码的MLC NAND Flash差错控制方法。优化缩短极化码通过优化删减图样得到,首先通过比特翻转重排序的方式得到基本删减图样,进而选择具有更低信道容量的冻结比特组成优化删减图样,使得到的删减比特全为冻结比特,可以显著提高删减算法的纠错性能。同时,根据MLC单元错误的不对称性,采用码率自适应的码字对FLASH中MSB和LSB进行不等错误保护。仿真结果表明:当误帧率为310-时,优化缩短极化码较相同码长的LDPC码和基本缩短极化码分别约有3.72~5.89 d B和1.47~3.49 d B增益;相比基于同一码率的优化缩短极化码方案,不等错误保护的差错控制方案获得约0.25 d B增益。 展开更多
关键词 极化码 多层单元 nand flash 缩短码 不等错误保护
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一种含BCH编解码器的SLC/MLC NAND FLASH控制器的VLSI设计 被引量:11
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作者 李璐 周海燕 《现代电子技术》 2009年第7期167-170,共4页
为了满足存储器市场对低单比特成本和高存储密度的需求,在一款基于ARM926EJ的片上处理器芯片中,集成了一个可支持SLC/MLC NAND FLASH的控制器。为了纠正FLASH存储器芯片中的随机错误,采用了可纠4比特错误的BCH纠错码,该纠错码非常适应N... 为了满足存储器市场对低单比特成本和高存储密度的需求,在一款基于ARM926EJ的片上处理器芯片中,集成了一个可支持SLC/MLC NAND FLASH的控制器。为了纠正FLASH存储器芯片中的随机错误,采用了可纠4比特错误的BCH纠错码,该纠错码非常适应NAND类型存储器的随机错误特点。该控制器可支持多种类型的NAND FLASH。另外,对一种基于伯利坎普-梅西算法的高效BCH编解码器VLSI结构进行了研究,采用一种简化伯利坎普-梅西算法实现的低复杂度的关键方程解算机消除其速度瓶颈。芯片采用SMIC 0.13μm CMOS工艺。测试结果证明,设计电路完全符合系统规范,性能表现优良。 展开更多
关键词 mlc nand flash控制器 BCH 编解码 伯利坎普-梅西算法 VLSI
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Low-Complexity Detection and Decoding Scheme for LDPC-Coded MLC NAND Flash Memory 被引量:1
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作者 Xusheng Lin Guojun Han +2 位作者 Shijie Ouyang Yanfu Li Yi Fang 《China Communications》 SCIE CSCD 2018年第6期58-67,共10页
With the development of manufacture technology, the multi-level cell(MLC)technique dramatically increases the storage density of NAND flash memory. As the result,cell-to-cell interference(CCI) becomes more serious and... With the development of manufacture technology, the multi-level cell(MLC)technique dramatically increases the storage density of NAND flash memory. As the result,cell-to-cell interference(CCI) becomes more serious and hence causes an increase in the raw bit error rate of data stored in the cells.Recently, low-density parity-check(LDPC)codes have appeared to be a promising solution to combat the interference of MLC NAND flash memory. However, the decoding complexity of the sum-product algorithm(SPA) is extremely high. In this paper, to improve the accuracy of the log likelihood ratio(LLR) information of each bit in each NAND flash memory cell, we adopt a non-uniform detection(N-UD) which uses the average maximum mutual information to determine the value of the soft-decision reference voltages.Furthermore, with an aim to reduce the decoding complexity and improve the decoding performance, we propose a modified soft reliabilitybased iterative majority-logic decoding(MSRBI-MLGD) algorithm, which uses a non-uniform quantizer based on power function to decode LDPC codes. Simulation results show that our design can offer a desirable trade-off between the performance and complexity for high-column-weight LDPC-coded MLC NAND flash memory. 展开更多
关键词 Cell-to-cell interference(CCI) LDPC codes mlc nand flash memory non-uniform detection(N-UD) modified soft reliability-based iterative majority-logic decoding(MSRBI-MLGD) algorithm
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LDPC Coding Scheme for Improving the Reliability of Multi-Level-Cell NAND Flash Memory in Radiation Environments 被引量:2
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作者 Guangjun Ge Liuguo Yin 《China Communications》 SCIE CSCD 2017年第8期10-21,共12页
Utilizing commercial off-the-shelf(COTS) components in satellites has received much attention due to the low cost. However, commercial memories suffer severe reliability problems in radiation environments. This paper ... Utilizing commercial off-the-shelf(COTS) components in satellites has received much attention due to the low cost. However, commercial memories suffer severe reliability problems in radiation environments. This paper studies the low-density parity-check(LDPC) coding scheme for improving the reliability of multi-level-cell(MLC) NAND Flash memory in radiation environments. Firstly, based on existing physical experiment works, we introduce a new error model for heavyion irradiations; secondly, we explore the optimization of writing voltage allocation to maximize the capacity of the storage channel; thirdly, we design the degree distribution of LDPC codes that is specially suitable for the proposed model; finally, we propose a joint detection-decoding scheme based on LDPC codes, which estimates the storage channel state and executes an adaptive log-likelihood ratio(LLR) calculation to achieve better performance. Simulation results show that, compared with the conventional LDPC coding scheme, the proposed scheme may almost double the lifetime of the MLC NAND Flash memory in radiation environments. 展开更多
关键词 low-density parity-check(LDPC) coding multi-level-cell(mlc nand flash memory joint detection-decoding commercial off-the-shelf(COTS) components space radiation environments
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WinCE系统中MLC型闪存的编程支持研究 被引量:2
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作者 张纪艳 张萌 张伟伟 《计算机技术与发展》 2010年第2期60-63,67,共5页
基于WinCE 6.0操作系统,以实现WinCE下驱动程序对MLC NAND闪存的支持及其驱动程序性能的提高为目的。介绍了NAND闪存驱动程序的整体架构;对Flash抽象层的功能及地址映射关系的建立进行分析,讨论了引用版本号的概念为MLC NAND闪存建立地... 基于WinCE 6.0操作系统,以实现WinCE下驱动程序对MLC NAND闪存的支持及其驱动程序性能的提高为目的。介绍了NAND闪存驱动程序的整体架构;对Flash抽象层的功能及地址映射关系的建立进行分析,讨论了引用版本号的概念为MLC NAND闪存建立地址映射关系的过程,使Flash抽象层程序可以支持MLC NAND;对Flash介质驱动层进行分析,介绍了采用两片编程技术提高驱动性能的原理与实现,及4位ECC校验的步骤;经对两片编程与单片编程方式的写速度测试,结果表明前者比后者速度提高了92.2%。 展开更多
关键词 mlcnandflash nandflash驱动 地址映射 两片编程 4位ECC
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