To address the challenges of complexity,power consumption,and cost constraints in traditional display driver integrated circuits(DDICs)caused by external NOR Flash and SRAM,this work proposes an embedded resistive ran...To address the challenges of complexity,power consumption,and cost constraints in traditional display driver integrated circuits(DDICs)caused by external NOR Flash and SRAM,this work proposes an embedded resistive random-access memory(RRAM)integration solution based on a 40 nm high-voltage CMOS logic platform.Targeting the yield fluctuations and stability challenges during RRAM mass production,systematic process optimizations are implemented to achieve synergistic improvements in RRAM performance and yield.Through modifications to the film sputtering and pre-deposition treatment,the withinwafer resistance uniformity(RSU)of the oxygen-deficient layer(ODL)thin film is improved from 11%to 8%,while inter-wafer process stability variation reduces from 23%to below 6%.Consequently,the yield of 8 Mb RRAM embedded mass production products increases from 87%to 98.5%.In terms of device performance,the RRAM demonstrates a fast 4.8 ns read speed,exceptional read disturb immunity of 3×10^(8) cycles at 95℃,10^(3) write/erase endurance cycles for the 1 Mb cells,and data retention of 12.5 years at 125℃.Post high-temperature operating life(HTOL)testing exhibits stable high/low resistance window.This study provides process optimization strategies and a reliability assurance framework for the mass production of highly integrated,low-power embedded RRAM display driver IC.展开更多
A novel method to characterize CMOS process fluctuations in subthreshold current mirrors （SCM） is reported. The proposed model is succinct in methodology and calculation complexity compared with previous statistical...A novel method to characterize CMOS process fluctuations in subthreshold current mirrors （SCM） is reported. The proposed model is succinct in methodology and calculation complexity compared with previous statistical models. However,it provides favorable estimations of CMOS process fluctuations on the SCM circuit, which makes it promising for engineering applications. The model statistically abstracts physical parameters, which depend on the IC process, into random variables with certain mean values and standard deviations, while aggregating all the random impacts into a discrete martingale. The correctness of the proposed method is experimentally verified on an SCM circuit implemented in an SMIC 0.18μm CMOS 1P6M mixed signal process with a conversion factor of 100 in an input range from 100pA to lμA. The pro- posed theory successfully predicts - 10% of die-to-die fluctuation measured in the experiment, and also suggests the -lmV of threshold voltage standard deviation over a single die,which meets the process parameters suggested by the design kit from the foundry. The deviations between calculated probabilities and measured data are less than 8%. Meanwhile, pertinent suggestions concerning high fluctuation tolerance subthreshold analog circuit design are also made and discussed.展开更多
There is growing interest in developing high-voltage MOSFET devices that can be integrated with low-voltage CMOS digital and analog circuits. In this paper,high-voltage nand p-type MOSFETs are fabricated in a commerci...There is growing interest in developing high-voltage MOSFET devices that can be integrated with low-voltage CMOS digital and analog circuits. In this paper,high-voltage nand p-type MOSFETs are fabricated in a commercial 3.3/ 5V 0.5μm n-well CMOS process without adding any process steps using n-well and p-channel stops. High current and highvoltage transistors with breakdown voltages between 23 and 35V for the nMOS transistors with different laydut parameters and 19V for the pMOS transistors are achieved. This paper also presents the insulation technology and characterization results for these high-voltage devices.展开更多
This paper presents a 1.2 V high accuracy thermal sensor analog front-end circuit with 7 probes placed around the microprocessor chip.This analog front-end consists of a BGR(bandgap reference),a DEM(dynamic element ma...This paper presents a 1.2 V high accuracy thermal sensor analog front-end circuit with 7 probes placed around the microprocessor chip.This analog front-end consists of a BGR(bandgap reference),a DEM(dynamic element matching)control,and probes.The BGR generates the voltages linear changed with temperature,which are followed by the data read out circuits.The superior accuracy of the BGR’s output voltage is a key factor for sensors fabricated via the FinFET digital process.Here,a 4-stage folded current bias structure is proposed,to increase DC accuracy and confer immunity against FinFET process variation due to limited device length and low current bias.At the same time,DEM is also adopted,so as to filter out current branch mismatches.Having been fabricated via a 12 nm FinFET CMOS process,200 chips were tested.The measurement results demonstrate that these analog front-end circuits can work steadily below 1.2 V,and a less than 3.1%3σ-accuracy level is achieved.Temperature stability is 0.088 mV/℃across a range from-40 to 130℃.展开更多
A CMOS integrated signal processing circuit based on capacitance resonance principle whose structure is simple in capacitive sensors is designed. The waveform of output voltage is improved by choosing bootstrap refere...A CMOS integrated signal processing circuit based on capacitance resonance principle whose structure is simple in capacitive sensors is designed. The waveform of output voltage is improved by choosing bootstrap reference current mirror with initiate circuit, CMOS analogy switch and positive feedback of double-stage inverter in the circuit. Output voltage of this circuit is a symmetric square wave signal. The variation of sensitive capacitance, which is part of the capacitive sensors, can be denoted by the change of output vohage＇s frequency. The whole circuit is designed with 1.5 μm P-weU CMOS process and simulated by PSpice software. Output frequency varies from 261.05 kHz to 47. 93 kHz if capacitance varies in the range of 1PF - 15PF. And the variation of frequency can be easily detected using counter or SCU.展开更多
A novel integrated ultraviolet（UV） photodetector has been proposed, which realizes a high UV selectivity by combining a conventional UV-selective photodiode with an extra infrared（IR） photodiode. The IR photodiode...A novel integrated ultraviolet（UV） photodetector has been proposed, which realizes a high UV selectivity by combining a conventional UV-selective photodiode with an extra infrared（IR） photodiode. The IR photodiode is designed for compensating the photocurrent response of the UV photodiode in the infrared band and is 15 times smaller than the UV one. The integrated photodetector has been fabricated in a 0.35 μm standard CMOS technology. Some critical performance indices of this new structure photodetector, such as spectral responsivity, breakdown voltage, quenching waveform, and transient response, are measured and analyzed. Test results show that the complementary UV–IR photodetector has a maximum spectral responsivity of 0.27 A·W-1 at the wavelength of 400 nm. The device has a high UV selectivity of 3000,which is much higher than that of the single UV photodiode.展开更多
In this paper, we present the implementation of a built-in current sensor (BICS) which takes into account the increased background current of defect-free circuits and the effects of process variation on ΔIDDQ testing...In this paper, we present the implementation of a built-in current sensor (BICS) which takes into account the increased background current of defect-free circuits and the effects of process variation on ΔIDDQ testing of CMOS data converters. A 12-bit digital-to-analog converter (DAC) is designed as the circuit under test (CUT). The BICS uses frequency as the output for fault detection in CUT. A fault is detected if it causes the output frequency to deviate more than ±10% from the reference frequency. The output frequencies of the BICS for various (MOSIS) model parameters are simulated to check for the effect of process variation on the frequency deviation. A set of eight faults simulating manufacturing defects in CMOS data converters are injected using fault-injection transistors and tested successfully.展开更多
文摘To address the challenges of complexity,power consumption,and cost constraints in traditional display driver integrated circuits(DDICs)caused by external NOR Flash and SRAM,this work proposes an embedded resistive random-access memory(RRAM)integration solution based on a 40 nm high-voltage CMOS logic platform.Targeting the yield fluctuations and stability challenges during RRAM mass production,systematic process optimizations are implemented to achieve synergistic improvements in RRAM performance and yield.Through modifications to the film sputtering and pre-deposition treatment,the withinwafer resistance uniformity(RSU)of the oxygen-deficient layer(ODL)thin film is improved from 11%to 8%,while inter-wafer process stability variation reduces from 23%to below 6%.Consequently,the yield of 8 Mb RRAM embedded mass production products increases from 87%to 98.5%.In terms of device performance,the RRAM demonstrates a fast 4.8 ns read speed,exceptional read disturb immunity of 3×10^(8) cycles at 95℃,10^(3) write/erase endurance cycles for the 1 Mb cells,and data retention of 12.5 years at 125℃.Post high-temperature operating life(HTOL)testing exhibits stable high/low resistance window.This study provides process optimization strategies and a reliability assurance framework for the mass production of highly integrated,low-power embedded RRAM display driver IC.
文摘A novel method to characterize CMOS process fluctuations in subthreshold current mirrors （SCM） is reported. The proposed model is succinct in methodology and calculation complexity compared with previous statistical models. However,it provides favorable estimations of CMOS process fluctuations on the SCM circuit, which makes it promising for engineering applications. The model statistically abstracts physical parameters, which depend on the IC process, into random variables with certain mean values and standard deviations, while aggregating all the random impacts into a discrete martingale. The correctness of the proposed method is experimentally verified on an SCM circuit implemented in an SMIC 0.18μm CMOS 1P6M mixed signal process with a conversion factor of 100 in an input range from 100pA to lμA. The pro- posed theory successfully predicts - 10% of die-to-die fluctuation measured in the experiment, and also suggests the -lmV of threshold voltage standard deviation over a single die,which meets the process parameters suggested by the design kit from the foundry. The deviations between calculated probabilities and measured data are less than 8%. Meanwhile, pertinent suggestions concerning high fluctuation tolerance subthreshold analog circuit design are also made and discussed.
文摘There is growing interest in developing high-voltage MOSFET devices that can be integrated with low-voltage CMOS digital and analog circuits. In this paper,high-voltage nand p-type MOSFETs are fabricated in a commercial 3.3/ 5V 0.5μm n-well CMOS process without adding any process steps using n-well and p-channel stops. High current and highvoltage transistors with breakdown voltages between 23 and 35V for the nMOS transistors with different laydut parameters and 19V for the pMOS transistors are achieved. This paper also presents the insulation technology and characterization results for these high-voltage devices.
基金This work was supported by the National Natural Science Foundation of China(No.61432016 and No.61521092)the Key Program of the Chinese Academy of Sciences(ZDRWXH-2017-1)the Strategic Priority Research Program of the Chinese Academy of Sciences(No.XDC05020000).
文摘This paper presents a 1.2 V high accuracy thermal sensor analog front-end circuit with 7 probes placed around the microprocessor chip.This analog front-end consists of a BGR(bandgap reference),a DEM(dynamic element matching)control,and probes.The BGR generates the voltages linear changed with temperature,which are followed by the data read out circuits.The superior accuracy of the BGR’s output voltage is a key factor for sensors fabricated via the FinFET digital process.Here,a 4-stage folded current bias structure is proposed,to increase DC accuracy and confer immunity against FinFET process variation due to limited device length and low current bias.At the same time,DEM is also adopted,so as to filter out current branch mismatches.Having been fabricated via a 12 nm FinFET CMOS process,200 chips were tested.The measurement results demonstrate that these analog front-end circuits can work steadily below 1.2 V,and a less than 3.1%3σ-accuracy level is achieved.Temperature stability is 0.088 mV/℃across a range from-40 to 130℃.
文摘A CMOS integrated signal processing circuit based on capacitance resonance principle whose structure is simple in capacitive sensors is designed. The waveform of output voltage is improved by choosing bootstrap reference current mirror with initiate circuit, CMOS analogy switch and positive feedback of double-stage inverter in the circuit. Output voltage of this circuit is a symmetric square wave signal. The variation of sensitive capacitance, which is part of the capacitive sensors, can be denoted by the change of output vohage＇s frequency. The whole circuit is designed with 1.5 μm P-weU CMOS process and simulated by PSpice software. Output frequency varies from 261.05 kHz to 47. 93 kHz if capacitance varies in the range of 1PF - 15PF. And the variation of frequency can be easily detected using counter or SCU.
基金supported by the National Natural Science Foundation of China(Grant No.61274043)the Key Project of the Ministry of Education of China(Grant No.212125)the State Key Program of the National Natural Science Foundation of China(Grant No.61233010)
文摘A novel integrated ultraviolet（UV） photodetector has been proposed, which realizes a high UV selectivity by combining a conventional UV-selective photodiode with an extra infrared（IR） photodiode. The IR photodiode is designed for compensating the photocurrent response of the UV photodiode in the infrared band and is 15 times smaller than the UV one. The integrated photodetector has been fabricated in a 0.35 μm standard CMOS technology. Some critical performance indices of this new structure photodetector, such as spectral responsivity, breakdown voltage, quenching waveform, and transient response, are measured and analyzed. Test results show that the complementary UV–IR photodetector has a maximum spectral responsivity of 0.27 A·W-1 at the wavelength of 400 nm. The device has a high UV selectivity of 3000,which is much higher than that of the single UV photodiode.
文摘In this paper, we present the implementation of a built-in current sensor (BICS) which takes into account the increased background current of defect-free circuits and the effects of process variation on ΔIDDQ testing of CMOS data converters. A 12-bit digital-to-analog converter (DAC) is designed as the circuit under test (CUT). The BICS uses frequency as the output for fault detection in CUT. A fault is detected if it causes the output frequency to deviate more than ±10% from the reference frequency. The output frequencies of the BICS for various (MOSIS) model parameters are simulated to check for the effect of process variation on the frequency deviation. A set of eight faults simulating manufacturing defects in CMOS data converters are injected using fault-injection transistors and tested successfully.
文摘针对融合射频识别（RFID）的无线温度传感器节点设计的需求,采用0.18μm 1P6M台积电CMOS工艺,设计了一种低功耗集成温度传感器。该温度传感器首先将温度信号转换为电压信号,然后通过经压控振荡器将电压信号转换为受温度控制的频率信号,再通过计数器,将频率信号转换为数字信号。传感器电路利用MOS管工作在亚阈值区,并采用动态阈值技术获得超低功耗。测试结果显示：所设计的温度传感器仅占用0.051 mm2,功耗仅为101 n W,在0~100℃范围内误差为-1.5~1.2℃。
