The achievable bit error rate of a linear equalizer is crucially determined by the choice of a decision delay parameter. This brief paper presents a simple method for the efficient determination of the optimal decisio...The achievable bit error rate of a linear equalizer is crucially determined by the choice of a decision delay parameter. This brief paper presents a simple method for the efficient determination of the optimal decision delay parameter that results in the best bit error rate performance for a linear equalizer. Keywords Linear equalizer - decision delay - bit error rate Eng Siong Chng received his university education at the University of Edinburgh, Edinburgh, Scotland (BEng 1991, PhD 1995). After his PhD, he spent 6 months in Japan, working as a researcher for Riken. After working in industry in Singapore for 7 years, he joined the School of Computer Engineering, Nanyang Technological University in 2003. His research interests are in digital signal processing for communication applications, speech and handwriting recognition and noise reduction.Sheng Chen obtained a BEng degree in control engineering from the East China Petroleum Institute, Dongying, China, in 1982, and a PhD degree in control engineering from the City University at London in 1986. He joined the School of Electronics and Computer Science at the University of Southampton in September 1999. He previously held research and academic appointments at the Universities of Sheffield, Edinburgh and Portsmouth. Dr Chen is a Senior Member of the IEEE in the USA. His recent research works include adaptive nonlinear signal processing, modeling and identification of nonlinear systems, neural networks and machine learning, finite-precision digital controller design, evolutionary computation methods and optimization. He has published over 200 research papers. In the database of the world’s most highly cited researchers in various disciplines, compiled by the Institute for Scientific Information (ISI) of the USA, Dr Chen is on the list of highly cited researchers in the category that covers all branches of engineering subject, see www.ISIHighlyCited.com.展开更多
A 28/56 Gb/s NRZ/PAM-4 dual-mode transceiver(TRx)designed in a 28-nm complementary metal-oxide-semiconduc-tor(CMOS)process is presented in this article.A voltage-mode(VM)driver featuring a 4-tap reconfigurable feed-fo...A 28/56 Gb/s NRZ/PAM-4 dual-mode transceiver(TRx)designed in a 28-nm complementary metal-oxide-semiconduc-tor(CMOS)process is presented in this article.A voltage-mode(VM)driver featuring a 4-tap reconfigurable feed-forward equal-izer(FFE)is employed in the quarter-rate transmitter(TX).The half-rate receiver(RX)incorporates a continuous-time linear equal-izer(CTLE),a 3-stage high-speed slicer with multi-clock-phase sampling,and a clock and data recovery(CDR).The experimen-tal results show that the TRx operates at a maximum speed of 56 Gb/s with chip-on board(COB)assembly.The 28 Gb/s NRZ eye diagram shows a far-end vertical eye opening of 210 mV with an output amplitude of 351 mV single-ended and the 56 Gb/s PAM-4 eye diagram exhibits far-end eye opening of 33 mV(upper-eye),31 mV(mid-eye),and 28 mV(lower-eye)with an output amplitude of 353 mV single-ended.The recovered 14 GHz clock from the RX exhibits random jitter(RJ)of 469 fs and deterministic jitter(DJ)of 8.76 ps.The 875 Mb/s de-multiplexed data features 593 ps horizontal eye opening with 32.02 ps RJ,at bit-error rate(BER)of 10-5(0.53 UI).The power dissipation of TX and RX are 125 and 181.4 mW,respectively,from a 0.9-V sup-ply.展开更多
This paper deals with the problem of designing a robust discrete output-feedback based repetitive-control system for a class of linear plants with periodic uncertainties. The periodicity of the repetitive-control syst...This paper deals with the problem of designing a robust discrete output-feedback based repetitive-control system for a class of linear plants with periodic uncertainties. The periodicity of the repetitive-control system is exploited to establish a two-dimensional （2D） model that converts the design problem into a robust stabilization problem for a discrete 2D system. By employing Lyapunov stability theory and the singular-value decomposition of the output matrix, a linear-matrix-inequality （LMI） based stability condition is derived. The condition can be used directly to design the gains of the repetitive controller. Two tuning parameters in the LMI enable the preferential adjustment of control and learning. A numerical example illustrates the design procedure and demonstrates the validity of the method.展开更多
A residual carrier frequency offset （CFO） estimation scheme is proposed for the uplink of orthogonal frequency division multiple access （OFDMA） systems. Multiple access interference caused by CFOs in the uplink is...A residual carrier frequency offset （CFO） estimation scheme is proposed for the uplink of orthogonal frequency division multiple access （OFDMA） systems. Multiple access interference caused by CFOs in the uplink is investigated, as it severely affects the performance of a classical maximum likelihood （ML） frequency estimator. By the use of the estimated CFOs of the active users, the linear maximum mean square error （LMMSE） equalization is performed before the ML frequency estimator for the interference cancellation, which can help to sufficiently improve the estimation accuracy for the residual CFO of the incoming user. Analysis and simulations show that the modified ML estimator provides a tradeoff between estimation accuracy and computational complexity caused by the LMMSE interference cancellation, and the proposed method allows OFDMA systems flexibly allocating subcarriers to users.展开更多
A new method of moving asymptotes for large-scale minimization subject to linear equality constraints is discussed. In this method, linear equality constraints are deleted with null space technique and the descending ...A new method of moving asymptotes for large-scale minimization subject to linear equality constraints is discussed. In this method, linear equality constraints are deleted with null space technique and the descending direction is obtained by solving a convex separable subproblem of moving asymptotes in each iteration. New rules for controlling the asymptotes parameters are designed and the global convergence of the method under some reasonable conditions is established and proved. The numerical results show that the new method may be capable of processing some large scale problems.展开更多
This work presents a PAM4 receiver analog frontend(AFE)operating up to 64 Gb/s.The electronic integrated circuit(EIC)is fabricated in 40-nm CMOS technology.This AFE is composed of a single-stage Continuous-Time Linear...This work presents a PAM4 receiver analog frontend(AFE)operating up to 64 Gb/s.The electronic integrated circuit(EIC)is fabricated in 40-nm CMOS technology.This AFE is composed of a single-stage Continuous-Time Linear Equalizer(CTLE),a Variable Gain Amplifier(VGA),an input impedance matching network,a buffer stage,and an output buffer.The single-stage triple-peaking CTLE proposed employs current reuse technique and a multi-feedback structure,enabling the adjustment of peaking in the low,mid,and high-frequency bands.Thus,only one-stage CTLE is sufficient to achieve an over-20-dB boost at Nyquist frequency to save power.The VGA adopts an enhanced structure based on the Gilbert cell,where the gain is manipulated by controlling the gate voltage of MOS transistors.The CTLE undergoes variations in its DC gain during the adjustment process to equalize channel losses.The role of the VGA is to stable the DC gain changes induced by the adjustment of the CTLE.The output buffer adopts two stages,aiming to ensure that the gain does not attenuate excessively while maintaining output impedance matching.The AFE consumes 21.1 mW with a supply voltage of 1.5/1 V.It can provide a maximum boost of 22.5 dB,and the data rate reaches up to 64 Gb/s.Additionally,it features peaking adjustment capabilities in the low,mid,and high-frequency bands.Finally,the measurement demonstrates its ability to effectively equalize a channel with a 12-dB loss at the Nyquist frequency of 16 GHz.展开更多
文摘The achievable bit error rate of a linear equalizer is crucially determined by the choice of a decision delay parameter. This brief paper presents a simple method for the efficient determination of the optimal decision delay parameter that results in the best bit error rate performance for a linear equalizer. Keywords Linear equalizer - decision delay - bit error rate Eng Siong Chng received his university education at the University of Edinburgh, Edinburgh, Scotland (BEng 1991, PhD 1995). After his PhD, he spent 6 months in Japan, working as a researcher for Riken. After working in industry in Singapore for 7 years, he joined the School of Computer Engineering, Nanyang Technological University in 2003. His research interests are in digital signal processing for communication applications, speech and handwriting recognition and noise reduction.Sheng Chen obtained a BEng degree in control engineering from the East China Petroleum Institute, Dongying, China, in 1982, and a PhD degree in control engineering from the City University at London in 1986. He joined the School of Electronics and Computer Science at the University of Southampton in September 1999. He previously held research and academic appointments at the Universities of Sheffield, Edinburgh and Portsmouth. Dr Chen is a Senior Member of the IEEE in the USA. His recent research works include adaptive nonlinear signal processing, modeling and identification of nonlinear systems, neural networks and machine learning, finite-precision digital controller design, evolutionary computation methods and optimization. He has published over 200 research papers. In the database of the world’s most highly cited researchers in various disciplines, compiled by the Institute for Scientific Information (ISI) of the USA, Dr Chen is on the list of highly cited researchers in the category that covers all branches of engineering subject, see www.ISIHighlyCited.com.
基金supported by National Natural Science Foundation of China under Grant 62174132the Fundamental Research Funds for Central Universities under Grant xzy022022060.
文摘A 28/56 Gb/s NRZ/PAM-4 dual-mode transceiver(TRx)designed in a 28-nm complementary metal-oxide-semiconduc-tor(CMOS)process is presented in this article.A voltage-mode(VM)driver featuring a 4-tap reconfigurable feed-forward equal-izer(FFE)is employed in the quarter-rate transmitter(TX).The half-rate receiver(RX)incorporates a continuous-time linear equal-izer(CTLE),a 3-stage high-speed slicer with multi-clock-phase sampling,and a clock and data recovery(CDR).The experimen-tal results show that the TRx operates at a maximum speed of 56 Gb/s with chip-on board(COB)assembly.The 28 Gb/s NRZ eye diagram shows a far-end vertical eye opening of 210 mV with an output amplitude of 351 mV single-ended and the 56 Gb/s PAM-4 eye diagram exhibits far-end eye opening of 33 mV(upper-eye),31 mV(mid-eye),and 28 mV(lower-eye)with an output amplitude of 353 mV single-ended.The recovered 14 GHz clock from the RX exhibits random jitter(RJ)of 469 fs and deterministic jitter(DJ)of 8.76 ps.The 875 Mb/s de-multiplexed data features 593 ps horizontal eye opening with 32.02 ps RJ,at bit-error rate(BER)of 10-5(0.53 UI).The power dissipation of TX and RX are 125 and 181.4 mW,respectively,from a 0.9-V sup-ply.
基金supported by National Natural Science Foundation of China(Nos.61210011and61203010)National Science Fund for Distinguished Youth Scholars of China(No.60425310)+1 种基金Scientific Research Fund of Hunan Provincial Education Department(No.12B044)Hunan Natural Science Foundation(No.11JJ4059)
文摘This paper deals with the problem of designing a robust discrete output-feedback based repetitive-control system for a class of linear plants with periodic uncertainties. The periodicity of the repetitive-control system is exploited to establish a two-dimensional （2D） model that converts the design problem into a robust stabilization problem for a discrete 2D system. By employing Lyapunov stability theory and the singular-value decomposition of the output matrix, a linear-matrix-inequality （LMI） based stability condition is derived. The condition can be used directly to design the gains of the repetitive controller. Two tuning parameters in the LMI enable the preferential adjustment of control and learning. A numerical example illustrates the design procedure and demonstrates the validity of the method.
基金Supported by the National High Technology Research and Development Programme of China （No. 2009AA011501）, National Basic Research Program of China （No. 2007CB310608）, the Fundamental Research Funds for the Central Universities in China, and China Postdoctoral Science Foundation funded project.
文摘A residual carrier frequency offset （CFO） estimation scheme is proposed for the uplink of orthogonal frequency division multiple access （OFDMA） systems. Multiple access interference caused by CFOs in the uplink is investigated, as it severely affects the performance of a classical maximum likelihood （ML） frequency estimator. By the use of the estimated CFOs of the active users, the linear maximum mean square error （LMMSE） equalization is performed before the ML frequency estimator for the interference cancellation, which can help to sufficiently improve the estimation accuracy for the residual CFO of the incoming user. Analysis and simulations show that the modified ML estimator provides a tradeoff between estimation accuracy and computational complexity caused by the LMMSE interference cancellation, and the proposed method allows OFDMA systems flexibly allocating subcarriers to users.
基金Supported by the National Natural Sicence Foundation of China(No.11071117)the Natural Science Foundation of Jiangsu Province(No.BK2006184)the Fundamental Research Funds for the Central Universities(No. 2010LKSX01)
文摘A new method of moving asymptotes for large-scale minimization subject to linear equality constraints is discussed. In this method, linear equality constraints are deleted with null space technique and the descending direction is obtained by solving a convex separable subproblem of moving asymptotes in each iteration. New rules for controlling the asymptotes parameters are designed and the global convergence of the method under some reasonable conditions is established and proved. The numerical results show that the new method may be capable of processing some large scale problems.
基金supported by the National Natural Science Foundation of China under Grant 62222409 and Grant 62174153.
文摘This work presents a PAM4 receiver analog frontend(AFE)operating up to 64 Gb/s.The electronic integrated circuit(EIC)is fabricated in 40-nm CMOS technology.This AFE is composed of a single-stage Continuous-Time Linear Equalizer(CTLE),a Variable Gain Amplifier(VGA),an input impedance matching network,a buffer stage,and an output buffer.The single-stage triple-peaking CTLE proposed employs current reuse technique and a multi-feedback structure,enabling the adjustment of peaking in the low,mid,and high-frequency bands.Thus,only one-stage CTLE is sufficient to achieve an over-20-dB boost at Nyquist frequency to save power.The VGA adopts an enhanced structure based on the Gilbert cell,where the gain is manipulated by controlling the gate voltage of MOS transistors.The CTLE undergoes variations in its DC gain during the adjustment process to equalize channel losses.The role of the VGA is to stable the DC gain changes induced by the adjustment of the CTLE.The output buffer adopts two stages,aiming to ensure that the gain does not attenuate excessively while maintaining output impedance matching.The AFE consumes 21.1 mW with a supply voltage of 1.5/1 V.It can provide a maximum boost of 22.5 dB,and the data rate reaches up to 64 Gb/s.Additionally,it features peaking adjustment capabilities in the low,mid,and high-frequency bands.Finally,the measurement demonstrates its ability to effectively equalize a channel with a 12-dB loss at the Nyquist frequency of 16 GHz.
