针对传统逐次逼近型模/数转换器(Successive Approximation Analog to Digital Converter,SAR ADC)中的电压域比较器存在延迟大、功耗高等问题,本文设计了一款应用于SAR ADC的低功耗时间域比较器。该比较器通过引入高增益的时间放大器(T...针对传统逐次逼近型模/数转换器(Successive Approximation Analog to Digital Converter,SAR ADC)中的电压域比较器存在延迟大、功耗高等问题,本文设计了一款应用于SAR ADC的低功耗时间域比较器。该比较器通过引入高增益的时间放大器(Time Amplifier,TA)成功实现了相位积累速度的指数级增加,有效减小了输入信号相位脱离鉴相器的“死区”所需的振荡周期数,缩短了比较延迟,优化了比较的速度和功耗。该比较器基于65 nm CMOS工艺进行设计,在0.4 V电源电压下功耗仅5.24 nW,失调电压为5.99 mV。展开更多
设计实现一种应用于CMOS图像传感器的10bit模数转换器(ADC),采用基于逐次逼近的新型流水线结构(Pipelined SAR ADC).提出了一种优化选取其中高精度倍增数模转换器(MDAC)和单位电容值的解析方法.通过采用第一级高精度、半增益MDAC和动态...设计实现一种应用于CMOS图像传感器的10bit模数转换器(ADC),采用基于逐次逼近的新型流水线结构(Pipelined SAR ADC).提出了一种优化选取其中高精度倍增数模转换器(MDAC)和单位电容值的解析方法.通过采用第一级高精度、半增益MDAC和动态比较器等技术提高了整体电路的线性度,并降低了系统功耗.通过对版图面积的优化设计,满足了CMOS图像传感器对芯片面积的要求.本设计基于180nm CMOS工艺,仿真结果显示电路实现了60.37dB的信噪失真比(SNDR)和76.37dB的无杂散动态范围(SFDR),有效精度(ENOB)达到了9.74bit.ADC的核心面积仅为140μmⅹ280μm,约为0.04mm2.在2.8V电压下,功耗为9.8mW.展开更多
This paper presents a low power 8-bit 1 MS/s SAR ADC with 7.72-bit ENOB. Without an op-amp, an improved segmented capacitor DAC is proposed to reduce the capacitance and the chip area. A dynamic latch comparator with ...This paper presents a low power 8-bit 1 MS/s SAR ADC with 7.72-bit ENOB. Without an op-amp, an improved segmented capacitor DAC is proposed to reduce the capacitance and the chip area. A dynamic latch comparator with output offset voltage storage technology is used to improve the precision. Adding an extra positive feedback in the latch is to increase the speed. What is more, two pairs of CMOS switches are utilized to eliminate the kickback noise introduced by the latch. The proposed SAR ADC was fabricated in SMIC 0.18μm CMOS technology. The measured results show that this design achieves an SFDR of 61.8 dB and an ENOB of 7.72 bits, and it consumes 67.5μW with the FOM of 312 fJ/conversion-step at 1 MS/s sample under 1.8 V power supply.展开更多
A low power 20 GHz CMOS dynamic latched regeneration comparator for ultra-high-speed, low-power analog-to-digital converters （ADCs） is proposed. The time constant in both the tracking and regeneration phases of the ...A low power 20 GHz CMOS dynamic latched regeneration comparator for ultra-high-speed, low-power analog-to-digital converters （ADCs） is proposed. The time constant in both the tracking and regeneration phases of the latch are analyzed based on the small signal model. A dynamic source-common logic （SCL） topology is adopted in the master-slave latch to increase the tracking and regeneration speeds. Implemented in 90 nm CMOS technology, this comparator only occupies a die area of 65 × 150 μm^2 with a power dissipation of 14 mW from a 1.2 V power supply. The measurement results show that the comparator can work up to 20 GHz. Operating with an input frequency of 1 GHz, the circuit can oversample up to 20 Giga-sampling-per-second （GSps） with 5 bits resolution; while operating at Nyquist, the comparator can sample up to 20 GSps with 4 bits resolution. The comparator has been successfully used in a 20 GSps flash ADC and the circuit can be also used in other high speed applications.展开更多
文摘针对传统逐次逼近型模/数转换器(Successive Approximation Analog to Digital Converter,SAR ADC)中的电压域比较器存在延迟大、功耗高等问题,本文设计了一款应用于SAR ADC的低功耗时间域比较器。该比较器通过引入高增益的时间放大器(Time Amplifier,TA)成功实现了相位积累速度的指数级增加,有效减小了输入信号相位脱离鉴相器的“死区”所需的振荡周期数,缩短了比较延迟,优化了比较的速度和功耗。该比较器基于65 nm CMOS工艺进行设计,在0.4 V电源电压下功耗仅5.24 nW,失调电压为5.99 mV。
文摘设计实现一种应用于CMOS图像传感器的10bit模数转换器(ADC),采用基于逐次逼近的新型流水线结构(Pipelined SAR ADC).提出了一种优化选取其中高精度倍增数模转换器(MDAC)和单位电容值的解析方法.通过采用第一级高精度、半增益MDAC和动态比较器等技术提高了整体电路的线性度,并降低了系统功耗.通过对版图面积的优化设计,满足了CMOS图像传感器对芯片面积的要求.本设计基于180nm CMOS工艺,仿真结果显示电路实现了60.37dB的信噪失真比(SNDR)和76.37dB的无杂散动态范围(SFDR),有效精度(ENOB)达到了9.74bit.ADC的核心面积仅为140μmⅹ280μm,约为0.04mm2.在2.8V电压下,功耗为9.8mW.
基金supported by the National Natural Science Foundation of China(Nos.61161003,61264001,61166004)the Guangxi Key Laboratory of Precision Navigation Technology and Application Foundation(No.DH201501)
文摘This paper presents a low power 8-bit 1 MS/s SAR ADC with 7.72-bit ENOB. Without an op-amp, an improved segmented capacitor DAC is proposed to reduce the capacitance and the chip area. A dynamic latch comparator with output offset voltage storage technology is used to improve the precision. Adding an extra positive feedback in the latch is to increase the speed. What is more, two pairs of CMOS switches are utilized to eliminate the kickback noise introduced by the latch. The proposed SAR ADC was fabricated in SMIC 0.18μm CMOS technology. The measured results show that this design achieves an SFDR of 61.8 dB and an ENOB of 7.72 bits, and it consumes 67.5μW with the FOM of 312 fJ/conversion-step at 1 MS/s sample under 1.8 V power supply.
基金supported by the PhD Programs Foundation of Ministry of Education of China(No.2009009211001)the Important National Science&Technology Specific Projects(No.2010ZX03006-003-02)
文摘A low power 20 GHz CMOS dynamic latched regeneration comparator for ultra-high-speed, low-power analog-to-digital converters （ADCs） is proposed. The time constant in both the tracking and regeneration phases of the latch are analyzed based on the small signal model. A dynamic source-common logic （SCL） topology is adopted in the master-slave latch to increase the tracking and regeneration speeds. Implemented in 90 nm CMOS technology, this comparator only occupies a die area of 65 × 150 μm^2 with a power dissipation of 14 mW from a 1.2 V power supply. The measurement results show that the comparator can work up to 20 GHz. Operating with an input frequency of 1 GHz, the circuit can oversample up to 20 Giga-sampling-per-second （GSps） with 5 bits resolution; while operating at Nyquist, the comparator can sample up to 20 GSps with 4 bits resolution. The comparator has been successfully used in a 20 GSps flash ADC and the circuit can be also used in other high speed applications.
