Utilizing commercial off-the-shelf(COTS) components in satellites has received much attention due to the low cost. However, commercial memories suffer severe reliability problems in radiation environments. This paper ...Utilizing commercial off-the-shelf(COTS) components in satellites has received much attention due to the low cost. However, commercial memories suffer severe reliability problems in radiation environments. This paper studies the low-density parity-check(LDPC) coding scheme for improving the reliability of multi-level-cell(MLC) NAND Flash memory in radiation environments. Firstly, based on existing physical experiment works, we introduce a new error model for heavyion irradiations; secondly, we explore the optimization of writing voltage allocation to maximize the capacity of the storage channel; thirdly, we design the degree distribution of LDPC codes that is specially suitable for the proposed model; finally, we propose a joint detection-decoding scheme based on LDPC codes, which estimates the storage channel state and executes an adaptive log-likelihood ratio(LLR) calculation to achieve better performance. Simulation results show that, compared with the conventional LDPC coding scheme, the proposed scheme may almost double the lifetime of the MLC NAND Flash memory in radiation environments.展开更多
Space laser communication(SLC)is an emerging technology to support high-throughput data transmissions in space networks.In this paper,to guarantee the reliability of high-speed SLC links,we aim at practical implementa...Space laser communication(SLC)is an emerging technology to support high-throughput data transmissions in space networks.In this paper,to guarantee the reliability of high-speed SLC links,we aim at practical implementation of low-density paritycheck(LDPC)decoding under resource-restricted space platforms.Particularly,due to the supply restriction and cost issues of high-speed on-board devices such as analog-to-digital converters(ADCs),the input of LDPC decoding will be usually constrained by hard-decision channel output.To tackle this challenge,density-evolution-based theoretical analysis is firstly performed to identify the cause of performance degradation in the conventional binaryinitialized iterative decoding(BIID)algorithm.Then,a computation-efficient decoding algorithm named multiary-initialized iterative decoding with early termination(MIID-ET)is proposed,which improves the error-correcting performance and computation efficiency by using a reliability-based initialization method and a threshold-based decoding termination rule.Finally,numerical simulations are conducted on example codes of rates 7/8 and 1/2 to evaluate the performance of different LDPC decoding algorithms,where the proposed MIID-ET outperforms the BIID with a coding gain of 0.38 dB and variable node calculation saving of 37%.With this advantage,the proposed MIID-ET can notably reduce LDPC decoder’s hardware implementation complexity under the same bit error rate performance,which successfully doubles the total throughput to 10 Gbps on a single-chip FPGA.展开更多
Quasi-cyclic low-density parity-check （QC-LDPC） codes can be constructed conveniently by cyclic lifting of protographs. For the purpose of eliminating short cycles in the Tanner graph to guarantee performance, first...Quasi-cyclic low-density parity-check （QC-LDPC） codes can be constructed conveniently by cyclic lifting of protographs. For the purpose of eliminating short cycles in the Tanner graph to guarantee performance, first an algorithm to enumerate the harmful short cycles in the protograph is designed, and then a greedy algorithm is proposed to assign proper permutation shifts to the circulant permutation submatrices in the parity check matrix after lifting. Compared with the existing deterministic edge swapping （DES） algorithms, the proposed greedy algorithm adds more constraints in the assignment of permutation shifts to improve performance. Simulation results verify that it outperforms DES in reducing short cycles. In addition, it is proved that the parity check matrices of the cyclic lifted QC-LDPC codes can be transformed into block lower triangular ones when the lifting factor is a power of 2. Utilizing this property, the QC- LDPC codes can be encoded by preprocessing the base matrices, which reduces the encoding complexity to a large extent.展开更多
Abstract： The layered decoding algorithm has been widely used in the implementation of Low Density Parity Check （LDPC） decoders, due to its high convergence speed. However, the pipeline operation of the layered dec...Abstract： The layered decoding algorithm has been widely used in the implementation of Low Density Parity Check （LDPC） decoders, due to its high convergence speed. However, the pipeline operation of the layered decoder may introduce memory access conflicts, which heavily deteriorates the decoder throughput. To essentially deal with the issue of memory access conflicts,展开更多
A new method for the construction of the high performance systematic irregular low-density paritycheck （LDPC） codes based on the sparse generator matrix （G-LDPC） is introduced. The code can greatly reduce the enco...A new method for the construction of the high performance systematic irregular low-density paritycheck （LDPC） codes based on the sparse generator matrix （G-LDPC） is introduced. The code can greatly reduce the encoding complexity while maintaining the same decoding complexity as traditional regular LDPC （H-LDPC） codes defined by the sparse parity check matrix. Simulation results show that the performance of the proposed irregular LDPC codes can offer significant gains over traditional LDPC codes in low SNRs with a few decoding iterations over an additive white Gaussian noise （AWGN） channel.展开更多
Two Relative-Residual-based Dynamic Schedules(RRDS) for Belief Propagation(BP) decoding of Low-Density Parity-Check(LDPC) codes are proposed,in which the Variable code-RRDS(VN-RRDS) is a greediness-reduced version of ...Two Relative-Residual-based Dynamic Schedules(RRDS) for Belief Propagation(BP) decoding of Low-Density Parity-Check(LDPC) codes are proposed,in which the Variable code-RRDS(VN-RRDS) is a greediness-reduced version of the Check code-RRDS(CN-RRDS).The RRDS only processes the variable(or check) node,which has the maximum relative residual among all the variable(or check) nodes in each decoding iteration,thus keeping less greediness and decreased complexity in comparison with the edge-based Variable-to-Check Residual Belief Propagation(VC-RBP) algorithm.Moreover,VN-RRDS propagates first the message which has the largest residual based on all check equations.For different types of LDPC codes,simulation results show that the convergence rate of RRDS is higher than that of VC-RBP while keeping very low computational complexity.Furthermore,VN-RRDS achieves faster convergence as well as better performance than CN-RRDS.展开更多
When implementing helicopter-satellite communications, periodical interruption of the received signal is a challenging problem because the communication antenna is intermittently blocked by the rotating blades of the ...When implementing helicopter-satellite communications, periodical interruption of the received signal is a challenging problem because the communication antenna is intermittently blocked by the rotating blades of the helicopter. The helicopter-satellite channel model and the Forward Error Control（FEC） coding countermeasure are presented in this paper. On the basis of this model, Check-Hybrid（CH） Low-Density Parity-Check（LDPC）codes are designed to mitigate the periodical blockage over the helicopter-satellite channels. The CH-LDPC code is derived by replacing part of single parity-check code constraints in a Quasi-Cyclic LDPC（QC-LDPC） code by using more powerful linear block code constraints. In particular, a method of optimizing the CH-LDPC code ensemble by searching the best matching component code among a variety of linear block codes using extrinsic information transfer charts is proposed. Simulation results show that, the CH-LDPC coding scheme designed for the helicopter-satellite channels in this paper achieves more than 25% bandwidth efficiency improvement, compared with the FEC scheme that uses QC-LDPC codes.展开更多
A novel low-complexity weighted symbol-flipping algorithm with flipping patterns to decode nonbinary low-density parity-check codes is proposed. The proposed decoding procedure updates the hard-decision received symbo...A novel low-complexity weighted symbol-flipping algorithm with flipping patterns to decode nonbinary low-density parity-check codes is proposed. The proposed decoding procedure updates the hard-decision received symbol vector iteratively in search of a valid codeword in the symbol vector space. Only one symbol is flipped in each iteration, and symbol flipping function, which is employed as the symbol flipping metric, combines the number of failed checks and the reliabilities of the received bits and calculated symbols. A scheme to avoid infinite loops and select one symbol to flip in high order Galois field search is also proposed. The design of flipping pattern＇s order and depth, which is dependent of the computational requirement and error performance, is also proposed and exemplified. Simulation results show that the algorithm achieves an appealing tradeoff between performance and computational requirement over relatively low Galois field for short to medium code length.展开更多
Non-uniform quantization for messages in Low-Density Parity-Check(LDPC)decoding canreduce implementation complexity and mitigate performance loss.But the distribution of messagesvaries in the iterative decoding.This l...Non-uniform quantization for messages in Low-Density Parity-Check(LDPC)decoding canreduce implementation complexity and mitigate performance loss.But the distribution of messagesvaries in the iterative decoding.This letter proposes a variable non-uniform quantized Belief Propaga-tion(BP)algorithm.The BP decoding is analyzed by density evolution with Gaussian approximation.Since the probability density of messages can be well approximated by Gaussian distribution,by theunbiased estimation of variance,the distribution of messages can be tracked during the iteration.Thusthe non-uniform quantization scheme can be optimized to minimize the distortion.Simulation resultsshow that the variable non-uniform quantization scheme can achieve better error rate performance andfaster decoding convergence than the conventional non-uniform quantization and uniform quantizationschemes.展开更多
With the development of manufacture technology, the multi-level cell(MLC)technique dramatically increases the storage density of NAND flash memory. As the result,cell-to-cell interference(CCI) becomes more serious and...With the development of manufacture technology, the multi-level cell(MLC)technique dramatically increases the storage density of NAND flash memory. As the result,cell-to-cell interference(CCI) becomes more serious and hence causes an increase in the raw bit error rate of data stored in the cells.Recently, low-density parity-check(LDPC)codes have appeared to be a promising solution to combat the interference of MLC NAND flash memory. However, the decoding complexity of the sum-product algorithm(SPA) is extremely high. In this paper, to improve the accuracy of the log likelihood ratio(LLR) information of each bit in each NAND flash memory cell, we adopt a non-uniform detection(N-UD) which uses the average maximum mutual information to determine the value of the soft-decision reference voltages.Furthermore, with an aim to reduce the decoding complexity and improve the decoding performance, we propose a modified soft reliabilitybased iterative majority-logic decoding(MSRBI-MLGD) algorithm, which uses a non-uniform quantizer based on power function to decode LDPC codes. Simulation results show that our design can offer a desirable trade-off between the performance and complexity for high-column-weight LDPC-coded MLC NAND flash memory.展开更多
This paper presents a simple yet effective decoding for general quasi-cyclic low-density parity-check （QC-LDPC） codes, which not only achieves high hardware utility efficiency （HUE）, but also brings about great me...This paper presents a simple yet effective decoding for general quasi-cyclic low-density parity-check （QC-LDPC） codes, which not only achieves high hardware utility efficiency （HUE）, but also brings about great memory block reduction without any performance degradation. The main idea is to split the check matrix into several row blocks, then to perform the improved mes- sage passing computations sequentially block by block. As the decoding algorithm improves, the sequential tie between the two-phase computations is broken, so that the two-phase computations can be overlapped which bring in high HUE. Two over- lapping schemes are also presented, each of which suits a different situation. In addition, an efficient memory arrangement scheme is proposed to reduce the great memory block requirement of the LDPC decoder. As an example, for the 0.4 rate LDPC code selected from Chinese Digital TV Terrestrial Broadcasting （DTTB）, our decoding saves over 80% memory blocks com- pared with the conventional decoding, and the decoder achieves 0.97 HUE. Finally, the 0.4 rate LDPC decoder is implemented on an FPGA device EP2S30 （speed grade -5）. Using 8 row processing units, the decoder can achieve a maximum net throughput of 28.5 Mbps at 20 iterations.展开更多
In this paper, we present a Joint Source-Channel Decoding algorithm (JSCD) for Low-Density Parity Check (LDPC) codes by modifying the Sum-Product Algorithm (SPA) to account for the source redun-dancy, which results fr...In this paper, we present a Joint Source-Channel Decoding algorithm (JSCD) for Low-Density Parity Check (LDPC) codes by modifying the Sum-Product Algorithm (SPA) to account for the source redun-dancy, which results from the neighbouring Huffman coded bits. Simulations demonstrate that in the presence of source redundancy, the proposed algorithm gives better performance than the Separate Source and Channel Decoding algorithm (SSCD).展开更多
A network-coding-based multisource LDPC-coded cooperative MIMO scheme is proposed,where multiple sources transmit their messages to the destination with the assistance from a single relay.The relay cooperates with mul...A network-coding-based multisource LDPC-coded cooperative MIMO scheme is proposed,where multiple sources transmit their messages to the destination with the assistance from a single relay.The relay cooperates with multiple sources simultaneously via network-coding.It avoids the issues of imperfect frequency/timing synchronization and large transmission delay which may be introduced by frequency-division multiple access(FDMA)/code-division multiple access(CDMA)and time-division multiple access(TDMA)manners.The proposed joint″Min-Sum″iterative decoding is effectively carried out in the destination.Such a decoding algorithm agrees with the introduced equivalent joint Tanner graph which can be used to fully characterize LDPC codes employed by the sources and relay.Theoretical analysis and numerical simulation show that the proposed scheme with joint iterative decoding can achieve significant cooperation diversity gain.Furthermore,for the relay,compared with the cascade scheme,the proposed scheme has much lower complexity of LDPC-encoding and is easier to be implemented in the hardware with similar bit error rate(BER)performance.展开更多
Low-Density Parity-Check (LDPC) code is one of the most exciting topics among the coding theory community.It is of great importance in both theory and practical communications over noisy channels.The most advantage of...Low-Density Parity-Check (LDPC) code is one of the most exciting topics among the coding theory community.It is of great importance in both theory and practical communications over noisy channels.The most advantage of LDPC codes is their relatively lower decoding complexity compared with turbo codes,while the disadvantage is its higher encoding complexity.In this paper,a new ap- proach is first proposed to construct high performance irregular systematic LDPC codes based on sparse generator matrix,which can significantly reduce the encoding complexity under the same de- coding complexity as that of regular or irregular LDPC codes defined by traditional sparse parity-check matrix.Then,the proposed generator-based systematic irregular LDPC codes are adopted as con- stituent block codes in rows and columns to design a new kind of product codes family,which also can be interpreted as irregular LDPC codes characterized by graph and thus decoded iteratively.Finally, the performance of the generator-based LDPC codes and the resultant product codes is investigated over an Additive White Gaussian Noise (AWGN) and also compared with the conventional LDPC codes under the same conditions of decoding complexity and channel noise.展开更多
Considering that the hardware implementation of the normalized minimum sum(NMS)decoding algorithm for low-density parity-check(LDPC)code is difficult due to the uncertainty of scale factor,an NMS decoding algorithm wi...Considering that the hardware implementation of the normalized minimum sum(NMS)decoding algorithm for low-density parity-check(LDPC)code is difficult due to the uncertainty of scale factor,an NMS decoding algorithm with variable scale factor is proposed for the near-earth space LDPC codes(8177,7154)in the consultative committee for space data systems(CCSDS)standard.The shift characteristics of field programmable gate array(FPGA)is used to optimize the quantization data of check nodes,and finally the function of LDPC decoder is realized.The simulation and experimental results show that the designed FPGA-based LDPC decoder adopts the scaling factor in the NMS decoding algorithm to improve the decoding performance,simplify the hardware structure,accelerate the convergence speed and improve the error correction ability.展开更多
Avalanche photodiodes （APD） are widely employed in visible light communication （VLC） systems. The general signal dependent Gaussian channel is investigated. Experiment results reveal that symbols on different cons...Avalanche photodiodes （APD） are widely employed in visible light communication （VLC） systems. The general signal dependent Gaussian channel is investigated. Experiment results reveal that symbols on different constellation points under official illuminance inevitably suffer from different levels of noise due to the multiplication process of APDs. In such a case, conventional log likely-hood ratio （LLR） calculation for signal independent channels may cause performance loss. The optimal LLR calculation for decoder is then derived because of the existence of non-ignorable APD shot noise. To find the decoding thresholds of the optimal and suboptimal detection schemes, the extrinsic information transfer （EXIT） chat is further analyzed. Finally a modified minimum sum algorithm is suggested with reduced complexity and acceptable performance loss. Numerical simulations show that, with a reg- ular （3, 6） low-density parity check （LDPC） code of block length 20,000, 0.7 dB gain is achieved with our proposed scheme over the LDPC decoder designed for signal independent noise. It is also found that the coding performance is improved for a larger modulation depth.展开更多
For one class of Low-Density Parity-Check(LDPC)codes with low row weight in theirparity check matrix,a new Syndrome Decoding(SD)based on the heuristic Beam Search(BS),labeledas SD-BS,is put forward to improve the erro...For one class of Low-Density Parity-Check(LDPC)codes with low row weight in theirparity check matrix,a new Syndrome Decoding(SD)based on the heuristic Beam Search(BS),labeledas SD-BS,is put forward to improve the error performance.First,two observations are made andverified by simulation results.One is that in the SNR region of interest,the hard-decision on thecorrupted sequence yields only a handful of erroneous bits.The other is that the true error pattern forthe nonzero syndrome has a high probability to survive the competition in the BS,provided sufficientbeam width.Bearing these two points in mind,the decoding of LDPC codes is transformed into seekingan error pattern with the known decoding syndrome.Secondly,the effectiveness of SD-BS dependsclosely on how to evaluate the bit reliability.Enlightened by a bit-flipping definition in the existingliterature,a new metric is employed in the proposed SD-BS.The strength of SD-BS is demonstrated viaapplying it on the corrupted sequences directly and the decoding failures of the Belief Propagation(BP),respectively.展开更多
A hybrid decoding algorithm is proposed for nonbinary low-density parity-check （LDPC） codes, which combines the weighted symbol-flipping （WSF） algorithm with the fast Fourier trans- form q-ary sum-product algorit...A hybrid decoding algorithm is proposed for nonbinary low-density parity-check （LDPC） codes, which combines the weighted symbol-flipping （WSF） algorithm with the fast Fourier trans- form q-ary sum-product algorithm （FFT-QSPA）. The flipped position and value are determined by the symbol flipping metric and the received bit values in the first stage WSF algorithm. If the low- eomplexity WSF algorithm is failed, the second stage FFT-QSPA is activated as a switching strategy. Simulation results show that the proposed hybrid algorithm greatly reduces the computational complexity with the performance close to that of FFT-QSPA.展开更多
In this paper, A Belief Propagation concatenated Orderd-Statistic Decoder (BP-OSD) based on accumulated Log-Likelihood Ratio (LLR) is proposed for medium and short lengths Low Density Parity-Check (LDPC) codes coded B...In this paper, A Belief Propagation concatenated Orderd-Statistic Decoder (BP-OSD) based on accumulated Log-Likelihood Ratio (LLR) is proposed for medium and short lengths Low Density Parity-Check (LDPC) codes coded Bit-Interleaved Coded Modulation (BICM) systems. The accumulated soft output values delivered by every BP iteration are used as reliability values of Soft-Input Soft-Output OSD (SISO-OSD) decoder and the soft output of SISO-OSD is used as a priori probabilities of the demodulator for the next iteration. Simulation results show that this improved algorithm achieves noticeable performance gain with only modest increase in computation complexity.展开更多
As an effective error correction technology,the Low Density Parity Check Code(LDPC)has been researched and applied by many scholars.Meanwhile,LDPC codes have some prominent performances,which involves close to the Sha...As an effective error correction technology,the Low Density Parity Check Code(LDPC)has been researched and applied by many scholars.Meanwhile,LDPC codes have some prominent performances,which involves close to the Shannon limit,achieving a higher bit rate and a fast decoding.However,whether these excellent characteristics are suitable for the resource-constrained Wireless Sensor Network(WSN),it seems to be seldom concerned.In this article,we review the LDPC code’s structure brief.ly,and them classify and summarize the LDPC codes’construction and decoding algorithms,finally,analyze the applications of LDPC code for WSN.We believe that our contributions will be able to facilitate the application of LDPC code in WSN.展开更多
基金supported by the National Basic Research Project of China(973)(2013CB329006)National Natural Science Foundation of China(NSFC,91538203)the new strategic industries development projects of Shenzhen City(JCYJ20150403155812833)
文摘Utilizing commercial off-the-shelf(COTS) components in satellites has received much attention due to the low cost. However, commercial memories suffer severe reliability problems in radiation environments. This paper studies the low-density parity-check(LDPC) coding scheme for improving the reliability of multi-level-cell(MLC) NAND Flash memory in radiation environments. Firstly, based on existing physical experiment works, we introduce a new error model for heavyion irradiations; secondly, we explore the optimization of writing voltage allocation to maximize the capacity of the storage channel; thirdly, we design the degree distribution of LDPC codes that is specially suitable for the proposed model; finally, we propose a joint detection-decoding scheme based on LDPC codes, which estimates the storage channel state and executes an adaptive log-likelihood ratio(LLR) calculation to achieve better performance. Simulation results show that, compared with the conventional LDPC coding scheme, the proposed scheme may almost double the lifetime of the MLC NAND Flash memory in radiation environments.
基金supported by the National Key R&D Program of China(Grant No.2022YFA1005000)the National Natural Science Foundation of China(Grant No.62101308 and 62025110).
文摘Space laser communication(SLC)is an emerging technology to support high-throughput data transmissions in space networks.In this paper,to guarantee the reliability of high-speed SLC links,we aim at practical implementation of low-density paritycheck(LDPC)decoding under resource-restricted space platforms.Particularly,due to the supply restriction and cost issues of high-speed on-board devices such as analog-to-digital converters(ADCs),the input of LDPC decoding will be usually constrained by hard-decision channel output.To tackle this challenge,density-evolution-based theoretical analysis is firstly performed to identify the cause of performance degradation in the conventional binaryinitialized iterative decoding(BIID)algorithm.Then,a computation-efficient decoding algorithm named multiary-initialized iterative decoding with early termination(MIID-ET)is proposed,which improves the error-correcting performance and computation efficiency by using a reliability-based initialization method and a threshold-based decoding termination rule.Finally,numerical simulations are conducted on example codes of rates 7/8 and 1/2 to evaluate the performance of different LDPC decoding algorithms,where the proposed MIID-ET outperforms the BIID with a coding gain of 0.38 dB and variable node calculation saving of 37%.With this advantage,the proposed MIID-ET can notably reduce LDPC decoder’s hardware implementation complexity under the same bit error rate performance,which successfully doubles the total throughput to 10 Gbps on a single-chip FPGA.
基金The National Key Technology R&D Program of China during the 12th Five-Year Plan Period(No.2012BAH15B00)
文摘Quasi-cyclic low-density parity-check （QC-LDPC） codes can be constructed conveniently by cyclic lifting of protographs. For the purpose of eliminating short cycles in the Tanner graph to guarantee performance, first an algorithm to enumerate the harmful short cycles in the protograph is designed, and then a greedy algorithm is proposed to assign proper permutation shifts to the circulant permutation submatrices in the parity check matrix after lifting. Compared with the existing deterministic edge swapping （DES） algorithms, the proposed greedy algorithm adds more constraints in the assignment of permutation shifts to improve performance. Simulation results verify that it outperforms DES in reducing short cycles. In addition, it is proved that the parity check matrices of the cyclic lifted QC-LDPC codes can be transformed into block lower triangular ones when the lifting factor is a power of 2. Utilizing this property, the QC- LDPC codes can be encoded by preprocessing the base matrices, which reduces the encoding complexity to a large extent.
基金the National Natural Science Foundation of China，the National Key Basic Research Program of China，The authors would like to thank all project partners for their valuable contributions and feedbacks
文摘Abstract： The layered decoding algorithm has been widely used in the implementation of Low Density Parity Check （LDPC） decoders, due to its high convergence speed. However, the pipeline operation of the layered decoder may introduce memory access conflicts, which heavily deteriorates the decoder throughput. To essentially deal with the issue of memory access conflicts,
文摘A new method for the construction of the high performance systematic irregular low-density paritycheck （LDPC） codes based on the sparse generator matrix （G-LDPC） is introduced. The code can greatly reduce the encoding complexity while maintaining the same decoding complexity as traditional regular LDPC （H-LDPC） codes defined by the sparse parity check matrix. Simulation results show that the performance of the proposed irregular LDPC codes can offer significant gains over traditional LDPC codes in low SNRs with a few decoding iterations over an additive white Gaussian noise （AWGN） channel.
基金supported by the Fundamental Research Funds for the Central Universities
文摘Two Relative-Residual-based Dynamic Schedules(RRDS) for Belief Propagation(BP) decoding of Low-Density Parity-Check(LDPC) codes are proposed,in which the Variable code-RRDS(VN-RRDS) is a greediness-reduced version of the Check code-RRDS(CN-RRDS).The RRDS only processes the variable(or check) node,which has the maximum relative residual among all the variable(or check) nodes in each decoding iteration,thus keeping less greediness and decreased complexity in comparison with the edge-based Variable-to-Check Residual Belief Propagation(VC-RBP) algorithm.Moreover,VN-RRDS propagates first the message which has the largest residual based on all check equations.For different types of LDPC codes,simulation results show that the convergence rate of RRDS is higher than that of VC-RBP while keeping very low computational complexity.Furthermore,VN-RRDS achieves faster convergence as well as better performance than CN-RRDS.
基金supported by the National Natural Science Foundation of China(No.91538203)the new strategic industries development projects of Shenzhen City(No.JCYJ20150403155812833)
文摘When implementing helicopter-satellite communications, periodical interruption of the received signal is a challenging problem because the communication antenna is intermittently blocked by the rotating blades of the helicopter. The helicopter-satellite channel model and the Forward Error Control（FEC） coding countermeasure are presented in this paper. On the basis of this model, Check-Hybrid（CH） Low-Density Parity-Check（LDPC）codes are designed to mitigate the periodical blockage over the helicopter-satellite channels. The CH-LDPC code is derived by replacing part of single parity-check code constraints in a Quasi-Cyclic LDPC（QC-LDPC） code by using more powerful linear block code constraints. In particular, a method of optimizing the CH-LDPC code ensemble by searching the best matching component code among a variety of linear block codes using extrinsic information transfer charts is proposed. Simulation results show that, the CH-LDPC coding scheme designed for the helicopter-satellite channels in this paper achieves more than 25% bandwidth efficiency improvement, compared with the FEC scheme that uses QC-LDPC codes.
文摘A novel low-complexity weighted symbol-flipping algorithm with flipping patterns to decode nonbinary low-density parity-check codes is proposed. The proposed decoding procedure updates the hard-decision received symbol vector iteratively in search of a valid codeword in the symbol vector space. Only one symbol is flipped in each iteration, and symbol flipping function, which is employed as the symbol flipping metric, combines the number of failed checks and the reliabilities of the received bits and calculated symbols. A scheme to avoid infinite loops and select one symbol to flip in high order Galois field search is also proposed. The design of flipping pattern＇s order and depth, which is dependent of the computational requirement and error performance, is also proposed and exemplified. Simulation results show that the algorithm achieves an appealing tradeoff between performance and computational requirement over relatively low Galois field for short to medium code length.
基金the Aerospace Technology Support Foun-dation of China(No.J04-2005040).
文摘Non-uniform quantization for messages in Low-Density Parity-Check(LDPC)decoding canreduce implementation complexity and mitigate performance loss.But the distribution of messagesvaries in the iterative decoding.This letter proposes a variable non-uniform quantized Belief Propaga-tion(BP)algorithm.The BP decoding is analyzed by density evolution with Gaussian approximation.Since the probability density of messages can be well approximated by Gaussian distribution,by theunbiased estimation of variance,the distribution of messages can be tracked during the iteration.Thusthe non-uniform quantization scheme can be optimized to minimize the distortion.Simulation resultsshow that the variable non-uniform quantization scheme can achieve better error rate performance andfaster decoding convergence than the conventional non-uniform quantization and uniform quantizationschemes.
基金supported in part by the NSF of China (61471131, 61771149, 61501126)NSF of Guangdong Province 2016A030310337+1 种基金the open research fund of National Mobile Communications Research Laboratory, Southeast University (No. 2018D02)the Guangdong Province Universities and Colleges Pearl River Scholar Funded Scheme (2017-ZJ022)
文摘With the development of manufacture technology, the multi-level cell(MLC)technique dramatically increases the storage density of NAND flash memory. As the result,cell-to-cell interference(CCI) becomes more serious and hence causes an increase in the raw bit error rate of data stored in the cells.Recently, low-density parity-check(LDPC)codes have appeared to be a promising solution to combat the interference of MLC NAND flash memory. However, the decoding complexity of the sum-product algorithm(SPA) is extremely high. In this paper, to improve the accuracy of the log likelihood ratio(LLR) information of each bit in each NAND flash memory cell, we adopt a non-uniform detection(N-UD) which uses the average maximum mutual information to determine the value of the soft-decision reference voltages.Furthermore, with an aim to reduce the decoding complexity and improve the decoding performance, we propose a modified soft reliabilitybased iterative majority-logic decoding(MSRBI-MLGD) algorithm, which uses a non-uniform quantizer based on power function to decode LDPC codes. Simulation results show that our design can offer a desirable trade-off between the performance and complexity for high-column-weight LDPC-coded MLC NAND flash memory.
基金Science and Technology on Avionics Integration Laboratory and Aeronautical Science Foundation of China (20115551022)
文摘This paper presents a simple yet effective decoding for general quasi-cyclic low-density parity-check （QC-LDPC） codes, which not only achieves high hardware utility efficiency （HUE）, but also brings about great memory block reduction without any performance degradation. The main idea is to split the check matrix into several row blocks, then to perform the improved mes- sage passing computations sequentially block by block. As the decoding algorithm improves, the sequential tie between the two-phase computations is broken, so that the two-phase computations can be overlapped which bring in high HUE. Two over- lapping schemes are also presented, each of which suits a different situation. In addition, an efficient memory arrangement scheme is proposed to reduce the great memory block requirement of the LDPC decoder. As an example, for the 0.4 rate LDPC code selected from Chinese Digital TV Terrestrial Broadcasting （DTTB）, our decoding saves over 80% memory blocks com- pared with the conventional decoding, and the decoder achieves 0.97 HUE. Finally, the 0.4 rate LDPC decoder is implemented on an FPGA device EP2S30 （speed grade -5）. Using 8 row processing units, the decoder can achieve a maximum net throughput of 28.5 Mbps at 20 iterations.
文摘In this paper, we present a Joint Source-Channel Decoding algorithm (JSCD) for Low-Density Parity Check (LDPC) codes by modifying the Sum-Product Algorithm (SPA) to account for the source redun-dancy, which results from the neighbouring Huffman coded bits. Simulations demonstrate that in the presence of source redundancy, the proposed algorithm gives better performance than the Separate Source and Channel Decoding algorithm (SSCD).
基金Supported by the Postdoctoral Science Foundation of China(2014M561694)the Science and Technology on Avionics Integration Laboratory and National Aeronautical Science Foundation of China(20105552)
文摘A network-coding-based multisource LDPC-coded cooperative MIMO scheme is proposed,where multiple sources transmit their messages to the destination with the assistance from a single relay.The relay cooperates with multiple sources simultaneously via network-coding.It avoids the issues of imperfect frequency/timing synchronization and large transmission delay which may be introduced by frequency-division multiple access(FDMA)/code-division multiple access(CDMA)and time-division multiple access(TDMA)manners.The proposed joint″Min-Sum″iterative decoding is effectively carried out in the destination.Such a decoding algorithm agrees with the introduced equivalent joint Tanner graph which can be used to fully characterize LDPC codes employed by the sources and relay.Theoretical analysis and numerical simulation show that the proposed scheme with joint iterative decoding can achieve significant cooperation diversity gain.Furthermore,for the relay,compared with the cascade scheme,the proposed scheme has much lower complexity of LDPC-encoding and is easier to be implemented in the hardware with similar bit error rate(BER)performance.
基金Supported by the National Aeronautical Foundation of Science and Research of China (No.04F52041)the Natural Science Foundation of Jiangsu Province (No.BK2006188).
文摘Low-Density Parity-Check (LDPC) code is one of the most exciting topics among the coding theory community.It is of great importance in both theory and practical communications over noisy channels.The most advantage of LDPC codes is their relatively lower decoding complexity compared with turbo codes,while the disadvantage is its higher encoding complexity.In this paper,a new ap- proach is first proposed to construct high performance irregular systematic LDPC codes based on sparse generator matrix,which can significantly reduce the encoding complexity under the same de- coding complexity as that of regular or irregular LDPC codes defined by traditional sparse parity-check matrix.Then,the proposed generator-based systematic irregular LDPC codes are adopted as con- stituent block codes in rows and columns to design a new kind of product codes family,which also can be interpreted as irregular LDPC codes characterized by graph and thus decoded iteratively.Finally, the performance of the generator-based LDPC codes and the resultant product codes is investigated over an Additive White Gaussian Noise (AWGN) and also compared with the conventional LDPC codes under the same conditions of decoding complexity and channel noise.
文摘Considering that the hardware implementation of the normalized minimum sum(NMS)decoding algorithm for low-density parity-check(LDPC)code is difficult due to the uncertainty of scale factor,an NMS decoding algorithm with variable scale factor is proposed for the near-earth space LDPC codes(8177,7154)in the consultative committee for space data systems(CCSDS)standard.The shift characteristics of field programmable gate array(FPGA)is used to optimize the quantization data of check nodes,and finally the function of LDPC decoder is realized.The simulation and experimental results show that the designed FPGA-based LDPC decoder adopts the scaling factor in the NMS decoding algorithm to improve the decoding performance,simplify the hardware structure,accelerate the convergence speed and improve the error correction ability.
基金supported by"973"project(No.2013CB329204)the National Natural Science Foundation of China(No.61223001,No.61461136003,and No.61571118)
文摘Avalanche photodiodes （APD） are widely employed in visible light communication （VLC） systems. The general signal dependent Gaussian channel is investigated. Experiment results reveal that symbols on different constellation points under official illuminance inevitably suffer from different levels of noise due to the multiplication process of APDs. In such a case, conventional log likely-hood ratio （LLR） calculation for signal independent channels may cause performance loss. The optimal LLR calculation for decoder is then derived because of the existence of non-ignorable APD shot noise. To find the decoding thresholds of the optimal and suboptimal detection schemes, the extrinsic information transfer （EXIT） chat is further analyzed. Finally a modified minimum sum algorithm is suggested with reduced complexity and acceptable performance loss. Numerical simulations show that, with a reg- ular （3, 6） low-density parity check （LDPC） code of block length 20,000, 0.7 dB gain is achieved with our proposed scheme over the LDPC decoder designed for signal independent noise. It is also found that the coding performance is improved for a larger modulation depth.
基金the National Science Foundation of China(No.60472104).
文摘For one class of Low-Density Parity-Check(LDPC)codes with low row weight in theirparity check matrix,a new Syndrome Decoding(SD)based on the heuristic Beam Search(BS),labeledas SD-BS,is put forward to improve the error performance.First,two observations are made andverified by simulation results.One is that in the SNR region of interest,the hard-decision on thecorrupted sequence yields only a handful of erroneous bits.The other is that the true error pattern forthe nonzero syndrome has a high probability to survive the competition in the BS,provided sufficientbeam width.Bearing these two points in mind,the decoding of LDPC codes is transformed into seekingan error pattern with the known decoding syndrome.Secondly,the effectiveness of SD-BS dependsclosely on how to evaluate the bit reliability.Enlightened by a bit-flipping definition in the existingliterature,a new metric is employed in the proposed SD-BS.The strength of SD-BS is demonstrated viaapplying it on the corrupted sequences directly and the decoding failures of the Belief Propagation(BP),respectively.
基金Supported by the National High Technology Research and Development Programme of China(No.2009AAJ128,2009AAJ208,2010AA7010422)
文摘A hybrid decoding algorithm is proposed for nonbinary low-density parity-check （LDPC） codes, which combines the weighted symbol-flipping （WSF） algorithm with the fast Fourier trans- form q-ary sum-product algorithm （FFT-QSPA）. The flipped position and value are determined by the symbol flipping metric and the received bit values in the first stage WSF algorithm. If the low- eomplexity WSF algorithm is failed, the second stage FFT-QSPA is activated as a switching strategy. Simulation results show that the proposed hybrid algorithm greatly reduces the computational complexity with the performance close to that of FFT-QSPA.
基金Supported by the National Natural Science Foundation of China (No: 60496311)
文摘In this paper, A Belief Propagation concatenated Orderd-Statistic Decoder (BP-OSD) based on accumulated Log-Likelihood Ratio (LLR) is proposed for medium and short lengths Low Density Parity-Check (LDPC) codes coded Bit-Interleaved Coded Modulation (BICM) systems. The accumulated soft output values delivered by every BP iteration are used as reliability values of Soft-Input Soft-Output OSD (SISO-OSD) decoder and the soft output of SISO-OSD is used as a priori probabilities of the demodulator for the next iteration. Simulation results show that this improved algorithm achieves noticeable performance gain with only modest increase in computation complexity.
基金This work is partially supported by the National Natural Science Foundation of China(No.61571004)the Shanghai Natural Science Foundation(No.17ZR1429100)+2 种基金the Science and Technology Innovation Program of Shanghai(No.115DZ1100400)Fujian Science and Technology Plan STS Program(2017T3009)the Scientific Instrument Developing Project of the Chinese Academy of Sciences(No.YJKYYQ20170074).
文摘As an effective error correction technology,the Low Density Parity Check Code(LDPC)has been researched and applied by many scholars.Meanwhile,LDPC codes have some prominent performances,which involves close to the Shannon limit,achieving a higher bit rate and a fast decoding.However,whether these excellent characteristics are suitable for the resource-constrained Wireless Sensor Network(WSN),it seems to be seldom concerned.In this article,we review the LDPC code’s structure brief.ly,and them classify and summarize the LDPC codes’construction and decoding algorithms,finally,analyze the applications of LDPC code for WSN.We believe that our contributions will be able to facilitate the application of LDPC code in WSN.
