To solve the issue of downloading speed and application scenarios limitation of current JTAGLink debugger, this paper presents a new scheme of ARM debugger with the feature of Ethemet interface implemented by pure har...To solve the issue of downloading speed and application scenarios limitation of current JTAGLink debugger, this paper presents a new scheme of ARM debugger with the feature of Ethemet interface implemented by pure hardware logic design. This paper outlines the principle of the scheme, blocks of logic design, and protocols design. The scheme provides higher downloading speed, wider flexibility on application, and improves work efficiency evidently. Key words： JTAGLink Debugger; Ethernet; FPGA; Logic Design展开更多
文摘To solve the issue of downloading speed and application scenarios limitation of current JTAGLink debugger, this paper presents a new scheme of ARM debugger with the feature of Ethemet interface implemented by pure hardware logic design. This paper outlines the principle of the scheme, blocks of logic design, and protocols design. The scheme provides higher downloading speed, wider flexibility on application, and improves work efficiency evidently. Key words： JTAGLink Debugger; Ethernet; FPGA; Logic Design
