This Special Topic of the Journal of Semiconductors(JOS)features expanded versions of key articles presented at the 2024 IEEE International Conference on Integrated Circuits Technologies and Applications(ICTA),which w...This Special Topic of the Journal of Semiconductors(JOS)features expanded versions of key articles presented at the 2024 IEEE International Conference on Integrated Circuits Technologies and Applications(ICTA),which was held in Hangzhou,Zhejiang,China,from October 25 to 27,2024.展开更多
The relentless down-scaling of electronics grands the modern integrated circuits(ICs)with the high speed,low power dissipation and low cost,fulfilling diverse demands of modern life.Whereas,with the semiconductor indu...The relentless down-scaling of electronics grands the modern integrated circuits(ICs)with the high speed,low power dissipation and low cost,fulfilling diverse demands of modern life.Whereas,with the semiconductor industry entering into sub-10 nm technology nodes,degrading device performance and increasing power consumption give rise to insurmountable roadblocks confronted by modern ICs that need to be conquered to sustain the Moore law's life.Bulk semiconductors like prevalent Si are plagued by seriously degraded carrier mobility as thickness thinning down to sub-5 nm,which is imperative to maintain sufficient gate electrostatic controllability to combat the increasingly degraded short channel effects.Nowadays,the emergence of two-dimensional(2D)materials opens up new gateway to eschew the hurdles laid in front of the scaling trend of modern IC,mainly ascribed to their ultimately atomic thickness,capability to maintain carrier mobility with thickness thinning down,dangling-bonds free surface,wide bandgaps tunability and feasibility to constitute diverse heterostructures.Blossoming breakthroughs in discrete electronic device,such as contact engineering,dielectric integration and vigorous channel-length scaling,or large circuits arrays,as boosted yields,improved variations and full-functioned processor fabrication,based on 2D materials have been achieved nowadays,facilitating 2D materials to step under the spotlight of IC industry to be treated as the most potential future successor or complementary counterpart of incumbent Si to further sustain the down-scaling of modern IC.展开更多
Vocational undergraduate education has entered a new stage of high-quality development,making the cultivation of students'learning ability a core issue in enhancing talent cultivation quality.This study conducted ...Vocational undergraduate education has entered a new stage of high-quality development,making the cultivation of students'learning ability a core issue in enhancing talent cultivation quality.This study conducted a questionnaire survey with 177 students majoring in integrated circuits at Shenzhen Polytechnic University(SZPU),focusing on six dimensions:self-learning proficiency,academic competence,goal planning,self-discipline,learning initiative,and learning environment.The results indicate that while students possess a solid learning foundation and clear career planning,significant deficiencies exist in the execution of academic plans,self-discipline,and learning initiative.In response to these issues,this study proposes four systematic improvement pathways from the institutional perspective:establishing a closed-loop academic navigation system incorporating“goal-process-feedback”,creating an immersive“virtual-physical integrated”learning environment,implementing a multi-dimensional“cognitive-affective-practical”initiative activation plan,and building a synergistic cultivation mechanism for“self-discipline and core competencies”.The findings aim to provide references for talent cultivation and teaching reform in vocational undergraduate integrated circuit programs.展开更多
The single-molecule detection tech-nique plays a pivotal role in elucidat-ing the fundamental mechanisms of various scientific processes at the molecular level,and holds essential im-portance in multiple fields includ...The single-molecule detection tech-nique plays a pivotal role in elucidat-ing the fundamental mechanisms of various scientific processes at the molecular level,and holds essential im-portance in multiple fields including physics,biology,and chemistry.Re-cently,single-molecule detection has garnered increasing attention owing to its practical utility in medical diagno-sis,primarily due to its exceptional sensitivity and the minimal sample volume required for analysis.However,the conventional single-molecule technique,represented by total internal reflection microscopy,faces challenges such as sophisticated operation procedures and limited detection throughput,thereby impeding its broader application.To address these limitations,we have demonstrated single-molecule detection using an integrated silicon photonic chip,of-fering a cost-effective and user-friendly alternative.By employing basic optics,we efficiently introduce the excitation source for single-molecule fluorescence by harnessing the strong evanescent field of high refractive-index waveguides.Subsequently,fluorescence signals are collected using basic optics comprising a water-immersion objective,relay optics,and a digi-tal camera.Our results highlight a low-cost,high-throughput single-molecule technique achieved through the integrated silicon photonic chip.This innovative approach is promised to facilitate the widespread adoption of single-molecule fluorescence in medical diagnosis.展开更多
Multi-level programmable photonic integrated circuits(PICs)and optical metasurfaces have gained widespread attention in many fields,such as neuromorphic photonics,opticalcommunications,and quantum information.In this ...Multi-level programmable photonic integrated circuits(PICs)and optical metasurfaces have gained widespread attention in many fields,such as neuromorphic photonics,opticalcommunications,and quantum information.In this paper,we propose pixelated programmable Si_(3)N_(4)PICs with record-high 20-level intermediate states at 785 nm wavelength.Such flexibility in phase or amplitude modulation is achieved by a programmable Sb_(2)S_(3)matrix,the footprint of whose elements can be as small as 1.2μm,limited only by the optical diffraction limit of anin-house developed pulsed laser writing system.We believe our work lays the foundation for laser-writing ultra-high-level(20 levels and even more)programmable photonic systems and metasurfaces based on phase change materials,which could catalyze diverse applications such as programmable neuromorphic photonics,biosensing,optical computing,photonic quantum computing,and reconfigurable metasurfaces.展开更多
This article addresses the past,present,and future status of hybrid plasmonic waveguides(HPWs).It presents a comprehensive review of HPW-based photonic integrated circuits(PICs),covering both passive and active device...This article addresses the past,present,and future status of hybrid plasmonic waveguides(HPWs).It presents a comprehensive review of HPW-based photonic integrated circuits(PICs),covering both passive and active devices,as well as potential application of on-chip HPWbased devices.HPW-based integrated circuits(HPWICs)are compatible with complementary metal oxide semiconductor technology,and their matched refractive indices enables the adaptation of existing fabrication processes for silicon-on-insulator designs.HPWs combine plasmonic and photonic waveguide components to provide strong confinement with longer propagation length L_(p)of HP modes with nominal losses.These HPWs are able to make a trade-off between low loss and longer L_(p),which is not possible with independent plasmonic and photonic waveguide components owing to their inability to simultaneously achieve low propagation loss with rapid and effective all-optical functionality.With HPWs,it is possible to overcome challenges such as high Ohmic losses and enhance the functional performance of PICs through the use of multiple discrete components.HPWs have been employed not only to guide transverse magnetic modes but also for optical beam manipulation,wireless optical communication,filtering,computation,sensing of bending,optical signal emission,and splitting.They also have the potential to play a pivotal role in optical communication systems for quantum computing and within data centers.At present,HPW-based PICs are poised to transform wireless chip-to-chip communication,a number of areas of biomedical science,machine learning,and artificial intelligence,as well as enabling the creation of densely integrated circuits and highly compact photonic devices.展开更多
Based on the physical characteristics of SiGe material,a new three-dimensional （3D） CMOS IC structure is proposed,in which the first device layer is made of Si material for nMOS devices and the second device layer i...Based on the physical characteristics of SiGe material,a new three-dimensional （3D） CMOS IC structure is proposed,in which the first device layer is made of Si material for nMOS devices and the second device layer is made of Six Ge1- x material for pMOS. The intrinsic performance of ICs with the new structure is then limited by Si nMOS.The electrical characteristics of a Si-SiGe 3D CMOS device and inverter are all simulated and analyzed by MEDICI. The simulation results indicate that the Si-SiGe 3D CMOS ICs are faster than the Si-Si 3D CMOS ICs. The delay time of the 3D Si-SiGe CMOS inverter is 2-3ps,which is shorter than that of the 3D Si-Si CMOS inverter.展开更多
Through-silicon-via （TSV） to TSV crosstalk noise is one of the key factors affecting the signal integrity of three- dimensional integrated circuits （3D ICs）. Based on the frequency dependent equivalent electrical ...Through-silicon-via （TSV） to TSV crosstalk noise is one of the key factors affecting the signal integrity of three- dimensional integrated circuits （3D ICs）. Based on the frequency dependent equivalent electrical parameters for the TSV channel, an analytical crosstalk noise model is established to capture the TSV induced crosstalk noise. The impact of various design parameters including insulation dielectric, via pitch, via height, silicon conductivity, and terminal impedance on the crosstalk noise is analyzed with the proposed model. Two approaches are proposed to alleviate the TSV noise, namely, driver sizing and via shielding, and the SPICE results show 241 rnV and 379 mV reductions in the peak noise voltage, respectively.展开更多
As an outstanding representative of layered materials,molybdenum disulfide(MoS_(2))has excellent physical properties,such as high carrier mobility,stability,and abundance on earth.Moreover,its reasonable band gap and ...As an outstanding representative of layered materials,molybdenum disulfide(MoS_(2))has excellent physical properties,such as high carrier mobility,stability,and abundance on earth.Moreover,its reasonable band gap and microelectronic compatible fabrication characteristics makes it the most promising candidate in future advanced integrated circuits such as logical electronics,flexible electronics,and focal-plane photodetector.However,to realize the all-aspects application of MoS_(2),the research on obtaining high-quality and large-area films need to be continuously explored to promote its industrialization.Although the MoS_(2)grain size has already improved from several micrometers to sub-millimeters,the high-quality growth of wafer-scale MoS_(2)is still of great challenge.Herein,this review mainly focuses on the evolution of MoS_(2)by including chemical vapor deposition,metal–organic chemical vapor deposition,physical vapor deposition,and thermal conversion technology methods.The state-of-the-art research on the growth and optimization mechanism,including nucleation,orientation,grain,and defect engineering,is systematically summarized.Then,this review summarizes the wafer-scale application of MoS_(2)in a transistor,inverter,electronics,and photodetectors.Finally,the current challenges and future perspectives are outlined for the wafer-scale growth and application of MoS_(2).展开更多
Hybrid integration ofⅢ-Ⅴand ferroelectric materials is being broadly adopted to enhance functionalities in silicon photonic integrated circuits(PICs).Bonding and transfer printing have been the popular approaches fo...Hybrid integration ofⅢ-Ⅴand ferroelectric materials is being broadly adopted to enhance functionalities in silicon photonic integrated circuits(PICs).Bonding and transfer printing have been the popular approaches for integration of III–V gain media with silicon PICs.Similar approaches are also being considered for ferroelectrics to enable larger RF modulation bandwidths,higher linearity,lower optical loss integrated optical modulators on chip.In this paper,we review existing integration strategies ofⅢ-Ⅴmaterials and present a route towards hybrid integration of bothⅢ-Ⅴand ferroelectrics on the same chip.We show that adiabatic transformation of the optical mode between hybrid ferroelectric and silicon sections enables efficient transfer of optical modal energies for maximum overlap of the optical mode with the ferroelectric media,similar to approaches adopted to maximize optical overlap with the gain section,thereby reducing lasing thresholds for hybridⅢ-Ⅴintegration with silicon PICs.Preliminary designs are presented to enable a foundry compatible hybrid integration route of diverse functionalities on silicon PICs.展开更多
A 330-500 GHz zero-biased broadband monolithic integrated tripler is reported. The measured results show that the maximum efficiency and the maximum output power are 2% and 194μW at 348 GHz. The saturation characteri...A 330-500 GHz zero-biased broadband monolithic integrated tripler is reported. The measured results show that the maximum efficiency and the maximum output power are 2% and 194μW at 348 GHz. The saturation characteristic test shows that the output i dB compression point is about -8.5 dBm at 334 GHz and the maximum efficiency is obtained at the point, which is slightly below the 1 dB compression point. Compared with the conventional hybrid integrated circuit, a major advantage of the monolithic integrated circuit is the significant improvement of reliability and consistency. In this work, a terahertz monolithic frequency multiplier at this band is designed and fabricated.展开更多
A heavy-ion irradiation experiment is studied in digital storage cells with different design approaches in 130？nm CMOS bulk Si and silicon-on-insulator （SOI） technologies. The effectiveness of linear energy transf...A heavy-ion irradiation experiment is studied in digital storage cells with different design approaches in 130？nm CMOS bulk Si and silicon-on-insulator （SOI） technologies. The effectiveness of linear energy transfer （LET） with a tilted ion beam at the 130？nm technology node is obtained. Tests of tilted angles θ=0 ° , 30 ° and 60 ° with respect to the normal direction are performed under heavy-ion Kr with certain power whose LET is about 40？MeVcm 2 /mg at normal incidence. Error numbers in D flip-flop chains are used to determine their upset sensitivity at different incidence angles. It is indicated that the effective LETs for SOI and bulk Si are not exactly in inverse proportion to cosθ , furthermore the effective LET for SOI is more closely in inverse proportion to cosθ compared to bulk Si, which are also the well known behavior. It is interesting that, if we design the sample in the dual interlocked storage cell approach, the effective LET in bulk Si will look like inversely proportional to cosθ very well, which is also specifically explained.展开更多
An 'Integrated Device and Circuit simulator' for thin film (0.05-0.2μm) submicron (0.5μm) and deep submicron (0.15, 0.25,0.35μm) CMOS/ SOI integrated circuit has been developed. This simulator has been used...An 'Integrated Device and Circuit simulator' for thin film (0.05-0.2μm) submicron (0.5μm) and deep submicron (0.15, 0.25,0.35μm) CMOS/ SOI integrated circuit has been developed. This simulator has been used for design and fabrication and physical library development of thin film submicron and deep submicron CMOS/ SOI integrated circuit.展开更多
Device physics research for submicron and deep submicron space microelectronics devices and integrated circuits will be described in three topics.1.Thin film submicron and deep submicron SOS / CMOS devices and integra...Device physics research for submicron and deep submicron space microelectronics devices and integrated circuits will be described in three topics.1.Thin film submicron and deep submicron SOS / CMOS devices and integrated circuits.2.Deep submicron LDD CMOS devices and integrated circuits.3.C band and Ku band microwave GaAs MESFET and III-V compound hetrojunction HEM T and HBT devices and integrated circuits.展开更多
Electrical ground looks simple on a schematic; unfortunately, the actual performance of a circuit is dictated by its layout （and by its printed-circuit-board）. When the ground node moves, system performance suffers ...Electrical ground looks simple on a schematic; unfortunately, the actual performance of a circuit is dictated by its layout （and by its printed-circuit-board）. When the ground node moves, system performance suffers and the system radiates electromagnetic interferences. But the understanding of the physics of ground noise can provide an intuitive sense for reducing the problem. Ground bounce can produce transients with amplitudes of volts; most often changing magnetic flux is the cause; in this work, the authors use a Finite-Difference Time-Domain to begin to understand such phenomena. Additionally, predicting substrate cross-talks in mixed-signal circuits has become a critical issue to preserve signal integrity in future integrated systems. Phenomena that involve parasitic signal propagation into the substrate are discussed. A simple methodology to predict the substrate cross-talk and some associated tools are presented. Finally, the authors indicate a stochastic method which could grasp both outer or inner RF （Radio-Frequency） radiations and substrate parasites.展开更多
Advances in developing transitions in microwave integrated circuits during the last ten years are reviewed. Some typical structures of transition are introduced. Transition structures can be classified into two basic ...Advances in developing transitions in microwave integrated circuits during the last ten years are reviewed. Some typical structures of transition are introduced. Transition structures can be classified into two basic types: one is transition between the same kind of transmission lines on different planes of a common substrate, the other transition between different types of transmission lines. Furthermore, future development of transition structures is discussed.展开更多
Metal-insulator-metal （MIM） capacitors with atomic-layer-deposited Al2O3 dielectric and reactively sputtered TaN electrodes in application to radio frequency integrated circuits have been characterized electrically....Metal-insulator-metal （MIM） capacitors with atomic-layer-deposited Al2O3 dielectric and reactively sputtered TaN electrodes in application to radio frequency integrated circuits have been characterized electrically. The capacitors exhibit a high density of about 6.05 fF/μm^2, a small leakage current of 4.8 × 10^-8 A/cm^2 at 3 V, a high breakdown electric field of 8.61 MV/cm as well as acceptable voltage coefficients of capacitance （VCCs） of 795 ppm/V2 and 268ppm/V at 1 MHz. The observed properties should be attributed to high-quality Al2O3 film and chemically stable TaN electrodes. Further, a logarithmically linear relationship between quadratic VCC and frequency is observed due to the change of relaxation time with carrier mobility in the dielectric. The conduction mechanism in the high field ranges is dominated by the Poole-Frenkel emission, and the leakage current in the low field ranges is likely to be associated with trap-assisted tunnelling. Meanwhile, the Al2O3 dielectric presents charge trapping under low voltage stresses, and defect generation under high voltage stresses, and it has a hard-breakdown performance.展开更多
We formulate a “Moore’s law” for photonic integrated circuits (PICs) and their spatial integration density using two methods. One is decomposing the integrated photonics devices of diverse types into equivalent bas...We formulate a “Moore’s law” for photonic integrated circuits (PICs) and their spatial integration density using two methods. One is decomposing the integrated photonics devices of diverse types into equivalent basic elements, which makes a comparison with the generic elements of electronic integrated circuits more meaningful. The other is making a complex compo- nent equivalent to a series of basic elements of the same functionality, which is used to calculate the integration density for func- tional components realized with different structures. The results serve as a benchmark of the evolution of PICs and we can con- clude that the density of integration measured in this way roughly increases by a factor of 2 per year. The prospects for a continued increase of spatial integration density are discussed.展开更多
The difference between circuit design stage and time requirements has broadened with the increasing complexity of the circuit.A big database is needed to undertake important analytical work like statistical method,hea...The difference between circuit design stage and time requirements has broadened with the increasing complexity of the circuit.A big database is needed to undertake important analytical work like statistical method,heat research,and IR-drop research that results in extended running times.This unit focuses on the assessment of test strength.Because of the enormous number of successful designs for currentmodels and the unnecessary time required for every test,maximum energy ratings with all tests cannot be achieved.Nevertheless,test safety is important for producing trustworthy findings to avoid loss of output and harm to the chip.Generally,effective power assessment is only possible in a limited sample of pre-selected experiments.Thus,a key objective is to find the experiments that might give the worst situations again for testing power.It offers a machine-based circuit power estimation(MLCPE)system for the selection of exams.Two distinct techniques of predicting are utilized.Firstly,to find testings with power dissipation,it forecasts the behavior of testing.Secondly,the changemovement and energy data are linked to the semiconductor design,identifying small problem areas.Several types of algorithms are utilized.In particular,the methods compared.The findings show great accuracy and efficiency in forecasting.That enables such methods suitable for selecting the worst scenario.展开更多
文摘This Special Topic of the Journal of Semiconductors(JOS)features expanded versions of key articles presented at the 2024 IEEE International Conference on Integrated Circuits Technologies and Applications(ICTA),which was held in Hangzhou,Zhejiang,China,from October 25 to 27,2024.
基金supported by start-up capital of Ningbo Eastern Institute of technology。
文摘The relentless down-scaling of electronics grands the modern integrated circuits(ICs)with the high speed,low power dissipation and low cost,fulfilling diverse demands of modern life.Whereas,with the semiconductor industry entering into sub-10 nm technology nodes,degrading device performance and increasing power consumption give rise to insurmountable roadblocks confronted by modern ICs that need to be conquered to sustain the Moore law's life.Bulk semiconductors like prevalent Si are plagued by seriously degraded carrier mobility as thickness thinning down to sub-5 nm,which is imperative to maintain sufficient gate electrostatic controllability to combat the increasingly degraded short channel effects.Nowadays,the emergence of two-dimensional(2D)materials opens up new gateway to eschew the hurdles laid in front of the scaling trend of modern IC,mainly ascribed to their ultimately atomic thickness,capability to maintain carrier mobility with thickness thinning down,dangling-bonds free surface,wide bandgaps tunability and feasibility to constitute diverse heterostructures.Blossoming breakthroughs in discrete electronic device,such as contact engineering,dielectric integration and vigorous channel-length scaling,or large circuits arrays,as boosted yields,improved variations and full-functioned processor fabrication,based on 2D materials have been achieved nowadays,facilitating 2D materials to step under the spotlight of IC industry to be treated as the most potential future successor or complementary counterpart of incumbent Si to further sustain the down-scaling of modern IC.
文摘Vocational undergraduate education has entered a new stage of high-quality development,making the cultivation of students'learning ability a core issue in enhancing talent cultivation quality.This study conducted a questionnaire survey with 177 students majoring in integrated circuits at Shenzhen Polytechnic University(SZPU),focusing on six dimensions:self-learning proficiency,academic competence,goal planning,self-discipline,learning initiative,and learning environment.The results indicate that while students possess a solid learning foundation and clear career planning,significant deficiencies exist in the execution of academic plans,self-discipline,and learning initiative.In response to these issues,this study proposes four systematic improvement pathways from the institutional perspective:establishing a closed-loop academic navigation system incorporating“goal-process-feedback”,creating an immersive“virtual-physical integrated”learning environment,implementing a multi-dimensional“cognitive-affective-practical”initiative activation plan,and building a synergistic cultivation mechanism for“self-discipline and core competencies”.The findings aim to provide references for talent cultivation and teaching reform in vocational undergraduate integrated circuit programs.
基金supported by the National Key Research and Development Program(No.2022YFE0107400)the internal research funding from Photonic View Technology Technology Co.,Ltd.the GuangCi Deep Mind Project of Ruijin Hospital Shanghai Jiao Tong University School of Medicine.
文摘The single-molecule detection tech-nique plays a pivotal role in elucidat-ing the fundamental mechanisms of various scientific processes at the molecular level,and holds essential im-portance in multiple fields including physics,biology,and chemistry.Re-cently,single-molecule detection has garnered increasing attention owing to its practical utility in medical diagno-sis,primarily due to its exceptional sensitivity and the minimal sample volume required for analysis.However,the conventional single-molecule technique,represented by total internal reflection microscopy,faces challenges such as sophisticated operation procedures and limited detection throughput,thereby impeding its broader application.To address these limitations,we have demonstrated single-molecule detection using an integrated silicon photonic chip,of-fering a cost-effective and user-friendly alternative.By employing basic optics,we efficiently introduce the excitation source for single-molecule fluorescence by harnessing the strong evanescent field of high refractive-index waveguides.Subsequently,fluorescence signals are collected using basic optics comprising a water-immersion objective,relay optics,and a digi-tal camera.Our results highlight a low-cost,high-throughput single-molecule technique achieved through the integrated silicon photonic chip.This innovative approach is promised to facilitate the widespread adoption of single-molecule fluorescence in medical diagnosis.
基金funded by the National Nature Science Foundation of China(Grant Nos.52175509 and 52130504)National Key Research and Development Program of China(2017YFF0204705)2021 Postdoctoral Innovation Research Plan of Hubei Province(0106100226)。
文摘Multi-level programmable photonic integrated circuits(PICs)and optical metasurfaces have gained widespread attention in many fields,such as neuromorphic photonics,opticalcommunications,and quantum information.In this paper,we propose pixelated programmable Si_(3)N_(4)PICs with record-high 20-level intermediate states at 785 nm wavelength.Such flexibility in phase or amplitude modulation is achieved by a programmable Sb_(2)S_(3)matrix,the footprint of whose elements can be as small as 1.2μm,limited only by the optical diffraction limit of anin-house developed pulsed laser writing system.We believe our work lays the foundation for laser-writing ultra-high-level(20 levels and even more)programmable photonic systems and metasurfaces based on phase change materials,which could catalyze diverse applications such as programmable neuromorphic photonics,biosensing,optical computing,photonic quantum computing,and reconfigurable metasurfaces.
文摘This article addresses the past,present,and future status of hybrid plasmonic waveguides(HPWs).It presents a comprehensive review of HPW-based photonic integrated circuits(PICs),covering both passive and active devices,as well as potential application of on-chip HPWbased devices.HPW-based integrated circuits(HPWICs)are compatible with complementary metal oxide semiconductor technology,and their matched refractive indices enables the adaptation of existing fabrication processes for silicon-on-insulator designs.HPWs combine plasmonic and photonic waveguide components to provide strong confinement with longer propagation length L_(p)of HP modes with nominal losses.These HPWs are able to make a trade-off between low loss and longer L_(p),which is not possible with independent plasmonic and photonic waveguide components owing to their inability to simultaneously achieve low propagation loss with rapid and effective all-optical functionality.With HPWs,it is possible to overcome challenges such as high Ohmic losses and enhance the functional performance of PICs through the use of multiple discrete components.HPWs have been employed not only to guide transverse magnetic modes but also for optical beam manipulation,wireless optical communication,filtering,computation,sensing of bending,optical signal emission,and splitting.They also have the potential to play a pivotal role in optical communication systems for quantum computing and within data centers.At present,HPW-based PICs are poised to transform wireless chip-to-chip communication,a number of areas of biomedical science,machine learning,and artificial intelligence,as well as enabling the creation of densely integrated circuits and highly compact photonic devices.
文摘Based on the physical characteristics of SiGe material,a new three-dimensional （3D） CMOS IC structure is proposed,in which the first device layer is made of Si material for nMOS devices and the second device layer is made of Six Ge1- x material for pMOS. The intrinsic performance of ICs with the new structure is then limited by Si nMOS.The electrical characteristics of a Si-SiGe 3D CMOS device and inverter are all simulated and analyzed by MEDICI. The simulation results indicate that the Si-SiGe 3D CMOS ICs are faster than the Si-Si 3D CMOS ICs. The delay time of the 3D Si-SiGe CMOS inverter is 2-3ps,which is shorter than that of the 3D Si-Si CMOS inverter.
基金Project supported by the National Natural Science Foundation of China(Grant Nos.61131001,61322405,61204044,61376039,and 61334003)
文摘Through-silicon-via （TSV） to TSV crosstalk noise is one of the key factors affecting the signal integrity of three- dimensional integrated circuits （3D ICs）. Based on the frequency dependent equivalent electrical parameters for the TSV channel, an analytical crosstalk noise model is established to capture the TSV induced crosstalk noise. The impact of various design parameters including insulation dielectric, via pitch, via height, silicon conductivity, and terminal impedance on the crosstalk noise is analyzed with the proposed model. Two approaches are proposed to alleviate the TSV noise, namely, driver sizing and via shielding, and the SPICE results show 241 rnV and 379 mV reductions in the peak noise voltage, respectively.
基金financially the National Natural Science Foundation of China(52002254,52272160)Sichuan Science and Technology Foundation(2020YJ0262,2021YFH0127,2022YFSY0045,2022YFH0083 and 23SYSX0060)+3 种基金the Chunhui plan of Ministry of Education,Fundamental Research Funds for the Central Universities,China(YJ201893)the Open-Foundation of Key Laboratory of Laser Device Technology,China North Industries Group Corporation Limited(Grant No.KLLDT202104)the foundation of the State Key Laboratory of Solidification Processing in NWPU(No.SKLSP202210)the 2035-Plan of Sichuan University。
文摘As an outstanding representative of layered materials,molybdenum disulfide(MoS_(2))has excellent physical properties,such as high carrier mobility,stability,and abundance on earth.Moreover,its reasonable band gap and microelectronic compatible fabrication characteristics makes it the most promising candidate in future advanced integrated circuits such as logical electronics,flexible electronics,and focal-plane photodetector.However,to realize the all-aspects application of MoS_(2),the research on obtaining high-quality and large-area films need to be continuously explored to promote its industrialization.Although the MoS_(2)grain size has already improved from several micrometers to sub-millimeters,the high-quality growth of wafer-scale MoS_(2)is still of great challenge.Herein,this review mainly focuses on the evolution of MoS_(2)by including chemical vapor deposition,metal–organic chemical vapor deposition,physical vapor deposition,and thermal conversion technology methods.The state-of-the-art research on the growth and optimization mechanism,including nucleation,orientation,grain,and defect engineering,is systematically summarized.Then,this review summarizes the wafer-scale application of MoS_(2)in a transistor,inverter,electronics,and photodetectors.Finally,the current challenges and future perspectives are outlined for the wafer-scale growth and application of MoS_(2).
文摘Hybrid integration ofⅢ-Ⅴand ferroelectric materials is being broadly adopted to enhance functionalities in silicon photonic integrated circuits(PICs).Bonding and transfer printing have been the popular approaches for integration of III–V gain media with silicon PICs.Similar approaches are also being considered for ferroelectrics to enable larger RF modulation bandwidths,higher linearity,lower optical loss integrated optical modulators on chip.In this paper,we review existing integration strategies ofⅢ-Ⅴmaterials and present a route towards hybrid integration of bothⅢ-Ⅴand ferroelectrics on the same chip.We show that adiabatic transformation of the optical mode between hybrid ferroelectric and silicon sections enables efficient transfer of optical modal energies for maximum overlap of the optical mode with the ferroelectric media,similar to approaches adopted to maximize optical overlap with the gain section,thereby reducing lasing thresholds for hybridⅢ-Ⅴintegration with silicon PICs.Preliminary designs are presented to enable a foundry compatible hybrid integration route of diverse functionalities on silicon PICs.
基金Supported by the National High-Technology Research and Development Program of China under Grant No 2011AA010203the National Basic Research Program of China under Grant Nos 2011CB201704 and 2010CB327502the National Natural Science Foundation of China under Grant Nos 61434006 and 61106074
文摘A 330-500 GHz zero-biased broadband monolithic integrated tripler is reported. The measured results show that the maximum efficiency and the maximum output power are 2% and 194μW at 348 GHz. The saturation characteristic test shows that the output i dB compression point is about -8.5 dBm at 334 GHz and the maximum efficiency is obtained at the point, which is slightly below the 1 dB compression point. Compared with the conventional hybrid integrated circuit, a major advantage of the monolithic integrated circuit is the significant improvement of reliability and consistency. In this work, a terahertz monolithic frequency multiplier at this band is designed and fabricated.
基金Supported by the Key Laboratory of Microsatellites,Chinese Academy of Sciences
文摘A heavy-ion irradiation experiment is studied in digital storage cells with different design approaches in 130？nm CMOS bulk Si and silicon-on-insulator （SOI） technologies. The effectiveness of linear energy transfer （LET） with a tilted ion beam at the 130？nm technology node is obtained. Tests of tilted angles θ=0 ° , 30 ° and 60 ° with respect to the normal direction are performed under heavy-ion Kr with certain power whose LET is about 40？MeVcm 2 /mg at normal incidence. Error numbers in D flip-flop chains are used to determine their upset sensitivity at different incidence angles. It is indicated that the effective LETs for SOI and bulk Si are not exactly in inverse proportion to cosθ , furthermore the effective LET for SOI is more closely in inverse proportion to cosθ compared to bulk Si, which are also the well known behavior. It is interesting that, if we design the sample in the dual interlocked storage cell approach, the effective LET in bulk Si will look like inversely proportional to cosθ very well, which is also specifically explained.
文摘Submicron CMOS IC technology, including triple layer resist lithography technology, RIE, LDD, Titanium Salicide, shallow junction, thin gate oxide, no bird's beak isolation and channel's multiple implantation doping technology have been developed. 0.50μm. CMOS integrated circuits have been fabricated using this submicron CMOS process.
文摘An 'Integrated Device and Circuit simulator' for thin film (0.05-0.2μm) submicron (0.5μm) and deep submicron (0.15, 0.25,0.35μm) CMOS/ SOI integrated circuit has been developed. This simulator has been used for design and fabrication and physical library development of thin film submicron and deep submicron CMOS/ SOI integrated circuit.
文摘Device physics research for submicron and deep submicron space microelectronics devices and integrated circuits will be described in three topics.1.Thin film submicron and deep submicron SOS / CMOS devices and integrated circuits.2.Deep submicron LDD CMOS devices and integrated circuits.3.C band and Ku band microwave GaAs MESFET and III-V compound hetrojunction HEM T and HBT devices and integrated circuits.
文摘Electrical ground looks simple on a schematic; unfortunately, the actual performance of a circuit is dictated by its layout （and by its printed-circuit-board）. When the ground node moves, system performance suffers and the system radiates electromagnetic interferences. But the understanding of the physics of ground noise can provide an intuitive sense for reducing the problem. Ground bounce can produce transients with amplitudes of volts; most often changing magnetic flux is the cause; in this work, the authors use a Finite-Difference Time-Domain to begin to understand such phenomena. Additionally, predicting substrate cross-talks in mixed-signal circuits has become a critical issue to preserve signal integrity in future integrated systems. Phenomena that involve parasitic signal propagation into the substrate are discussed. A simple methodology to predict the substrate cross-talk and some associated tools are presented. Finally, the authors indicate a stochastic method which could grasp both outer or inner RF （Radio-Frequency） radiations and substrate parasites.
基金Supported by the Specialized Research Fund for the Doctoral Program of Higher Education (No.20010614003) and the Key Project of Chinese Ministry of Education(No.104166).
文摘Advances in developing transitions in microwave integrated circuits during the last ten years are reviewed. Some typical structures of transition are introduced. Transition structures can be classified into two basic types: one is transition between the same kind of transmission lines on different planes of a common substrate, the other transition between different types of transmission lines. Furthermore, future development of transition structures is discussed.
基金Project supported by the National Natural Science Foundation of China （Grant No 90607023）, Shanghai Pujiang Program （Grant No 05PJ14017）, SRF for R0CS, SEM, and the Micro/Nano-electronics Science and Technology Innovation Platform （985） and the Ministry of Education of China in the International Research Training Group ＂Materials and Concepts for Advanced Interconnects
文摘Metal-insulator-metal （MIM） capacitors with atomic-layer-deposited Al2O3 dielectric and reactively sputtered TaN electrodes in application to radio frequency integrated circuits have been characterized electrically. The capacitors exhibit a high density of about 6.05 fF/μm^2, a small leakage current of 4.8 × 10^-8 A/cm^2 at 3 V, a high breakdown electric field of 8.61 MV/cm as well as acceptable voltage coefficients of capacitance （VCCs） of 795 ppm/V2 and 268ppm/V at 1 MHz. The observed properties should be attributed to high-quality Al2O3 film and chemically stable TaN electrodes. Further, a logarithmically linear relationship between quadratic VCC and frequency is observed due to the change of relaxation time with carrier mobility in the dielectric. The conduction mechanism in the high field ranges is dominated by the Poole-Frenkel emission, and the leakage current in the low field ranges is likely to be associated with trap-assisted tunnelling. Meanwhile, the Al2O3 dielectric presents charge trapping under low voltage stresses, and defect generation under high voltage stresses, and it has a hard-breakdown performance.
文摘We formulate a “Moore’s law” for photonic integrated circuits (PICs) and their spatial integration density using two methods. One is decomposing the integrated photonics devices of diverse types into equivalent basic elements, which makes a comparison with the generic elements of electronic integrated circuits more meaningful. The other is making a complex compo- nent equivalent to a series of basic elements of the same functionality, which is used to calculate the integration density for func- tional components realized with different structures. The results serve as a benchmark of the evolution of PICs and we can con- clude that the density of integration measured in this way roughly increases by a factor of 2 per year. The prospects for a continued increase of spatial integration density are discussed.
基金supported by Dr S Karthik,SRM Institute of Science and TechnologySRM Institute of Science and Technology,Vadapalani Campus,Chennai,Tamilnadu,India。
文摘The difference between circuit design stage and time requirements has broadened with the increasing complexity of the circuit.A big database is needed to undertake important analytical work like statistical method,heat research,and IR-drop research that results in extended running times.This unit focuses on the assessment of test strength.Because of the enormous number of successful designs for currentmodels and the unnecessary time required for every test,maximum energy ratings with all tests cannot be achieved.Nevertheless,test safety is important for producing trustworthy findings to avoid loss of output and harm to the chip.Generally,effective power assessment is only possible in a limited sample of pre-selected experiments.Thus,a key objective is to find the experiments that might give the worst situations again for testing power.It offers a machine-based circuit power estimation(MLCPE)system for the selection of exams.Two distinct techniques of predicting are utilized.Firstly,to find testings with power dissipation,it forecasts the behavior of testing.Secondly,the changemovement and energy data are linked to the semiconductor design,identifying small problem areas.Several types of algorithms are utilized.In particular,the methods compared.The findings show great accuracy and efficiency in forecasting.That enables such methods suitable for selecting the worst scenario.
