The effects of source-drain underlaps on the performance of a top gate silicon nanowire on insulator transistor are studied using a three dimensional(3D) self-consistent Poisson-Schrodinger quantum simulation. Voltage...The effects of source-drain underlaps on the performance of a top gate silicon nanowire on insulator transistor are studied using a three dimensional(3D) self-consistent Poisson-Schrodinger quantum simulation. Voltage-controlled tunnel barrier is the device transport physics. The off current, the on/off current ratio, and the inverse subthreshold slope are improved while the on current is degraded with underlap. The physics behind this behavior is the modulation of a tunnel barrier with underlap. The underlap primarily affects the tunneling component of drain current. About 50% contribution to the gate capacitance comes from the fringing electric fields emanating from the gate metal to the source and drain. The gate capacitance reduces with underlap, which should reduce the intrinsic switching delay and increase the intrinsic cut-off frequency. However, both the on current and the transconductance reduce with underlap, and the consequence is the increase of delay and the reduction of cut-off frequency.展开更多
Low-frequency noise（LFN） in all operation regions of amorphous indium zinc oxide（a-IZO） thin film transistors（TFTs） with an aluminum oxide gate insulator is investigated. Based on the LFN measured results, we ex...Low-frequency noise（LFN） in all operation regions of amorphous indium zinc oxide（a-IZO） thin film transistors（TFTs） with an aluminum oxide gate insulator is investigated. Based on the LFN measured results, we extract the distribution of localized states in the band gap and the spatial distribution of border traps in the gate dielectric,and study the dependence of measured noise on the characteristic temperature of localized states for a-IZO TFTs with Al2 O3 gate dielectric. Further study on the LFN measured results shows that the gate voltage dependent noise data closely obey the mobility fluctuation model, and the average Hooge＇s parameter is about 1.18×10^-3.Considering the relationship between the free carrier number and the field effect mobility, we simulate the LFN using the △N-△μ model, and the total trap density near the IZO/oxide interface is about 1.23×10^18 cm^-3eV^-1.展开更多
In this paper, a novel dual-gate and dielectric-inserted lateral trench insulated gate bipolar transistor （DGDI LTIGBT） structure, which features a double extended trench gate and a dielectric inserted in the drift ...In this paper, a novel dual-gate and dielectric-inserted lateral trench insulated gate bipolar transistor （DGDI LTIGBT） structure, which features a double extended trench gate and a dielectric inserted in the drift region, is proposed and discussed. The device can not only decrease the specific on-resistance Ron,sp , but also simultaneously improve the temperature performance. Simulation results show that the proposed LTIGBT achieves an ultra-low on-state voltage drop of 1.31 V at 700 A·cm-2 with a small half-cell pitch of 10.5 μm, a specific on-resistance R on,sp of 187 mΩ·mm2, and a high breakdown voltage of 250 V. The on-state voltage drop of the DGDI LTIGBT is 18% less than that of the DI LTIGBT and 30.3% less than that of the conventional LTIGBT. The proposed LTIGBT exhibits a good positive temperature coefficient for safety paralleling to handling larger currents and enhances the short-circuit capability while maintaining a low self-heating effect. Furthermore, it also shows a better tradeoff between the specific on-resistance and the turnoff loss, although it has a longer turnoff delay time.展开更多
A high voltage（〉 600 V） integrable silicon-on-insulator（SOI） trench-type lateral insulated gate bipolar transistor（LIGBT） with a reduced cell-pitch is proposed.The LIGBT features multiple trenches（MTs）：two o...A high voltage（〉 600 V） integrable silicon-on-insulator（SOI） trench-type lateral insulated gate bipolar transistor（LIGBT） with a reduced cell-pitch is proposed.The LIGBT features multiple trenches（MTs）：two oxide trenches in the drift region and a trench gate extended to the buried oxide（BOX）.Firstly,the oxide trenches enhance electric field strength because of the lower permittivity of oxide than that of Si.Secondly,oxide trenches bring in multi-directional depletion,leading to a reshaped electric field distribution and an enhanced reduced-surface electric-field（RESURF） effect.Both increase the breakdown voltage（BV）.Thirdly,oxide trenches fold the drift region around the oxide trenches,leading to a reduced cell-pitch.Finally,the oxide trenches enhance the conductivity modulation,resulting in a high electron/hole concentration in the drift region as well as a low forward voltage drop（Von）.The oxide trenches cause a low anode-cathode capacitance,which increases the switching speed and reduces the turn-off energy loss（Eoff）.The MT SOI LIGBT exhibits a BV of 603 V at a small cell-pitch of 24 μm,a Von of 1.03 V at 100 A/cm-2,a turn-off time of 250 ns and Eoff of 4.1×10？3 mJ.The trench gate extended to BOX synchronously acts as dielectric isolation between high voltage LIGBT and low voltage circuits,simplifying the fabrication processes.展开更多
Low-frequency flicker noise is usually associated with material defects or imperfection of fabrication procedure. Up to now, there is only very limited knowledge about flicker noise of the topological insulator, whose...Low-frequency flicker noise is usually associated with material defects or imperfection of fabrication procedure. Up to now, there is only very limited knowledge about flicker noise of the topological insulator, whose topologically protected conducting surface is theoretically immune to back scattering. To suppress the bulk conductivity we synthesize antimony doped Bi2Se3 nanowires and conduct transport measurements at cryogenic temperatures. The low-frequency current noise measurement shows that the noise amplitude at the high-drain current regime can be described by Hooge＇s empirical relationship, while the noise level is significantly lower than that predicted by Hooge＇s model near the Dirac point. Furthermore, different frequency responses of noise power spectrum density for specific drain currents at the low drain current regime indicate the complex origin of noise sources of topological insulator.展开更多
A novel lateral insulated gate bipolar transistor on a silicon-on-insulator substrate SOI-LIGBT with a special low-doped P-well structure is proposed.The P-well structure is added to attach the P-body under the channe...A novel lateral insulated gate bipolar transistor on a silicon-on-insulator substrate SOI-LIGBT with a special low-doped P-well structure is proposed.The P-well structure is added to attach the P-body under the channel so as to reduce the linear anode current degradation without additional process.The influence of the length and depth of the P-well on the hot-carrier HC reliability of the SOI-LIGBT is studied.With the increase in the length of the P-well the perpendicular electric field peak and the impact ionization peak diminish resulting in the reduction of the hot-carrier degradation. In addition the impact ionization will be weakened with the increase in the depth of the P-well which also makes the hot-carrier degradation decrease.Considering the effect of the low-doped P-well and the process windows the length and depth of the P-well are both chosen as 2 μm.展开更多
Effective thermal control systems are essential for the reliable working of insulated gate bipolar transistors （IGBTs） in many applications. A novel spray cooling loop system with integrated sintered porous copper w...Effective thermal control systems are essential for the reliable working of insulated gate bipolar transistors （IGBTs） in many applications. A novel spray cooling loop system with integrated sintered porous copper wick （SCLS-SPC） is proposed to meet the requirements of higher device level heat fluxes and the harsh environments in some applications such as hybrid, fuel cell vehicles and aerospace. Fuzzy logic and proportional-integral-derivative （PID） policies are applied to adjust the electronic temperature within a safe working range. To evaluate the thermal control effect, a mathematical model of a 4-node thermal network and pump are established for predicting the dynamics of the SCLS-SPC. Moreover, the transient response of the 4 nodes and vapor mass flowrate under no control, PID and Fuzzy-PID are numerically investigated and discussed in detail.展开更多
A novel high performance trench field stop （TFS） superjunction （S J） insulated gate bipolar transistor （IGBT） with a buried oxide （BO） layer is proposed in this paper. The BO layer inserted between the P-base ...A novel high performance trench field stop （TFS） superjunction （S J） insulated gate bipolar transistor （IGBT） with a buried oxide （BO） layer is proposed in this paper. The BO layer inserted between the P-base and the SJ drift region acts as a barrier layer for the hole-carrier in the drift region. Therefore, conduction modulation in the emitter side of the SJ drift region is enhanced significantly and the carrier distribution in the drift region is optimized for the proposed structure. As a result, compared with the conventional TFS SJ IGBT （Conv-SJ）, the proposed BO-SJ IGBT structure possesses a drastically reduced on-state voltage drop （gce（on）） and an improved tradeoff between gee（on） and turn-off loss （Eoff）, with no breakdown voltage （BV） degraded. The results show that with the spacing between the gate and the BO layer Wo = 0.2 μm, the thickness of the BO layer Lo = 0.2 μm, the thickness of the drift region Ld = 90 μm, the half width and doping concentration of the N- and P-pillars Wn = Wp = 2.5μm and Nn = Np = 3 × 10^15 cm^-3, the Vce（on） and Eoff of the proposed structure are 1.08 V and 2.81 mJ/cm2 with the collector doping concentration Nc = 1 × 10^18 cm^-3 and 1.12 V and 1.73 mJ/cm2 with Nc = 5 × 10^17 cm^-3, respectively. However, with the same device parameters, the Vce（on） and Eoff for the Conv-SJ are 1.81 V and 2.88 mJ/cm2 with Nc= 1 × 10^18 cm^-3 and 1.98 V and 2.82 mJ/cm2 with Nc = 5 ×10^17 cm^-3, respectively. Meanwhile, the BV of the proposed structure and Conv-SJ are 1414 V and 1413 V, respectively.展开更多
A novel ultralow turnoff loss dual-gate silicon-on-insulator （SOI） lateral insulated gate bipolar transistor （LIGBT） is proposed. The proposed SOI LIGBT features an extra trench gate inserted between the p-well an...A novel ultralow turnoff loss dual-gate silicon-on-insulator （SOI） lateral insulated gate bipolar transistor （LIGBT） is proposed. The proposed SOI LIGBT features an extra trench gate inserted between the p-well and n-drift, and an n-type carrier stored （CS） layer beneath the p-well. In the on-state, the extra trench gate acts as a barrier, which increases the cartier density at the cathode side of n-drift region, resulting in a decrease of the on-state voltage drop （Von）. In the off-state, due to the uniform carder distribution and the assisted depletion effect induced by the extra trench gate, large number of carriers can be removed at the initial turnoff process, contributing to a low turnoff loss （Eoff）. Moreover, owing to the dual-gate field plates and CS layer, the carrier density beneath the p-well can greatly increase, which further improves the tradeoff between Eoff and Von. Simulation results show that Eoff of the proposed SOI LIGBT can decrease by 77% compared with the conventional trench gate SOI LIGBT at the same Von of 1.1 V.展开更多
We present a detailed study of a superjunction （S J） nanoscale partially narrow mesa （PNM） insulated gate bipolar transistor （IGBT） structure. This structure is created by combining the nanoscale PNM structure a...We present a detailed study of a superjunction （S J） nanoscale partially narrow mesa （PNM） insulated gate bipolar transistor （IGBT） structure. This structure is created by combining the nanoscale PNM structure and the SJ structure together. It demonstrates an ultra-low saturation voltage （Vce（sat）） and low turn-off loss （Eoff） while maintaining other device parameters. Compared with the conventional 1.2 kV trench IGBT, our simulation result shows that the gce（sat） of this structure decreases to 0.94 V, which is close to the theoretical limit of 1.2 kV IGBT, Meanwhile, the fall time decreases from 109.7 ns to 12 ns and the Eoff is down to only 37% of that of the conventional structure. The superior tradeoff characteristic between Vce（sat） and Eoff is presented owing to the nanometer level mesa width and SJ structure. Moreover, the short circuit degeneration phenomenon in the very narrow mesa structure due to the collector-induced barriers lowering （CIBL） effect is not observed in this structure. Thus, enough short circuit ability can be achieved by using wide, floating P-well technique. Based on these structure advantages, the SJ-PNM-IGBT with nanoscale mesa width indicates a potentially superior overall performance towards the IGBT parameter limit.展开更多
A novel 4H-Si C trench insulated gate bipolar transistor(IGBT)with a controllable hole-extracting(CHE)path is proposed and investigated in this paper.The CHE path is controlled by metal semiconductor gate(MES gate)and...A novel 4H-Si C trench insulated gate bipolar transistor(IGBT)with a controllable hole-extracting(CHE)path is proposed and investigated in this paper.The CHE path is controlled by metal semiconductor gate(MES gate)and metal oxide semiconductor gate(MOS gate)in the p-shield region.The grounded p-shield region can significantly suppress the high electric field around gate oxide in Si C devices,but it weakens the conductivity modulation in the Si C trench IGBT by rapidly sweeping out holes.This effect can be eliminated by introducing the CHE path.The CHE path is pinched off by the high gate bias voltage at on-state to maintain high conductivity modulation and obtain a comparatively low on-state voltage(VON).During the turn-off transient,the CHE path is formed,which contributes to a decreased turn-off loss(EOFF).Based on numerical simulation,the EOFFof the proposed IGBT is reduced by 89%compared with the conventional IGBT at the same VONand the VONof the proposed IGBT is reduced by 50%compared to the grounded p-shield IGBT at the same EOFF.In addition,the average power reduction for the proposed device can be 51.0%to 81.7%and 58.2%to 72.1%with its counterparts at a wide frequency range of 500 Hz to 10 k Hz,revealing a great improvement of frequency characteristics.展开更多
Rotor chopper control is a simple and effective drive method for induction motor. This paper presents a novel IGBT chopper topology,which can both adjust rotor resistance and protect IGBT efficiently. Investigation on...Rotor chopper control is a simple and effective drive method for induction motor. This paper presents a novel IGBT chopper topology,which can both adjust rotor resistance and protect IGBT efficiently. Investigation on the quasi transient state of the rotor rectifying circuit is made, and a nonlinear mapping between the equivalent resistance and the duty cycle is deduced. Furthermore, the method for determining the magnitude of the external resistor is introduced.展开更多
This paper introduces the Insulated gate bipolar transistor(IGBT)in- verter for arc welding.The principle of the inverter,the structure and charac- teristics of IGBT and the current feedback system using LEM current t...This paper introduces the Insulated gate bipolar transistor(IGBT)in- verter for arc welding.The principle of the inverter,the structure and charac- teristics of IGBT and the current feedback system using LEM current transduc- er are discussed.By the measurement of its efficiency and power factor and the tests of welding processes,the developed 150A IGBT inverter proves to be a kind of energy-saving portable power supply for arc welding with broad prospects.展开更多
A lateral insulated gate bipolar transistor(LIGBT)based on silicon-on-insulator(SOI)structure is proposed and investigated.This device features a compound dielectric buried layer(CDBL)and an assistant-depletion trench...A lateral insulated gate bipolar transistor(LIGBT)based on silicon-on-insulator(SOI)structure is proposed and investigated.This device features a compound dielectric buried layer(CDBL)and an assistant-depletion trench(ADT).The CDBL is employed to introduce two high electric field peaks that optimize the electric field distributions and that,under the same breakdown voltage(BV)condition,allow the CDBL to acquire a drift region of shorter length and a smaller number of stored carriers.Reducing their numbers helps in fast-switching.Furthermore,the ADT contributes to the rapid extraction of the stored carriers from the drift region as well as the formation of an additional heat-flow channel.The simulation results show that the BV of the proposed LIGBT is increased by 113%compared with the conventional SOI LIGBT of the same length L_(D).Contrastingly,the length of the drift region of the proposed device(11.2μm)is about one third that of a traditional device(33μm)with the same BV of 141 V.Therefore,the turn-off loss(E_(OFF))of the CDBL SOI LIGBT is decreased by 88.7%compared with a conventional SOI LIGBT when the forward voltage drop(VF)is 1.64 V.Moreover,the short-circuit failure time of the proposed device is 45%longer than that of the conventional SOI LIGBT.Therefor,the proposed CDBL SOI LIGBT exhibits a better V_(F)-E_(OFF)tradeoff and an improved short-circuit robustness.展开更多
A novel silicon carbide gate-controlled bipolar field effect composite transistor with poly silicon region(SiC GCBTP)is proposed.Different from the traditional electrode connection mode of SiC vertical diffused MOS(VD...A novel silicon carbide gate-controlled bipolar field effect composite transistor with poly silicon region(SiC GCBTP)is proposed.Different from the traditional electrode connection mode of SiC vertical diffused MOS(VDMOS),the P+region of P-well is connected with the gate in SiC GCBTP,and the polysilicon region is added between the P+region and the gate.By this method,additional minority carriers can be injected into the drift region at on-state,and the distribution of minority carriers in the drift region will be optimized,so the on-state current is increased.In terms of static characteristics,it has the same high breakdown voltage(811 V)as SiC VDMOS whose length of drift is 5.5μm.The on-state current of SiC GCBTP is 2.47×10^(-3)A/μm(V_(G)=10 V,V_(D)=10 V)which is 5.7 times of that of SiC IGBT and 36.4 times of that of SiC VDMOS.In terms of dynamic characteristics,the turn-on time of SiC GCBTP is only 0.425 ns.And the turn-off time of SiC GCBTP is similar to that of SIC insulated gate bipolar transistor(IGBT),which is 114.72 ns.展开更多
A novel trench insulated gate bipolar transistor(IGBT) with improved dynamic characteristics is proposed and investigated. The poly gate and poly emitter of the proposed IGBT are arranged alternately along the trench....A novel trench insulated gate bipolar transistor(IGBT) with improved dynamic characteristics is proposed and investigated. The poly gate and poly emitter of the proposed IGBT are arranged alternately along the trench. A self-biased p-MOSFET is formed on the emitter side. Owing to this unique three-dimensional(3D) trench architecture, both the turnoff characteristic and the turn-on characteristic can be greatly improved. At the turn-off moment, the maximum electric field and impact ionization rate of the proposed IGBT decrease and the dynamic avalanche(DA) is suppressed. Comparing with the carrier-stored trench gate bipolar transistor(CSTBT), the turn-off loss(E_(off)) of the proposed IGBT also decreases by 31% at the same ON-state voltage. At the turn-on moment, the built-in p-MOSFET reduces the reverse displacement current(I_(G_dis)), which is conducive to lowing dI_(C)/d_(t). As a result, compared with the CSTBT with the same turn-on loss(E_(on)), at I_(C) = 20 A/cm^(2), the proposed IGBT decreases by 35% of collector surge current(I_(surge)) and 52% of dI_(C)/d_(t).展开更多
With the widespread use of high-power and highly integrated insulated gate bipolar transistor(IGBT),their cooling methods have become challenging.This paper proposes a liquid cooling scheme for heavy-duty automated gu...With the widespread use of high-power and highly integrated insulated gate bipolar transistor(IGBT),their cooling methods have become challenging.This paper proposes a liquid cooling scheme for heavy-duty automated guided vehicle(AGV)motor driver in port environment,and improves heat dissipation by analyzing and optimizing the core component of finned heat sink.Firstly,the temperature distribution of the initial scheme is studied by using Fluent software,and the heat transfer characteristics of the finned heat sink are obtained through numerical analysis.Secondly,an orthogonal test is designed and combined with the response surface methodology to optimize the structural parameters of the finned heat sink,resulting in a 14.57%increase in the heat dissipation effect.Finally,the effectiveness of heat dissipation enhancement is verified.This work provides valuable insights into improving the heat dissipation of IGBT modules and heat sinks,and provides guidance for their future applications.展开更多
In this paper,ground-signal-ground type through-silicon vias（TSVs） exploiting air gaps as insulation layers are designed,analyzed and simulated for applications in millimeter wave.The compact wideband equivalent-cir...In this paper,ground-signal-ground type through-silicon vias（TSVs） exploiting air gaps as insulation layers are designed,analyzed and simulated for applications in millimeter wave.The compact wideband equivalent-circuit model and passive elements（RLGC） parameters based on the physical parameters are presented with the frequency up to 100 GHz.The parasitic capacitance of TSVs can be approximated as the dielectric capacitance of air gaps when the thickness of air gaps is greater than 0.75 μm.Therefore,the applied voltage of TSVs only needs to achieve the flatband voltage,and there is no need to indicate the threshold voltage.This is due to the small permittivity of air gaps.The proposed model shows good agreement with the simulation results of ADS and Ansoft＇s HFSS over a wide frequency range.展开更多
In this study, we investigate the single-event transient（SET） characteristics of a partially depleted silicon-on-insulator（PDSOI） metal-oxide-semiconductor（MOS） device induced by a pulsed laser.We measure and an...In this study, we investigate the single-event transient（SET） characteristics of a partially depleted silicon-on-insulator（PDSOI） metal-oxide-semiconductor（MOS） device induced by a pulsed laser.We measure and analyze the drain transient current at the wafer level. The results indicate that the body-drain junction and its vicinity are more SET sensitive than the other regions in PD-SOI devices.We use ISE 3D simulation tools to analyze the SET response when different regions of the device are hit. Then, we discuss in detail the characteristics of transient currents and the electrostatic potential distribution change in devices after irradiation. Finally, we analyze the parasitic bipolar junction transistor（p-BJT） effect by performing both a laser test and simulations.展开更多
The popularity of insulated gate bipolar transistors(IGBTs)for use in high-voltage direct current(HVDC)transmission and flexible AC transmission systems(FACTS)is increasing.Unfortunately,for these applications wire-bo...The popularity of insulated gate bipolar transistors(IGBTs)for use in high-voltage direct current(HVDC)transmission and flexible AC transmission systems(FACTS)is increasing.Unfortunately,for these applications wire-bond IGBT technology has a number of shortcomings,such as insufficient current ratings for the most powerful schemes,and inability to fail to short-circuit.Press-pack IGBT technology,conversely,offers increased current ratings,and an inherent short-circuit failure mode,making it a more attractive choice for HVDC and FACTS.However,the design and manufacture of these devices requires a comprehensive understanding of the unique technical challenges,which differ markedly from those for wirebond modules or traditional pressure contact devices.Specific challenges include providing a high degree of mechanical protection for the IGBT chip against normal operating stresses.Furthermore,it is essential to achieve uniform contact pressure across each chip surface to ensure optimum performance.To achieve this,manufacturers have designed products that use rigid copper electrodes manufactured to tighter tolerances than for other pressure contact devices,such as thyristors,and products that use compliant electrodes,incorporating spring assemblies.Dynex is in the advanced stages of development of press-pack IGBT technology with demonstrated robust solutions for the technical challenges outlined in this paper.Design success has been achieved through the use of state-of-the-art simulations in conjunction with a long history of manufacturing expertise for bipolar and IGBT products.Finally,multiple press-pack IGBT variants are currently undergoing evaluation tests prior to product release.展开更多
文摘The effects of source-drain underlaps on the performance of a top gate silicon nanowire on insulator transistor are studied using a three dimensional(3D) self-consistent Poisson-Schrodinger quantum simulation. Voltage-controlled tunnel barrier is the device transport physics. The off current, the on/off current ratio, and the inverse subthreshold slope are improved while the on current is degraded with underlap. The physics behind this behavior is the modulation of a tunnel barrier with underlap. The underlap primarily affects the tunneling component of drain current. About 50% contribution to the gate capacitance comes from the fringing electric fields emanating from the gate metal to the source and drain. The gate capacitance reduces with underlap, which should reduce the intrinsic switching delay and increase the intrinsic cut-off frequency. However, both the on current and the transconductance reduce with underlap, and the consequence is the increase of delay and the reduction of cut-off frequency.
基金Supported by the National Natural Science Foundation of China under Grant No 61574048the Science and Technology Research Project of Guangdong Province under Grant Nos 2015B090912002 and 2015B090901048the Pearl River S&T Nova Program of Guangzhou under Grant No 201710010172
文摘Low-frequency noise（LFN） in all operation regions of amorphous indium zinc oxide（a-IZO） thin film transistors（TFTs） with an aluminum oxide gate insulator is investigated. Based on the LFN measured results, we extract the distribution of localized states in the band gap and the spatial distribution of border traps in the gate dielectric,and study the dependence of measured noise on the characteristic temperature of localized states for a-IZO TFTs with Al2 O3 gate dielectric. Further study on the LFN measured results shows that the gate voltage dependent noise data closely obey the mobility fluctuation model, and the average Hooge＇s parameter is about 1.18×10^-3.Considering the relationship between the free carrier number and the field effect mobility, we simulate the LFN using the △N-△μ model, and the total trap density near the IZO/oxide interface is about 1.23×10^18 cm^-3eV^-1.
基金the Major Program of the National Natural Science Foundation of China(Grant No.2009ZX02305-006)the National Natural Science Foundation of China(Grant No.61076082)
文摘In this paper, a novel dual-gate and dielectric-inserted lateral trench insulated gate bipolar transistor （DGDI LTIGBT） structure, which features a double extended trench gate and a dielectric inserted in the drift region, is proposed and discussed. The device can not only decrease the specific on-resistance Ron,sp , but also simultaneously improve the temperature performance. Simulation results show that the proposed LTIGBT achieves an ultra-low on-state voltage drop of 1.31 V at 700 A·cm-2 with a small half-cell pitch of 10.5 μm, a specific on-resistance R on,sp of 187 mΩ·mm2, and a high breakdown voltage of 250 V. The on-state voltage drop of the DGDI LTIGBT is 18% less than that of the DI LTIGBT and 30.3% less than that of the conventional LTIGBT. The proposed LTIGBT exhibits a good positive temperature coefficient for safety paralleling to handling larger currents and enhances the short-circuit capability while maintaining a low self-heating effect. Furthermore, it also shows a better tradeoff between the specific on-resistance and the turnoff loss, although it has a longer turnoff delay time.
基金Projects supported by the National Natural Science Foundation of China (Grant No. 61176069)the State Key Laboratory of Electronic Thin Films and Integrated Devices,China (Grant No. CXJJ201004)the National Key Laboratory of Analog Integrated Circuit,China (Grant No. 9140C090304110C0905)
文摘A high voltage（〉 600 V） integrable silicon-on-insulator（SOI） trench-type lateral insulated gate bipolar transistor（LIGBT） with a reduced cell-pitch is proposed.The LIGBT features multiple trenches（MTs）：two oxide trenches in the drift region and a trench gate extended to the buried oxide（BOX）.Firstly,the oxide trenches enhance electric field strength because of the lower permittivity of oxide than that of Si.Secondly,oxide trenches bring in multi-directional depletion,leading to a reshaped electric field distribution and an enhanced reduced-surface electric-field（RESURF） effect.Both increase the breakdown voltage（BV）.Thirdly,oxide trenches fold the drift region around the oxide trenches,leading to a reduced cell-pitch.Finally,the oxide trenches enhance the conductivity modulation,resulting in a high electron/hole concentration in the drift region as well as a low forward voltage drop（Von）.The oxide trenches cause a low anode-cathode capacitance,which increases the switching speed and reduces the turn-off energy loss（Eoff）.The MT SOI LIGBT exhibits a BV of 603 V at a small cell-pitch of 24 μm,a Von of 1.03 V at 100 A/cm-2,a turn-off time of 250 ns and Eoff of 4.1×10？3 mJ.The trench gate extended to BOX synchronously acts as dielectric isolation between high voltage LIGBT and low voltage circuits,simplifying the fabrication processes.
基金Supported by the National Basic Research Program of China under Grant No 2012CB921703the National Natural Science Foundation of China under Grant Nos 11174357 and 11574379the Strategic Priority Research Program of Chinese Academy of Sciences under Grant No XDB07010300
文摘Low-frequency flicker noise is usually associated with material defects or imperfection of fabrication procedure. Up to now, there is only very limited knowledge about flicker noise of the topological insulator, whose topologically protected conducting surface is theoretically immune to back scattering. To suppress the bulk conductivity we synthesize antimony doped Bi2Se3 nanowires and conduct transport measurements at cryogenic temperatures. The low-frequency current noise measurement shows that the noise amplitude at the high-drain current regime can be described by Hooge＇s empirical relationship, while the noise level is significantly lower than that predicted by Hooge＇s model near the Dirac point. Furthermore, different frequency responses of noise power spectrum density for specific drain currents at the low drain current regime indicate the complex origin of noise sources of topological insulator.
基金The National Natural Science Foundation of China(No.61204083)the Natural Science Foundation of Jiangsu Province(No.BK2011059)the Program for New Century Excellent Talents in University(No.NCET-10-0331)
文摘A novel lateral insulated gate bipolar transistor on a silicon-on-insulator substrate SOI-LIGBT with a special low-doped P-well structure is proposed.The P-well structure is added to attach the P-body under the channel so as to reduce the linear anode current degradation without additional process.The influence of the length and depth of the P-well on the hot-carrier HC reliability of the SOI-LIGBT is studied.With the increase in the length of the P-well the perpendicular electric field peak and the impact ionization peak diminish resulting in the reduction of the hot-carrier degradation. In addition the impact ionization will be weakened with the increase in the depth of the P-well which also makes the hot-carrier degradation decrease.Considering the effect of the low-doped P-well and the process windows the length and depth of the P-well are both chosen as 2 μm.
文摘Effective thermal control systems are essential for the reliable working of insulated gate bipolar transistors （IGBTs） in many applications. A novel spray cooling loop system with integrated sintered porous copper wick （SCLS-SPC） is proposed to meet the requirements of higher device level heat fluxes and the harsh environments in some applications such as hybrid, fuel cell vehicles and aerospace. Fuzzy logic and proportional-integral-derivative （PID） policies are applied to adjust the electronic temperature within a safe working range. To evaluate the thermal control effect, a mathematical model of a 4-node thermal network and pump are established for predicting the dynamics of the SCLS-SPC. Moreover, the transient response of the 4 nodes and vapor mass flowrate under no control, PID and Fuzzy-PID are numerically investigated and discussed in detail.
基金Project supported by the National Science and Technology Major Project,China(Grant No.2011ZX02504-003)the Fundamental Research Funds for the Central Universities(Grant No.ZYGX2011J024)the Open Foundation of State Key Laboratory of Electronic Thin Films and Integrated Devices,China(Grant No.KFJJ201301)
文摘A novel high performance trench field stop （TFS） superjunction （S J） insulated gate bipolar transistor （IGBT） with a buried oxide （BO） layer is proposed in this paper. The BO layer inserted between the P-base and the SJ drift region acts as a barrier layer for the hole-carrier in the drift region. Therefore, conduction modulation in the emitter side of the SJ drift region is enhanced significantly and the carrier distribution in the drift region is optimized for the proposed structure. As a result, compared with the conventional TFS SJ IGBT （Conv-SJ）, the proposed BO-SJ IGBT structure possesses a drastically reduced on-state voltage drop （gce（on）） and an improved tradeoff between gee（on） and turn-off loss （Eoff）, with no breakdown voltage （BV） degraded. The results show that with the spacing between the gate and the BO layer Wo = 0.2 μm, the thickness of the BO layer Lo = 0.2 μm, the thickness of the drift region Ld = 90 μm, the half width and doping concentration of the N- and P-pillars Wn = Wp = 2.5μm and Nn = Np = 3 × 10^15 cm^-3, the Vce（on） and Eoff of the proposed structure are 1.08 V and 2.81 mJ/cm2 with the collector doping concentration Nc = 1 × 10^18 cm^-3 and 1.12 V and 1.73 mJ/cm2 with Nc = 5 × 10^17 cm^-3, respectively. However, with the same device parameters, the Vce（on） and Eoff for the Conv-SJ are 1.81 V and 2.88 mJ/cm2 with Nc= 1 × 10^18 cm^-3 and 1.98 V and 2.82 mJ/cm2 with Nc = 5 ×10^17 cm^-3, respectively. Meanwhile, the BV of the proposed structure and Conv-SJ are 1414 V and 1413 V, respectively.
基金Project supported by the National Natural Science Foundation of China(Grant Nos.61376080 and 61674027)the Natural Science Foundation of Guangdong Province,China(Grant Nos.2014A030313736 and 2016A030311022)
文摘A novel ultralow turnoff loss dual-gate silicon-on-insulator （SOI） lateral insulated gate bipolar transistor （LIGBT） is proposed. The proposed SOI LIGBT features an extra trench gate inserted between the p-well and n-drift, and an n-type carrier stored （CS） layer beneath the p-well. In the on-state, the extra trench gate acts as a barrier, which increases the cartier density at the cathode side of n-drift region, resulting in a decrease of the on-state voltage drop （Von）. In the off-state, due to the uniform carder distribution and the assisted depletion effect induced by the extra trench gate, large number of carriers can be removed at the initial turnoff process, contributing to a low turnoff loss （Eoff）. Moreover, owing to the dual-gate field plates and CS layer, the carrier density beneath the p-well can greatly increase, which further improves the tradeoff between Eoff and Von. Simulation results show that Eoff of the proposed SOI LIGBT can decrease by 77% compared with the conventional trench gate SOI LIGBT at the same Von of 1.1 V.
基金Project supported by the National Natural Science Foundation of China(Grant No.61404161)
文摘We present a detailed study of a superjunction （S J） nanoscale partially narrow mesa （PNM） insulated gate bipolar transistor （IGBT） structure. This structure is created by combining the nanoscale PNM structure and the SJ structure together. It demonstrates an ultra-low saturation voltage （Vce（sat）） and low turn-off loss （Eoff） while maintaining other device parameters. Compared with the conventional 1.2 kV trench IGBT, our simulation result shows that the gce（sat） of this structure decreases to 0.94 V, which is close to the theoretical limit of 1.2 kV IGBT, Meanwhile, the fall time decreases from 109.7 ns to 12 ns and the Eoff is down to only 37% of that of the conventional structure. The superior tradeoff characteristic between Vce（sat） and Eoff is presented owing to the nanometer level mesa width and SJ structure. Moreover, the short circuit degeneration phenomenon in the very narrow mesa structure due to the collector-induced barriers lowering （CIBL） effect is not observed in this structure. Thus, enough short circuit ability can be achieved by using wide, floating P-well technique. Based on these structure advantages, the SJ-PNM-IGBT with nanoscale mesa width indicates a potentially superior overall performance towards the IGBT parameter limit.
基金Project supported by the Hunan Provincial Natural Science Foundation of China(Grant No.2021JJ30738)Scientific Research Fund of Hunan Provincial Education Department(Grant No.19K001)Hunan Provincial Key Laboratory of Flexible Electronic Materials Genome Engineering’s Open Fund Project-2020(Grant No.202016)。
文摘A novel 4H-Si C trench insulated gate bipolar transistor(IGBT)with a controllable hole-extracting(CHE)path is proposed and investigated in this paper.The CHE path is controlled by metal semiconductor gate(MES gate)and metal oxide semiconductor gate(MOS gate)in the p-shield region.The grounded p-shield region can significantly suppress the high electric field around gate oxide in Si C devices,but it weakens the conductivity modulation in the Si C trench IGBT by rapidly sweeping out holes.This effect can be eliminated by introducing the CHE path.The CHE path is pinched off by the high gate bias voltage at on-state to maintain high conductivity modulation and obtain a comparatively low on-state voltage(VON).During the turn-off transient,the CHE path is formed,which contributes to a decreased turn-off loss(EOFF).Based on numerical simulation,the EOFFof the proposed IGBT is reduced by 89%compared with the conventional IGBT at the same VONand the VONof the proposed IGBT is reduced by 50%compared to the grounded p-shield IGBT at the same EOFF.In addition,the average power reduction for the proposed device can be 51.0%to 81.7%and 58.2%to 72.1%with its counterparts at a wide frequency range of 500 Hz to 10 k Hz,revealing a great improvement of frequency characteristics.
文摘Rotor chopper control is a simple and effective drive method for induction motor. This paper presents a novel IGBT chopper topology,which can both adjust rotor resistance and protect IGBT efficiently. Investigation on the quasi transient state of the rotor rectifying circuit is made, and a nonlinear mapping between the equivalent resistance and the duty cycle is deduced. Furthermore, the method for determining the magnitude of the external resistor is introduced.
文摘This paper introduces the Insulated gate bipolar transistor(IGBT)in- verter for arc welding.The principle of the inverter,the structure and charac- teristics of IGBT and the current feedback system using LEM current transduc- er are discussed.By the measurement of its efficiency and power factor and the tests of welding processes,the developed 150A IGBT inverter proves to be a kind of energy-saving portable power supply for arc welding with broad prospects.
基金Project supported by the National Basic Research Program of China(Grant No.2015CB351906)Science Foundation for Distinguished Young Scholars of Shaanxi Province,China(Grant No.2018JC-017)。
文摘A lateral insulated gate bipolar transistor(LIGBT)based on silicon-on-insulator(SOI)structure is proposed and investigated.This device features a compound dielectric buried layer(CDBL)and an assistant-depletion trench(ADT).The CDBL is employed to introduce two high electric field peaks that optimize the electric field distributions and that,under the same breakdown voltage(BV)condition,allow the CDBL to acquire a drift region of shorter length and a smaller number of stored carriers.Reducing their numbers helps in fast-switching.Furthermore,the ADT contributes to the rapid extraction of the stored carriers from the drift region as well as the formation of an additional heat-flow channel.The simulation results show that the BV of the proposed LIGBT is increased by 113%compared with the conventional SOI LIGBT of the same length L_(D).Contrastingly,the length of the drift region of the proposed device(11.2μm)is about one third that of a traditional device(33μm)with the same BV of 141 V.Therefore,the turn-off loss(E_(OFF))of the CDBL SOI LIGBT is decreased by 88.7%compared with a conventional SOI LIGBT when the forward voltage drop(VF)is 1.64 V.Moreover,the short-circuit failure time of the proposed device is 45%longer than that of the conventional SOI LIGBT.Therefor,the proposed CDBL SOI LIGBT exhibits a better V_(F)-E_(OFF)tradeoff and an improved short-circuit robustness.
基金Project supported in part by the Science Foundation for Distinguished Young Scholars of Shaanxi Province,China(Grant No.2018JC-017)111 Project(Grant No.B12026)。
文摘A novel silicon carbide gate-controlled bipolar field effect composite transistor with poly silicon region(SiC GCBTP)is proposed.Different from the traditional electrode connection mode of SiC vertical diffused MOS(VDMOS),the P+region of P-well is connected with the gate in SiC GCBTP,and the polysilicon region is added between the P+region and the gate.By this method,additional minority carriers can be injected into the drift region at on-state,and the distribution of minority carriers in the drift region will be optimized,so the on-state current is increased.In terms of static characteristics,it has the same high breakdown voltage(811 V)as SiC VDMOS whose length of drift is 5.5μm.The on-state current of SiC GCBTP is 2.47×10^(-3)A/μm(V_(G)=10 V,V_(D)=10 V)which is 5.7 times of that of SiC IGBT and 36.4 times of that of SiC VDMOS.In terms of dynamic characteristics,the turn-on time of SiC GCBTP is only 0.425 ns.And the turn-off time of SiC GCBTP is similar to that of SIC insulated gate bipolar transistor(IGBT),which is 114.72 ns.
基金Project supported by the Natural Science Foundation of Hunan Province, China (Grant No. 2023JJ40161)the Natural Science Foundation of Changsha, China (Grant No. kq2202163)+1 种基金the National Natural Science Foundation of China (Grant No. U21A20499)the Fundamental Research Funds for the Central Universities, China (Grant No. 531118010735)。
文摘A novel trench insulated gate bipolar transistor(IGBT) with improved dynamic characteristics is proposed and investigated. The poly gate and poly emitter of the proposed IGBT are arranged alternately along the trench. A self-biased p-MOSFET is formed on the emitter side. Owing to this unique three-dimensional(3D) trench architecture, both the turnoff characteristic and the turn-on characteristic can be greatly improved. At the turn-off moment, the maximum electric field and impact ionization rate of the proposed IGBT decrease and the dynamic avalanche(DA) is suppressed. Comparing with the carrier-stored trench gate bipolar transistor(CSTBT), the turn-off loss(E_(off)) of the proposed IGBT also decreases by 31% at the same ON-state voltage. At the turn-on moment, the built-in p-MOSFET reduces the reverse displacement current(I_(G_dis)), which is conducive to lowing dI_(C)/d_(t). As a result, compared with the CSTBT with the same turn-on loss(E_(on)), at I_(C) = 20 A/cm^(2), the proposed IGBT decreases by 35% of collector surge current(I_(surge)) and 52% of dI_(C)/d_(t).
基金Supported by the National Key Research and Development Plan Program(No.2022YFB4701101)National Natural Science Foundation of Chi-na(No.U1913211)Natural Science Foundation of Hebei Province of China(No.F2021202062)。
文摘With the widespread use of high-power and highly integrated insulated gate bipolar transistor(IGBT),their cooling methods have become challenging.This paper proposes a liquid cooling scheme for heavy-duty automated guided vehicle(AGV)motor driver in port environment,and improves heat dissipation by analyzing and optimizing the core component of finned heat sink.Firstly,the temperature distribution of the initial scheme is studied by using Fluent software,and the heat transfer characteristics of the finned heat sink are obtained through numerical analysis.Secondly,an orthogonal test is designed and combined with the response surface methodology to optimize the structural parameters of the finned heat sink,resulting in a 14.57%increase in the heat dissipation effect.Finally,the effectiveness of heat dissipation enhancement is verified.This work provides valuable insights into improving the heat dissipation of IGBT modules and heat sinks,and provides guidance for their future applications.
基金Project supported by the National Basic Research Program of China(Grant No.2014CB339900)the National Natural Science Foundation of China(Grant Nos.61376039,61334003,61574104,and 61474088)
文摘In this paper,ground-signal-ground type through-silicon vias（TSVs） exploiting air gaps as insulation layers are designed,analyzed and simulated for applications in millimeter wave.The compact wideband equivalent-circuit model and passive elements（RLGC） parameters based on the physical parameters are presented with the frequency up to 100 GHz.The parasitic capacitance of TSVs can be approximated as the dielectric capacitance of air gaps when the thickness of air gaps is greater than 0.75 μm.Therefore,the applied voltage of TSVs only needs to achieve the flatband voltage,and there is no need to indicate the threshold voltage.This is due to the small permittivity of air gaps.The proposed model shows good agreement with the simulation results of ADS and Ansoft＇s HFSS over a wide frequency range.
基金Project supported by Funds of Key Laboratory,China(Grant No.y7ys011001)Youth Innovation Promotion Association,Chinese Academy of Sciences(Grant No.y5yq01r002)
文摘In this study, we investigate the single-event transient（SET） characteristics of a partially depleted silicon-on-insulator（PDSOI） metal-oxide-semiconductor（MOS） device induced by a pulsed laser.We measure and analyze the drain transient current at the wafer level. The results indicate that the body-drain junction and its vicinity are more SET sensitive than the other regions in PD-SOI devices.We use ISE 3D simulation tools to analyze the SET response when different regions of the device are hit. Then, we discuss in detail the characteristics of transient currents and the electrostatic potential distribution change in devices after irradiation. Finally, we analyze the parasitic bipolar junction transistor（p-BJT） effect by performing both a laser test and simulations.
文摘The popularity of insulated gate bipolar transistors(IGBTs)for use in high-voltage direct current(HVDC)transmission and flexible AC transmission systems(FACTS)is increasing.Unfortunately,for these applications wire-bond IGBT technology has a number of shortcomings,such as insufficient current ratings for the most powerful schemes,and inability to fail to short-circuit.Press-pack IGBT technology,conversely,offers increased current ratings,and an inherent short-circuit failure mode,making it a more attractive choice for HVDC and FACTS.However,the design and manufacture of these devices requires a comprehensive understanding of the unique technical challenges,which differ markedly from those for wirebond modules or traditional pressure contact devices.Specific challenges include providing a high degree of mechanical protection for the IGBT chip against normal operating stresses.Furthermore,it is essential to achieve uniform contact pressure across each chip surface to ensure optimum performance.To achieve this,manufacturers have designed products that use rigid copper electrodes manufactured to tighter tolerances than for other pressure contact devices,such as thyristors,and products that use compliant electrodes,incorporating spring assemblies.Dynex is in the advanced stages of development of press-pack IGBT technology with demonstrated robust solutions for the technical challenges outlined in this paper.Design success has been achieved through the use of state-of-the-art simulations in conjunction with a long history of manufacturing expertise for bipolar and IGBT products.Finally,multiple press-pack IGBT variants are currently undergoing evaluation tests prior to product release.
