在复杂时钟结构芯片设计的物理实现中,基于Innovus工具采用传统时钟树综合流程得到的时钟树,具有时序违例大、插入缓冲器单元多、功耗大等问题,会给整个芯片设计带来挑战和困难。本文在传统时钟树流程基础上,采取在时钟树综合之前编写...在复杂时钟结构芯片设计的物理实现中,基于Innovus工具采用传统时钟树综合流程得到的时钟树,具有时序违例大、插入缓冲器单元多、功耗大等问题,会给整个芯片设计带来挑战和困难。本文在传统时钟树流程基础上,采取在时钟树综合之前编写一个时序约束文件来分段长时钟树的方法进行改进优化。与传统方法的结果相比,最终得到一个级数较低的高质量时钟树,该时钟树时序违例小,违例路径减少85条,插入的缓冲器数目减少了2676个。新方法能有效地降低了芯片的总功耗以及节省了大量的空间面积,解决了局部绕线阻塞问题,并提高了芯片的工作性能。In the physical implementation of complex clock structure chip design, the clock tree obtained based on the Innovus tool using the traditional clock tree synthesis process has problems such as large timing violations, many insertion buffer units, and large power consumption, which will bring challenges and difficulties to the entire chip design. Based on the traditional clock tree process, this paper adopts the method of writing a timing constraint file to segment the clock tree before the clock tree synthesis. Compared with the results of the traditional method, a high-quality clock tree with a low series is obtained, which has small timing violations, 85 fewer illegal paths, and 2676 buffers inserted. The new method can effectively reduce the total power consumption of the chip, save a lot of space area, solve the problem of local winding blockage, and improve the working performance of the chip.展开更多
随着当今电子行业的发展,对SoC芯片,尤其是数模混合芯片的要求越来越高。和传统的DEF/GDS数据交互方式相比,Mixed Signal Open Database(MSOA)RapidPDK可以帮助设计人员通过相同的PDK更好地完成数字工具Innovus和模拟工具Virtuoso之间...随着当今电子行业的发展,对SoC芯片,尤其是数模混合芯片的要求越来越高。和传统的DEF/GDS数据交互方式相比,Mixed Signal Open Database(MSOA)RapidPDK可以帮助设计人员通过相同的PDK更好地完成数字工具Innovus和模拟工具Virtuoso之间的数据传递。首先描述了5 nm MSOA RapidPDK生成方式,其次使用生成的PDK实现5 nm IP物理实现,同时验证MSOA flow对5 nm设计在版图完成和交付方面的速率提升。展开更多
文摘近年来,随着人工智能技术开始广泛应用,大规模和超大规模逻辑复杂的人工智能(Artificial Intelligence)芯片设计需求日渐增加,后端物理实现在布局布线方面的挑战也随之而来。由于复杂的数据交互给传统的后端宏单元布局规划工作带来很大的挑战。在宏单元的摆放,绕线阻塞的评估和低功耗的实现等方面的难度越来越大,需要增加迭代次数来寻求最优方案,从而需要较长的设计周期。为了满足市场应用的需求,如何提高设计效率就成为AI芯片设计的一个重要课题。本文主要介绍基于Cadence新一代布局布线工具Innovus平台,为了实现高标准的PPA(Power Performance Area),引入新的方法学—混合摆放(Mix-Place),并提出了一套快速布局规划(Floorplan),兼顾时序的压降优化(Timing Aware IR Drop Eco)和光刻坏点修复(Fix Litho Hotspot)相结合的一体化完整解决方案。采用先进的FinFet工艺,完成了Enflame自主研发的云端训练AI芯片设计后端物理实现的快速迭代工作。在保证时序收敛的基础上,降低功耗,提高面积的利用率和绕线的可预测性,有效地缩短了设计周期,完成投片,并推进产品的更新换代。
文摘在复杂时钟结构芯片设计的物理实现中,基于Innovus工具采用传统时钟树综合流程得到的时钟树,具有时序违例大、插入缓冲器单元多、功耗大等问题,会给整个芯片设计带来挑战和困难。本文在传统时钟树流程基础上,采取在时钟树综合之前编写一个时序约束文件来分段长时钟树的方法进行改进优化。与传统方法的结果相比,最终得到一个级数较低的高质量时钟树,该时钟树时序违例小,违例路径减少85条,插入的缓冲器数目减少了2676个。新方法能有效地降低了芯片的总功耗以及节省了大量的空间面积,解决了局部绕线阻塞问题,并提高了芯片的工作性能。In the physical implementation of complex clock structure chip design, the clock tree obtained based on the Innovus tool using the traditional clock tree synthesis process has problems such as large timing violations, many insertion buffer units, and large power consumption, which will bring challenges and difficulties to the entire chip design. Based on the traditional clock tree process, this paper adopts the method of writing a timing constraint file to segment the clock tree before the clock tree synthesis. Compared with the results of the traditional method, a high-quality clock tree with a low series is obtained, which has small timing violations, 85 fewer illegal paths, and 2676 buffers inserted. The new method can effectively reduce the total power consumption of the chip, save a lot of space area, solve the problem of local winding blockage, and improve the working performance of the chip.
