A low jitter All-Digital Phase-Locked Loop （ADPLL） used as a clock generator is designed. The Digital-Controlled Oscillator （DCO） for this ADPLL is a seven-stage ring oscillator with the delay of each stage change...A low jitter All-Digital Phase-Locked Loop （ADPLL） used as a clock generator is designed. The Digital-Controlled Oscillator （DCO） for this ADPLL is a seven-stage ring oscillator with the delay of each stage changeable. Based on the Impulse Sensitivity Function （ISF） analysis, an effective way is proposed to reduce the ADPLL＇s jitter by the careful design of the sizes of the inverters used in the DCO with a simple architecture other than a complex one. The ADPLL is implemented in a 0.18μm CMOS process with 1.SV supply voltage, occupies 0.046mm^2 of on-chip area. According to the measured results, the ADPLL can operate from 108MHz to 304MHz, and the peak-to-peak jitter is 139ps when the DCO＇s output frequency is 188MHz.展开更多
A Colpitts oscillator, working around a 3 GHz frequency, contains a double gate Metal Oxide Semiconductor transistor (DGMOS). A mixed-mode analysis is involved, applying a quantum model to the device, whereas the rest...A Colpitts oscillator, working around a 3 GHz frequency, contains a double gate Metal Oxide Semiconductor transistor (DGMOS). A mixed-mode analysis is involved, applying a quantum model to the device, whereas the rest of the considered circuit is governed by Kirchhoff’s laws. The Linear Time Variant (LTV) model of phase noise is based on the Impulse Sensitivity Function of the Colpitts Oscillator which describes carefully the sensitivity of an oscillator to any impulse current injection in any node of the circuit. Finally, we improve the phase noise modeling, confronting some analytical developments to mixed-mode simulations.展开更多
文摘A low jitter All-Digital Phase-Locked Loop （ADPLL） used as a clock generator is designed. The Digital-Controlled Oscillator （DCO） for this ADPLL is a seven-stage ring oscillator with the delay of each stage changeable. Based on the Impulse Sensitivity Function （ISF） analysis, an effective way is proposed to reduce the ADPLL＇s jitter by the careful design of the sizes of the inverters used in the DCO with a simple architecture other than a complex one. The ADPLL is implemented in a 0.18μm CMOS process with 1.SV supply voltage, occupies 0.046mm^2 of on-chip area. According to the measured results, the ADPLL can operate from 108MHz to 304MHz, and the peak-to-peak jitter is 139ps when the DCO＇s output frequency is 188MHz.
文摘A Colpitts oscillator, working around a 3 GHz frequency, contains a double gate Metal Oxide Semiconductor transistor (DGMOS). A mixed-mode analysis is involved, applying a quantum model to the device, whereas the rest of the considered circuit is governed by Kirchhoff’s laws. The Linear Time Variant (LTV) model of phase noise is based on the Impulse Sensitivity Function of the Colpitts Oscillator which describes carefully the sensitivity of an oscillator to any impulse current injection in any node of the circuit. Finally, we improve the phase noise modeling, confronting some analytical developments to mixed-mode simulations.
