本文设计的IEEE 1394事物层接口连接了PLB(Processor Local Bus)总线和1394链路层模块,主要实现1394事物层模块数据的发送和接收.首先对事物层接口进行系统结构设计,然后对PLB从接口、FIFO接口和主机访问寄存器接口这3个子模块分别进行...本文设计的IEEE 1394事物层接口连接了PLB(Processor Local Bus)总线和1394链路层模块,主要实现1394事物层模块数据的发送和接收.首先对事物层接口进行系统结构设计,然后对PLB从接口、FIFO接口和主机访问寄存器接口这3个子模块分别进行逻辑设计,最后采用硬件描述语言对设计进行可综合描述,并使用软件QuestaSim进行仿真验证.该设计使事务层能够跨时钟域同链路层进行数据包的传输,并进行有效的数据位宽转换,提高传输效率.经过仿真验证,结果满足设计要求,表明IEEE 1394事物层接口能够正常发送和接收等时及异步数据包.展开更多
This paper presents the implementation of a multi-rate SerDes transceiver for IEEE 1394b applications. Simple and effective pre-emphasis and equalizer circuits are used in the transmitter and receiver, respectively. A...This paper presents the implementation of a multi-rate SerDes transceiver for IEEE 1394b applications. Simple and effective pre-emphasis and equalizer circuits are used in the transmitter and receiver, respectively. A phase interpolator based clock and data recovery circuit with optimized linearity is also described. With an on-chip fully integrated phase locked loop, the transceiver works at data rates of 100 Mb/s, 400 Mb/s, and 800 Mb/s, supporting three different operating modes of S100b, S400b, and S800b for IEEE 1394b. The chip has been fabricated using 0.13 μm technology. The die area of transceiver is 2.9×1.6 mm2^ including bonding pads and the total power dissipation is 284 mW with 1.2 V core supply and 3.3 V input/output supply voltages.展开更多
文摘本文设计的IEEE 1394事物层接口连接了PLB(Processor Local Bus)总线和1394链路层模块,主要实现1394事物层模块数据的发送和接收.首先对事物层接口进行系统结构设计,然后对PLB从接口、FIFO接口和主机访问寄存器接口这3个子模块分别进行逻辑设计,最后采用硬件描述语言对设计进行可综合描述,并使用软件QuestaSim进行仿真验证.该设计使事务层能够跨时钟域同链路层进行数据包的传输,并进行有效的数据位宽转换,提高传输效率.经过仿真验证,结果满足设计要求,表明IEEE 1394事物层接口能够正常发送和接收等时及异步数据包.
基金supported by the National Natural Science Foundation of China under Grant No. 61006027the New Century Excellent Talents Program under Grant No. NCET-10-0297
文摘This paper presents the implementation of a multi-rate SerDes transceiver for IEEE 1394b applications. Simple and effective pre-emphasis and equalizer circuits are used in the transmitter and receiver, respectively. A phase interpolator based clock and data recovery circuit with optimized linearity is also described. With an on-chip fully integrated phase locked loop, the transceiver works at data rates of 100 Mb/s, 400 Mb/s, and 800 Mb/s, supporting three different operating modes of S100b, S400b, and S800b for IEEE 1394b. The chip has been fabricated using 0.13 μm technology. The die area of transceiver is 2.9×1.6 mm2^ including bonding pads and the total power dissipation is 284 mW with 1.2 V core supply and 3.3 V input/output supply voltages.
