A 4H-SiC superjunction(SJ)MOSFET(SJMOS)with integrated high-K gate dielectric and split gate(HKSG-SJMOS)is proposed in this paper.The key features of HKSG-SJMOS involve the utilization of high-K(HK)dielectric as the g...A 4H-SiC superjunction(SJ)MOSFET(SJMOS)with integrated high-K gate dielectric and split gate(HKSG-SJMOS)is proposed in this paper.The key features of HKSG-SJMOS involve the utilization of high-K(HK)dielectric as the gate dielectric,which surrounds the source-connected split gate(SG)and metal gate.The high-K gate dielectric optimizes the electric field distribution within the drift region,creating a low-resistance conductive channel.This enhancement leads to an increase in the breakdown voltage(BV)and a reduction in the specific on resistance(R_(on,sp)).The introduction of split gate surrounded by high-K dielectric reduces the gate-drain capacitance(C_(gd))and gate-drain charge(Q_(gd)),which improves the switching characteristics.The simulation results indicate that compared to conventional 4H-SiC SJMOS,the HKSG-SJMOS exhibits a 110.5%enhancement in figure of merit(FOM,FOM=BV^(2)/R_(on,sp)),a 93.6%reduction in the high frequency figure of merit(HFFOM)of R_(on,sp)·C_(gd),and reductions in turn-on loss(E_(on))and turn-off loss(E_(off))by 38.3%and 31.6%,respectively.Furthermore,the reverse recovery characteristics of HKSG-SJMOS has also discussed,revealing superior performance compared to conventional 4H-SiC SJMOS.展开更多
Combining two-dimensional materials and high-k gate dielectrics offers a promising way to enhance the device performance of tunneling field-effect transistor(TFET).In this work,the device performance of WSe_(2)/SnSe_(...Combining two-dimensional materials and high-k gate dielectrics offers a promising way to enhance the device performance of tunneling field-effect transistor(TFET).In this work,the device performance of WSe_(2)/SnSe_(2)TFET with various gate dielectric materials is investigated based on quantum transport sim-ulation.Results show that TFETs with high-k gate dielectric materials exhibit improved on-offratio and enhanced transconductance.The optimized WSe_(2)/SnSe_(2)TFET with TiO_(2)gate dielectrics achieves an on-state current of 1560μA/μm and a subthreshold swing(SS)of 48 mV/dec.The utilization of high-k gate dielectric materials results in shorter tunneling length,higher transmission efficiency,and increased elec-tron tunneling probability.The performance of the WSe_(2)/SnSe_(2)TFET would be affected by the presence of the underlap region.Moreover,WSe_(2)/SnSe_(2)TFETs with La_(2)O_(3)dielectric can be scaled down to 3 nm while meeting high-performance(HP)device requirements according to the International Technology Roadmap for Semiconductors(ITRS).This research presents a practical solution for designing advanced logic devices in the sub-5 nm technology node.展开更多
A new 2-Π lumped element equivalent circuit model for high-k stacked on-chip transformers is proposed. The model parameters are extracted with high precision, mainly based on analytical methods. The developed model e...A new 2-Π lumped element equivalent circuit model for high-k stacked on-chip transformers is proposed. The model parameters are extracted with high precision, mainly based on analytical methods. The developed model enables fast and accurate time domain transient analysis and noise analysis in RFIC simulation since all elements in the model are fre- quency independent. The validity of the proposed model has been demonstrated by a fabricated monolithic stacked trans- former in TSMC＇s 0.13μm mixed-signal （MS）/RF CMOS＇ process.展开更多
The key technologies for the dual high-k and dual metal gate, such as the electrical optimization of metal insert poly-Si stack structure, the separating of high-k and metal gate of n/pMOS in different regions of the ...The key technologies for the dual high-k and dual metal gate, such as the electrical optimization of metal insert poly-Si stack structure, the separating of high-k and metal gate of n/pMOS in different regions of the wafer, and the synchronous etching of n/pMOS gate stack, are successfully developed. First, reasonable flat-band voltage and equivalent oxide thickness of pMOS MIPS structure are obtained by further optimizing the HfSiAlON dielectric through incorporating more Al-O dipole at interface between HfSiAlON and bottom SiOx. Then, the separating of high-k and metal gate for n/pMOS is achieved by SC1（NH4OH：H2O2：H2O = 1 ： 1 ： 5） and DHF-based solution for the selective removing of n MOS TaN and Hf Si ON and by BCl3-based plasma and DHF-based solution for the selective removing of pMOS TaN/Mo and HfSiAlON.After that, the synchronous etching of n/pMOS gate stack is developed by utilizing optimized BCl3/SF6/O2/Ar plasma to obtain a vertical profile for TaN and TaN/Mo and by utilizing BCl3/Ar plasma combined with DHF-based solution to achieve high selectivity to Si substrate. Finally, good electrical characteristics of CMOS devices, obtained by utilizing these new developed technologies, further confirm that they are practicable technologies for DHDMG integration.展开更多
This paper presents a new silicon-on-insulator(SOI) lateral-double-diffused metal-oxide-semiconductor transistor(LDMOST) device with alternated high-k dielectric and step doped silicon pillars(HKSD device). Due to the...This paper presents a new silicon-on-insulator(SOI) lateral-double-diffused metal-oxide-semiconductor transistor(LDMOST) device with alternated high-k dielectric and step doped silicon pillars(HKSD device). Due to the modulation of step doping technology and high-k dielectric on the electric field and doped profile of each zone, the HKSD device shows a greater performance. The analytical models of the potential, electric field, optimal breakdown voltage, and optimal doped profile are derived. The analytical results and the simulated results are basically consistent, which confirms the proposed model suitable for the HKSD device. The potential and electric field modulation mechanism are investigated based on the simulation and analytical models. Furthermore, the influence of the parameters on the breakdown voltage(BV) and specific on-resistance(R_(on,sp)) are obtained. The results indicate that the HKSD device has a higher BV and lower R_(on,sp) compared to the SD device and HK device.展开更多
The Langdu high-K calc-alkaline intrusions are located in the Zhongdian area, which is the southern part of the Yidun island arc. These intrusive rocks consist mainly of monzonite porphyry, granodiorite, and diorite p...The Langdu high-K calc-alkaline intrusions are located in the Zhongdian area, which is the southern part of the Yidun island arc. These intrusive rocks consist mainly of monzonite porphyry, granodiorite, and diorite porphyry. The K20 content of majority of these rocks is greater than 3%, and, in the K20-SiO2 diagram, all the samples fall into the high-K calc-alkaline to shoshonitic fields. They are enriched in light rare earth elements （LREEs） and depleted in heavy rare earth elements （HREEs; LaN/YbN = 14.3-21.2）, and show slightly negative Eu anomalies （6Eu = 0.77-1.00）. These rocks have high K, Rb, Sr, and Ba contents; moderate to high enrichment of compatible elements （Cr = 36.7-79.9 ppm, Co = 9.6-16.4 ppm, and MgO = 2.2%-3.4%）; low Nb, Ta, and Ti contents, and characteristic of low high field strength elements（HFSEs） versus incompatible elements ratios （Nb/Th = 0.75, Nb/La = 0.34） and incompatible elements ratios （Nb/U = 3.0 and Ce/Pb = 5.1, Ba/Rb = 12.0）. These rocks exhibit restricted Sr and Nd isotopic compositions, with （87Sr/S6Sr）i values ranging from 0.7044 to 0.7069 and ENd（t） values from -2.8 to -2.2. The Sr-Nd isotope systematic and specific trace element ratios suggest that Langdu high-K calc-alkaline intrusive rocks derived from a metasomatized mantle source. The unique geochemical feature of intrusive rocks can be modeled successfully using different members of a slightly enriched mantle, a slab-derived fluid, and terrigenous sediments. It can be inferred that the degree of partial melting and the presence of specific components are temporally related to the tectonic evolution of the Zhongdian island arc. Formation of these rocks can be explained by the various degrees of melting within an ascending region of the slightly enriched mantle, triggered by the subduction of the Garz^--Litang ocean, and an interaction between the slab-derived fluid and the terrigenous sediments.展开更多
A new SiC superjunction power MOSFET device using high-k insulator and p-type pillar with an integrated Schottky barrier diode(Hk-SJ-SBD MOSFET)is proposed,and has been compared with the SiC high-k MOSFET(Hk MOSFET),S...A new SiC superjunction power MOSFET device using high-k insulator and p-type pillar with an integrated Schottky barrier diode(Hk-SJ-SBD MOSFET)is proposed,and has been compared with the SiC high-k MOSFET(Hk MOSFET),SiC superjuction MOSFET(SJ MOSFET)and the conventional SiC MOSFET in this article.In the proposed SiC Hk-SJ-SBD MOSFET,under the combined action of the p-type region and the Hk dielectric layer in the drift region,the concentration of the N-drift region and the current spreading layer can be increased to achieve an ultra-low specific on-resistance(Ron,sp).The integrated Schottky barrier diode(SBD)also greatly improves the reverse recovery performance of the device.TCAD simulation results indicate that the Ron,sp of the proposed SiC Hk-SJ-SBD MOSFET is 0.67 mΩ·cm^(2)with a 2240 V breakdown voltage(BV),which is more than 72.4%,23%,5.6%lower than that of the conventional SiC MOSFET,Hk SiC MOSFET and SJ SiC MOSFET with the 1950,2220,and 2220V BV,respectively.The reverse recovery time and reverse recovery charge of the proposed MOSFET is 16 ns and18 nC,which are greatly reduced by more than 74%and 94%in comparison with those of all the conventional SiC MOSFET,Hk SiC MOSFET and SJ SiC MOSFET,due to the integrated SBD in the proposed MOSFET.And the trade-off relationship between the Ron,sp and the BV is also significantly improved compared with that of the conventional MOSFET,Hk MOSFET and SJ MOSFET as well as the MOSFETs in other previous literature,respectively.In addition,compared with conventional SJ SiC MOSFET,the proposed SiC MOSFET has better immunity to charge imbalance,which may bring great application prospects.展开更多
This paper reports that the high-K HfO2 gate dielectrics are fabricated on n-germanium substrates by sputtering Hf on Ge and following by a furnace annealing. The impacts of sputtering ambient, annealing ambient and a...This paper reports that the high-K HfO2 gate dielectrics are fabricated on n-germanium substrates by sputtering Hf on Ge and following by a furnace annealing. The impacts of sputtering ambient, annealing ambient and annealing temperature on the electrical properties of high-K HfO2 gate dielectrics on germanium substrates are investigated. Experimental results indicate that high-K HfO2 gate dielectrics on germanium substrates with good electrical characteristics are obtained, the electrical properties of high-K HfO2 gate dielectrics is strongly correlated with sputtering ambient, annealing ambient and annealing temperature.展开更多
A novel trench MOS barrier Schottky diode（TMBS） device with a high-k material introduced into the gate insulator is reported, which is named high-k TMBS. By simulation with Medici, it is found that the high-k TMBS c...A novel trench MOS barrier Schottky diode（TMBS） device with a high-k material introduced into the gate insulator is reported, which is named high-k TMBS. By simulation with Medici, it is found that the high-k TMBS can have 19.8% lower leakage current while maintaining the same breakdown voltage and forward turn-on voltage compared with the conventional regular trench TMBS.展开更多
A physical model for mobility degradation by interface-roughness scattering and Coulomb scattering is proposed for SiGe p-MOSFET with a high-k dielectric/SiO2 gate stack. Impacts of the two kinds of scatterings on mob...A physical model for mobility degradation by interface-roughness scattering and Coulomb scattering is proposed for SiGe p-MOSFET with a high-k dielectric/SiO2 gate stack. Impacts of the two kinds of scatterings on mobility degradation are investigated. Effects of interlayer （SiO2） thickness and permittivities of the high-k dielectric and interlayer on carrier mobility are also discussed. It is shown that a smooth interface between high-k dielectric and interlayer, as well as moderate permittivities of high-k dielectrics, is highly desired to improve carriers mobility while keeping alow equivalent oxide thickness. Simulated results agree reasonably with experimental data.展开更多
The decreasing feature sizes in complementary metal-oxide semiconductor （CMOS） transistor technology will require the replacement of SiO2 with gate dielectrics that have a high dielectric constant （high-k） because...The decreasing feature sizes in complementary metal-oxide semiconductor （CMOS） transistor technology will require the replacement of SiO2 with gate dielectrics that have a high dielectric constant （high-k） because as the SiO2 gate thickness is reduced below 1.4 nm, electron tunnelling effects and high leakage currents occur in SiO2, which present serious obstacles to future device reliability. In recent years significant progress has been made on the screening and selection of high-k gate dielectrics, understanding their physical properties, and their integration into CMOS technology. Now the family of hafnium oxide-based materials has emerged as the leading candidate for high-k gate dielectrics due to their excellent physical properties. It is also realized that the high-k oxides must be implemented in conjunction with metal gate electrodes to get sufficient potential for CMOS continue scaling. In the advanced nanoscale Si-based CMOS devices, the composition and thickness of interfacial layers in the gate stacks determine the critical performance of devices. Therefore, detailed atomic- scale understandings of the microstructures and interfacial structures built in the advanced CMOS gate stacks, are highly required. In this paper, several high-resolution electron, ion, and photon-based techniques currently used to characterize the high-k gate dielectrics and interfaces at atomic-scale, are reviewed. Particularly, we critically review the research progress on the characterization of interface behavior and structural evolution in the high-k gate dielectrics by high-resolution transmission electron microscopy （HRTEM） and the related techniques based on scanning transmission electron microscopy （STEM）, including high-angle annular dark- field （HAADF） imaging （also known as Z-contrast imaging）, electron energy-loss spectroscopy （EELS）, and energy dispersive X-ray spectroscopy （EDS）, due to that HRTEM and STEM have become essential metrology tools for characterizing the dielectric gate stacks in the present and future generations of CMOS devices. In Section 1 of this review, the working principles of each technique are briefly introduced and their key features are outlined. In Section 2, microstructural characterizations of high-k gate dielectrics at atomic-scale by electron microscopy are critically reviewed by citing some recent results reported on high-k gate dielectrics. In Section 3, metal gate electrodes and the interfacial structures between high-k dielectrics and metal gates are discussed. The electron beam damage effects in high-k gate stacks are also evaluated, and their origins and prevention are described in Section 4. Finally, we end this review with personal perspectives towards the future challenges of atomic-scale material characterization in advanced CMOS gate stacks.展开更多
With the continued downscaling of complementary metal-oxide-semiconductor field effect transistor dimensions, high-dielectric constant （high-k） gate materials, as alternatives to SiO2, have been extensively investig...With the continued downscaling of complementary metal-oxide-semiconductor field effect transistor dimensions, high-dielectric constant （high-k） gate materials, as alternatives to SiO2, have been extensively investigated. Hf （Zr）-based high-k gate dielectric thin films have been regarded as the most promising candidates for high-k gate dielectric according to the International Technology Roadmap for Semiconductor due to their excellent physical properties and performance. This paper reviews the recent progress on Hf （Zr）-based high-k gate dielectrics based on PVD （physical vapor deposition） process. This article begins with a survey of various methods developed for generating Hf （Zr）-based high-k gate dielectrics, and then mainly focuses on microstructure, synthesis, characterization, formation mechanisms of interfacial layer, and optical properties of Hf （Zr）-based high-k gate dielectrics. Finally, this review concludes with personal perspectives towards future research on Hf （Zr）-based high-k gate dielectrics.展开更多
In this paper the influences of the metal-gate and high-k/SiO 2 /Si stacked structure on the metal-oxide-semiconductor field-effect transistor（MOSFET） are investigated.The flat-band voltage is revised by considering...In this paper the influences of the metal-gate and high-k/SiO 2 /Si stacked structure on the metal-oxide-semiconductor field-effect transistor（MOSFET） are investigated.The flat-band voltage is revised by considering the influences of stacked structure and metal-semiconductor work function fluctuation.The two-dimensional Poisson＇s equation of potential distribution is presented.A threshold voltage analytical model for metal-gate/high-k/SiO 2 /Si stacked MOSFETs is developed by solving these Poisson＇s equations using the boundary conditions.The model is verified by a two-dimensional device simulator,which provides the basic design guidance for metal-gate/high-k/SiO 2 /Si stacked MOSFETs.展开更多
NH3-plasma treatment is used to improve the quality of the gate dielectric and interface. Al2O3 is adopted as a buffer layer between HfO2 and MoS2 to decrease the interface-state density. Four groups of MOS capacitors...NH3-plasma treatment is used to improve the quality of the gate dielectric and interface. Al2O3 is adopted as a buffer layer between HfO2 and MoS2 to decrease the interface-state density. Four groups of MOS capacitors and back-gate transistors with different gate dielectrics are fabricated and their C–V and I–V characteristics are compared. It is found that the Al2O3/HfO2 back-gate transistor with NH3-plasma treatment shows the best electrical performance: high on–off current ratio of 1.53 × 107, higher field-effect mobility of 26.51 cm2/V·s, and lower subthreshold swing of 145 m V/dec.These are attributed to the improvements of the gate dielectric and interface qualities by the NH3-plasma treatment and the addition of Al2O3 as a buffer layer.展开更多
High-k metal gate stacks are being used to suppress the gate leakage due to tunneling for sub-45 nm technology nodes.The reliability of thin dielectric films becomes a limitation to device manufacturing,especially to ...High-k metal gate stacks are being used to suppress the gate leakage due to tunneling for sub-45 nm technology nodes.The reliability of thin dielectric films becomes a limitation to device manufacturing,especially to the breakdown characteristic.In this work,a breakdown simulator based on a percolation model and the kinetic Monte Carlo method is set up,and the intrinsic relation between time to breakdown and trap generation rate R is studied by TDDB simulation.It is found that all degradation factors,such as trap generation rate time exponent m,Weibull slope β and percolation factor s,each could be expressed as a function of trap density time exponent α.Based on the percolation relation and power law lifetime projection,a temperature related trap generation model is proposed.The validity of this model is confirmed by comparing with experiment results.For other device and material conditions,the percolation relation provides a new way to study the relationship between trap generation and lifetime projection.展开更多
In this work, an in-situ ozone treatment is carried out to improve the interface thermal stability of HfO_2/Al_2O_3 gate stack on germanium（Ge） substrate. The micrometer scale level of HfO_2/Al_2O_3 gate stack on Ge...In this work, an in-situ ozone treatment is carried out to improve the interface thermal stability of HfO_2/Al_2O_3 gate stack on germanium（Ge） substrate. The micrometer scale level of HfO_2/Al_2O_3 gate stack on Ge is studied using conductive atomic force microscopy（AFM） with a conductive tip. The initial results indicate that comparing with a non insitu ozone treated sample, the interface thermal stability of the sample with an in-situ ozone treatment can be substantially improved after annealing. As a result, void-free surface, low conductive spots, low leakage current density, and relative high breakdown voltage high-κ/Ge are obtained. A detailed analysis is performed to confirm the origins of the changes.All results indicate that in-situ ozone treatment is a promising method to improve the interface properties of Ge-based three-dimensional（3D） devices in future technology nodes.展开更多
基金supported by the National Natural Science Foundation of China(Grant Nos.62074080 and U23B2042)in part by the Natural Science Foundation of Jiangsu Province(Grant No.BK20211104)in part by the Jiangsu Provincial Key Research and Development Program(Grant No.BE2022126)。
文摘A 4H-SiC superjunction(SJ)MOSFET(SJMOS)with integrated high-K gate dielectric and split gate(HKSG-SJMOS)is proposed in this paper.The key features of HKSG-SJMOS involve the utilization of high-K(HK)dielectric as the gate dielectric,which surrounds the source-connected split gate(SG)and metal gate.The high-K gate dielectric optimizes the electric field distribution within the drift region,creating a low-resistance conductive channel.This enhancement leads to an increase in the breakdown voltage(BV)and a reduction in the specific on resistance(R_(on,sp)).The introduction of split gate surrounded by high-K dielectric reduces the gate-drain capacitance(C_(gd))and gate-drain charge(Q_(gd)),which improves the switching characteristics.The simulation results indicate that compared to conventional 4H-SiC SJMOS,the HKSG-SJMOS exhibits a 110.5%enhancement in figure of merit(FOM,FOM=BV^(2)/R_(on,sp)),a 93.6%reduction in the high frequency figure of merit(HFFOM)of R_(on,sp)·C_(gd),and reductions in turn-on loss(E_(on))and turn-off loss(E_(off))by 38.3%and 31.6%,respectively.Furthermore,the reverse recovery characteristics of HKSG-SJMOS has also discussed,revealing superior performance compared to conventional 4H-SiC SJMOS.
基金supported by the National Natural Science Foun-dation of China(Grant Nos.62174122 and U2241244)the Fun-damental Research Funds for the Central Universities(Grant No.2042023kf0116)+1 种基金the Science and Technology Project of China Southern Power Grid Co.,Ltd.(Grant No.GXKJXM20220095)the Hubei Key Laboratory of Electronic Manufacturing and Pack-aging Integration of Wuhan University(Grant No.EMPI2023016)。
文摘Combining two-dimensional materials and high-k gate dielectrics offers a promising way to enhance the device performance of tunneling field-effect transistor(TFET).In this work,the device performance of WSe_(2)/SnSe_(2)TFET with various gate dielectric materials is investigated based on quantum transport sim-ulation.Results show that TFETs with high-k gate dielectric materials exhibit improved on-offratio and enhanced transconductance.The optimized WSe_(2)/SnSe_(2)TFET with TiO_(2)gate dielectrics achieves an on-state current of 1560μA/μm and a subthreshold swing(SS)of 48 mV/dec.The utilization of high-k gate dielectric materials results in shorter tunneling length,higher transmission efficiency,and increased elec-tron tunneling probability.The performance of the WSe_(2)/SnSe_(2)TFET would be affected by the presence of the underlap region.Moreover,WSe_(2)/SnSe_(2)TFETs with La_(2)O_(3)dielectric can be scaled down to 3 nm while meeting high-performance(HP)device requirements according to the International Technology Roadmap for Semiconductors(ITRS).This research presents a practical solution for designing advanced logic devices in the sub-5 nm technology node.
文摘A new 2-Π lumped element equivalent circuit model for high-k stacked on-chip transformers is proposed. The model parameters are extracted with high precision, mainly based on analytical methods. The developed model enables fast and accurate time domain transient analysis and noise analysis in RFIC simulation since all elements in the model are fre- quency independent. The validity of the proposed model has been demonstrated by a fabricated monolithic stacked trans- former in TSMC＇s 0.13μm mixed-signal （MS）/RF CMOS＇ process.
基金Project supported by the National High Technology Research and Development Program of China(Grant No.2015AA010601)
文摘The key technologies for the dual high-k and dual metal gate, such as the electrical optimization of metal insert poly-Si stack structure, the separating of high-k and metal gate of n/pMOS in different regions of the wafer, and the synchronous etching of n/pMOS gate stack, are successfully developed. First, reasonable flat-band voltage and equivalent oxide thickness of pMOS MIPS structure are obtained by further optimizing the HfSiAlON dielectric through incorporating more Al-O dipole at interface between HfSiAlON and bottom SiOx. Then, the separating of high-k and metal gate for n/pMOS is achieved by SC1（NH4OH：H2O2：H2O = 1 ： 1 ： 5） and DHF-based solution for the selective removing of n MOS TaN and Hf Si ON and by BCl3-based plasma and DHF-based solution for the selective removing of pMOS TaN/Mo and HfSiAlON.After that, the synchronous etching of n/pMOS gate stack is developed by utilizing optimized BCl3/SF6/O2/Ar plasma to obtain a vertical profile for TaN and TaN/Mo and by utilizing BCl3/Ar plasma combined with DHF-based solution to achieve high selectivity to Si substrate. Finally, good electrical characteristics of CMOS devices, obtained by utilizing these new developed technologies, further confirm that they are practicable technologies for DHDMG integration.
基金Project supported by the National Natural Science Foundation of China(Grant Nos.61704084 and 61874059)。
文摘This paper presents a new silicon-on-insulator(SOI) lateral-double-diffused metal-oxide-semiconductor transistor(LDMOST) device with alternated high-k dielectric and step doped silicon pillars(HKSD device). Due to the modulation of step doping technology and high-k dielectric on the electric field and doped profile of each zone, the HKSD device shows a greater performance. The analytical models of the potential, electric field, optimal breakdown voltage, and optimal doped profile are derived. The analytical results and the simulated results are basically consistent, which confirms the proposed model suitable for the HKSD device. The potential and electric field modulation mechanism are investigated based on the simulation and analytical models. Furthermore, the influence of the parameters on the breakdown voltage(BV) and specific on-resistance(R_(on,sp)) are obtained. The results indicate that the HKSD device has a higher BV and lower R_(on,sp) compared to the SD device and HK device.
基金supported by the National Science Foundation of China (NSFC) project(41203039)the innovation team of ore-forming dynamics and prediction of concealed deposits, KMUST(2008)
文摘The Langdu high-K calc-alkaline intrusions are located in the Zhongdian area, which is the southern part of the Yidun island arc. These intrusive rocks consist mainly of monzonite porphyry, granodiorite, and diorite porphyry. The K20 content of majority of these rocks is greater than 3%, and, in the K20-SiO2 diagram, all the samples fall into the high-K calc-alkaline to shoshonitic fields. They are enriched in light rare earth elements （LREEs） and depleted in heavy rare earth elements （HREEs; LaN/YbN = 14.3-21.2）, and show slightly negative Eu anomalies （6Eu = 0.77-1.00）. These rocks have high K, Rb, Sr, and Ba contents; moderate to high enrichment of compatible elements （Cr = 36.7-79.9 ppm, Co = 9.6-16.4 ppm, and MgO = 2.2%-3.4%）; low Nb, Ta, and Ti contents, and characteristic of low high field strength elements（HFSEs） versus incompatible elements ratios （Nb/Th = 0.75, Nb/La = 0.34） and incompatible elements ratios （Nb/U = 3.0 and Ce/Pb = 5.1, Ba/Rb = 12.0）. These rocks exhibit restricted Sr and Nd isotopic compositions, with （87Sr/S6Sr）i values ranging from 0.7044 to 0.7069 and ENd（t） values from -2.8 to -2.2. The Sr-Nd isotope systematic and specific trace element ratios suggest that Langdu high-K calc-alkaline intrusive rocks derived from a metasomatized mantle source. The unique geochemical feature of intrusive rocks can be modeled successfully using different members of a slightly enriched mantle, a slab-derived fluid, and terrigenous sediments. It can be inferred that the degree of partial melting and the presence of specific components are temporally related to the tectonic evolution of the Zhongdian island arc. Formation of these rocks can be explained by the various degrees of melting within an ascending region of the slightly enriched mantle, triggered by the subduction of the Garz^--Litang ocean, and an interaction between the slab-derived fluid and the terrigenous sediments.
基金supported in part by the National Natural Science Foundation of China(Grant No.61974015)Key R&D Project of Science and Technology Plan of the Sichuan province(Grant No.2021YFG0139)the Open Foundation of State Key Laboratory of Electronic Thin Films and Integrated Devices of China(Grant No.KFJJ201806)。
文摘A new SiC superjunction power MOSFET device using high-k insulator and p-type pillar with an integrated Schottky barrier diode(Hk-SJ-SBD MOSFET)is proposed,and has been compared with the SiC high-k MOSFET(Hk MOSFET),SiC superjuction MOSFET(SJ MOSFET)and the conventional SiC MOSFET in this article.In the proposed SiC Hk-SJ-SBD MOSFET,under the combined action of the p-type region and the Hk dielectric layer in the drift region,the concentration of the N-drift region and the current spreading layer can be increased to achieve an ultra-low specific on-resistance(Ron,sp).The integrated Schottky barrier diode(SBD)also greatly improves the reverse recovery performance of the device.TCAD simulation results indicate that the Ron,sp of the proposed SiC Hk-SJ-SBD MOSFET is 0.67 mΩ·cm^(2)with a 2240 V breakdown voltage(BV),which is more than 72.4%,23%,5.6%lower than that of the conventional SiC MOSFET,Hk SiC MOSFET and SJ SiC MOSFET with the 1950,2220,and 2220V BV,respectively.The reverse recovery time and reverse recovery charge of the proposed MOSFET is 16 ns and18 nC,which are greatly reduced by more than 74%and 94%in comparison with those of all the conventional SiC MOSFET,Hk SiC MOSFET and SJ SiC MOSFET,due to the integrated SBD in the proposed MOSFET.And the trade-off relationship between the Ron,sp and the BV is also significantly improved compared with that of the conventional MOSFET,Hk MOSFET and SJ MOSFET as well as the MOSFETs in other previous literature,respectively.In addition,compared with conventional SJ SiC MOSFET,the proposed SiC MOSFET has better immunity to charge imbalance,which may bring great application prospects.
基金Project supported by the National Natural Science Foundation of China （Grant No 90307006）, by the National High Tech. Development Program of China （Grant No 2003AA1Z1370）, and by the State Key Development Program for Basic Research of China （Grant No G2000036500）.
文摘This paper reports that the high-K HfO2 gate dielectrics are fabricated on n-germanium substrates by sputtering Hf on Ge and following by a furnace annealing. The impacts of sputtering ambient, annealing ambient and annealing temperature on the electrical properties of high-K HfO2 gate dielectrics on germanium substrates are investigated. Experimental results indicate that high-K HfO2 gate dielectrics on germanium substrates with good electrical characteristics are obtained, the electrical properties of high-K HfO2 gate dielectrics is strongly correlated with sputtering ambient, annealing ambient and annealing temperature.
基金Project supported by the National Basic Research Program of China(Grant No.2011CBA00607)the National Natural Science Foundation of China(Grant Nos.61106089 and 61376097)the Zhejiang Provincial Natural Science Foundation of China(Grant No.LR14F040001)
文摘A novel trench MOS barrier Schottky diode（TMBS） device with a high-k material introduced into the gate insulator is reported, which is named high-k TMBS. By simulation with Medici, it is found that the high-k TMBS can have 19.8% lower leakage current while maintaining the same breakdown voltage and forward turn-on voltage compared with the conventional regular trench TMBS.
基金Project supported by the National Natural Science Foundation of China （Grant No 60776016）, the RGC of HKSAR, China （Grant No HKU7142/05E）, and Open Foundation of State Key Laboratory of Advanced Technology for Materials Synthesis and Processing （Grant No WUT2006M02）.
文摘A physical model for mobility degradation by interface-roughness scattering and Coulomb scattering is proposed for SiGe p-MOSFET with a high-k dielectric/SiO2 gate stack. Impacts of the two kinds of scatterings on mobility degradation are investigated. Effects of interlayer （SiO2） thickness and permittivities of the high-k dielectric and interlayer on carrier mobility are also discussed. It is shown that a smooth interface between high-k dielectric and interlayer, as well as moderate permittivities of high-k dielectrics, is highly desired to improve carriers mobility while keeping alow equivalent oxide thickness. Simulated results agree reasonably with experimental data.
基金support from Natural Science Foundation of Jiangsu Province (ProjectNo. BK2007130)National Natural Science Foundation of China (Grant Nos. 10874065, 60576023 and 60636010)+3 种基金Ministry of Science and Technology of China (Grant No.2009CB929503)Ministry of Science and Technology of China (Grant Nos. 2009CB929503 and2009ZX02101-4)the project sponsored by the Scientific Research Foundation for the Returned Overseas Chinese Scholars, State Education MinistryNational Found for Fostering Talents of Basic Science (NFFTBS) (ProjectNo. J0630316)
文摘The decreasing feature sizes in complementary metal-oxide semiconductor （CMOS） transistor technology will require the replacement of SiO2 with gate dielectrics that have a high dielectric constant （high-k） because as the SiO2 gate thickness is reduced below 1.4 nm, electron tunnelling effects and high leakage currents occur in SiO2, which present serious obstacles to future device reliability. In recent years significant progress has been made on the screening and selection of high-k gate dielectrics, understanding their physical properties, and their integration into CMOS technology. Now the family of hafnium oxide-based materials has emerged as the leading candidate for high-k gate dielectrics due to their excellent physical properties. It is also realized that the high-k oxides must be implemented in conjunction with metal gate electrodes to get sufficient potential for CMOS continue scaling. In the advanced nanoscale Si-based CMOS devices, the composition and thickness of interfacial layers in the gate stacks determine the critical performance of devices. Therefore, detailed atomic- scale understandings of the microstructures and interfacial structures built in the advanced CMOS gate stacks, are highly required. In this paper, several high-resolution electron, ion, and photon-based techniques currently used to characterize the high-k gate dielectrics and interfaces at atomic-scale, are reviewed. Particularly, we critically review the research progress on the characterization of interface behavior and structural evolution in the high-k gate dielectrics by high-resolution transmission electron microscopy （HRTEM） and the related techniques based on scanning transmission electron microscopy （STEM）, including high-angle annular dark- field （HAADF） imaging （also known as Z-contrast imaging）, electron energy-loss spectroscopy （EELS）, and energy dispersive X-ray spectroscopy （EDS）, due to that HRTEM and STEM have become essential metrology tools for characterizing the dielectric gate stacks in the present and future generations of CMOS devices. In Section 1 of this review, the working principles of each technique are briefly introduced and their key features are outlined. In Section 2, microstructural characterizations of high-k gate dielectrics at atomic-scale by electron microscopy are critically reviewed by citing some recent results reported on high-k gate dielectrics. In Section 3, metal gate electrodes and the interfacial structures between high-k dielectrics and metal gates are discussed. The electron beam damage effects in high-k gate stacks are also evaluated, and their origins and prevention are described in Section 4. Finally, we end this review with personal perspectives towards the future challenges of atomic-scale material characterization in advanced CMOS gate stacks.
基金the support from the National Major Project of Fundamental Research:Nanomaterials and Nanostructures(Grant No.2005CB623603)the National Natural Science Foundation of China(Grant No.10674138)the Special Fund for President Scholarship,Chinese Academy of Sciences.
文摘With the continued downscaling of complementary metal-oxide-semiconductor field effect transistor dimensions, high-dielectric constant （high-k） gate materials, as alternatives to SiO2, have been extensively investigated. Hf （Zr）-based high-k gate dielectric thin films have been regarded as the most promising candidates for high-k gate dielectric according to the International Technology Roadmap for Semiconductor due to their excellent physical properties and performance. This paper reviews the recent progress on Hf （Zr）-based high-k gate dielectrics based on PVD （physical vapor deposition） process. This article begins with a survey of various methods developed for generating Hf （Zr）-based high-k gate dielectrics, and then mainly focuses on microstructure, synthesis, characterization, formation mechanisms of interfacial layer, and optical properties of Hf （Zr）-based high-k gate dielectrics. Finally, this review concludes with personal perspectives towards future research on Hf （Zr）-based high-k gate dielectrics.
基金Project supported by the National Natural Science Foundation of China (Grant Nos. 60936005 and 61076097)the Cultivation Fund of the Key Scientific and Technical Innovation Project,Ministry of Education of China (Grant No. 708083)the Fundamental Research Funds for the Central Universities (Grant No. 20110203110012)
文摘In this paper the influences of the metal-gate and high-k/SiO 2 /Si stacked structure on the metal-oxide-semiconductor field-effect transistor（MOSFET） are investigated.The flat-band voltage is revised by considering the influences of stacked structure and metal-semiconductor work function fluctuation.The two-dimensional Poisson＇s equation of potential distribution is presented.A threshold voltage analytical model for metal-gate/high-k/SiO 2 /Si stacked MOSFETs is developed by solving these Poisson＇s equations using the boundary conditions.The model is verified by a two-dimensional device simulator,which provides the basic design guidance for metal-gate/high-k/SiO 2 /Si stacked MOSFETs.
基金Project supported by the National Natural Science Foundation of China(Grant No.61774064)
文摘NH3-plasma treatment is used to improve the quality of the gate dielectric and interface. Al2O3 is adopted as a buffer layer between HfO2 and MoS2 to decrease the interface-state density. Four groups of MOS capacitors and back-gate transistors with different gate dielectrics are fabricated and their C–V and I–V characteristics are compared. It is found that the Al2O3/HfO2 back-gate transistor with NH3-plasma treatment shows the best electrical performance: high on–off current ratio of 1.53 × 107, higher field-effect mobility of 26.51 cm2/V·s, and lower subthreshold swing of 145 m V/dec.These are attributed to the improvements of the gate dielectric and interface qualities by the NH3-plasma treatment and the addition of Al2O3 as a buffer layer.
基金supported by the National High Technology Research and Development Program of China(Grant No.SS2015AA010601)the National Natural Science Foundation of China(Grant Nos.61176091 and 61306129)the Opening Project of Key Laboratory of Microelectronics Devices&Integrated Technology,Institute of Micro Electronics of Chinese Academy of Sciences
文摘High-k metal gate stacks are being used to suppress the gate leakage due to tunneling for sub-45 nm technology nodes.The reliability of thin dielectric films becomes a limitation to device manufacturing,especially to the breakdown characteristic.In this work,a breakdown simulator based on a percolation model and the kinetic Monte Carlo method is set up,and the intrinsic relation between time to breakdown and trap generation rate R is studied by TDDB simulation.It is found that all degradation factors,such as trap generation rate time exponent m,Weibull slope β and percolation factor s,each could be expressed as a function of trap density time exponent α.Based on the percolation relation and power law lifetime projection,a temperature related trap generation model is proposed.The validity of this model is confirmed by comparing with experiment results.For other device and material conditions,the percolation relation provides a new way to study the relationship between trap generation and lifetime projection.
基金supported by the National Natural Science Foundation of China(Grant No.61604016)China Postdoctoral Science Foundation(Grant No.2017M613028)the Fundamental Research Funds for the Central Universities,China(Grant Nos.310831161003 and CHD2017ZD142)
文摘In this work, an in-situ ozone treatment is carried out to improve the interface thermal stability of HfO_2/Al_2O_3 gate stack on germanium（Ge） substrate. The micrometer scale level of HfO_2/Al_2O_3 gate stack on Ge is studied using conductive atomic force microscopy（AFM） with a conductive tip. The initial results indicate that comparing with a non insitu ozone treated sample, the interface thermal stability of the sample with an in-situ ozone treatment can be substantially improved after annealing. As a result, void-free surface, low conductive spots, low leakage current density, and relative high breakdown voltage high-κ/Ge are obtained. A detailed analysis is performed to confirm the origins of the changes.All results indicate that in-situ ozone treatment is a promising method to improve the interface properties of Ge-based three-dimensional（3D） devices in future technology nodes.
