Classical atomistic simulations based on the lattice dynalnics theory and the Born core-shell model are performed to systematically study the crystal structure and thermal properties of high-k Hfl-xSixO2. The coeffici...Classical atomistic simulations based on the lattice dynalnics theory and the Born core-shell model are performed to systematically study the crystal structure and thermal properties of high-k Hfl-xSixO2. The coefficients of thermal expansion, specific heat, Griineisen parameters, phonon densities of states and Debye temperatures are calculated at different temperatures and for different Si-doping concentrations. With the increase of the Si-doping concentration, the lattice constant decreases. At the same time, both the coefficient of thermal expansion and the specific heat at a constant volume of Hf1-mSixO2 also decreases. The Griineisen parameter is about 0.95 at temperatures less than 100 K. Compared with Si-doped HfO2, pure HfO2 has a higher Debye temperature when the temperature is less than 25 K, while it has lower Debye temperature when the temperature is higher than 50 K. Some simulation results fit well with the experimental data. We expect that our results will be helpful for understanding the local lattice structure and thermal properties of Hf1-mSixO2.展开更多
The gate dielectric plays a critical role in field-effect transistors since it determines the capability of gate control and the reliability of the device.In modern large scale integrated circuits,the stacking of high...The gate dielectric plays a critical role in field-effect transistors since it determines the capability of gate control and the reliability of the device.In modern large scale integrated circuits,the stacking of high-k oxides has become an indispensable strategy to enable the continuous shrinking of the device.However,the multiple interfaces,various kinds and large number of defects have brought about significant reliability issues such as threshold voltage shift,gate leakage current,random noise,hysteresis,fixed charges and so on.Effectively dealing with these reliability issues has become the main challenge of dielectric design.On the other hand,with the emerging of twodimensional(2D)channel materials,traditional oxide dielectrics turn out to be nonideal due to their surface dangling bonds.The development and design of new gate dielectrics become urgent and attractive.In this review,we will summarize the advantages and challenges of different dielectrics that are applicable to several mainstream channel materials,including Si,SiC,GaN and 2D materials.For each kind of dielectric,possible strategies to improve its reliability are discussed.展开更多
Growing a silicon(Si) layer on top of stacked Si-germanium(Ge) compressive layer can introduce a tensile strain on the former, resulting in superior device characteristics. Such a structure can be used for high perfor...Growing a silicon(Si) layer on top of stacked Si-germanium(Ge) compressive layer can introduce a tensile strain on the former, resulting in superior device characteristics. Such a structure can be used for high performance complementary metal-oxide-semiconductor(CMOS) circuits. Down scaling metal-oxide-semiconductor field-effect transistors(MOSFETs) into the deep submicron/nanometer regime forces the source(S) and drain(D) series resistance to become comparable with the channel resistance and thus it cannot be neglected. Owing to the persisting technological importance of strained Si devices, in this work, we propose a multi-iterative technique for evaluating the performance of strained-Si/strained-Si_(1-y)Ge_y/relaxed-Si_(1-x)Ge_x MOSFETs and its related circuits in the presence of S/D series resistance, leading to the development of a simulator that can faithfully plot the performance of the device and related digital circuits. The impact of strain on device/circuit performance is also investigated with emphasis on metal gate and high-k dielectric materials.展开更多
The integration of high-k dielectrics with two-dimensional(2D)semiconductors is a critical step towards high-performance nanoelectronics,which however remains challenging due to the high density of interface states an...The integration of high-k dielectrics with two-dimensional(2D)semiconductors is a critical step towards high-performance nanoelectronics,which however remains challenging due to the high density of interface states and the damage to the monolayer 2D semiconductors.In this study,we propose a selective hydrogenation strategy to improve the interface properties while the 2D semiconductors are not affected.Using the interface of monolayer molybdenum disulfide(MoS_(2))and silicon nitride as an example,we show substantially improved interface properties for electronic applications after the interfacial hydrogenation,as evidenced by reduced inhomogeneous charge redistribution,increased band offset,and nearly intact electronic properties of MoS_(2).Importantly,this hydrogenation process selectively occurs only at the silicon nitride surface and is compatible with the current semiconductor fabrication process.We further show that this strategy is general and applicable to other interfaces between high-k dielectrics and 2D semiconductors such as hafnium dioxide(HfO_(2))on the monolayer MoS_(2).Our results demonstrate a simple yet viable way to improve the integration of high-k dielectrics on a broad range of 2D transition metal disulfide semiconductors,shedding light on practical electronic and optoelectronic applications.展开更多
We investigate the effect of a high-k dielectric in the tunnel layer to improve the erase speed-retention trade-off. Here, the proposed stack in the tunnel layer is AlLaO_3/Hf AlO/SiO_2. These proposed materials posse...We investigate the effect of a high-k dielectric in the tunnel layer to improve the erase speed-retention trade-off. Here, the proposed stack in the tunnel layer is AlLaO_3/Hf AlO/SiO_2. These proposed materials possess low valence band offset with high permittivity to improve both the erase speed and retention time in barrier engineered silicon-oxide-nitride-oxide-silicon（BE-SONOS）. In the proposed structure Hf Al O and AlLaO_3 replace Si_3N_4 and the top SiO_2 layer in a conventional oxide/nitride/oxide（ONO） tunnel stack. Due to the lower conduction band offset（CBO） and high permittivity of the proposed material in the tunnel layer, it offers better program/erase（P/E） speed and retention time. In this work the gate length is also scaled down from 220 to 55 nm to observe the effect of high-k materials while scaling, for the same equivalent oxide thickness（EOT）. We found that the scaling down of the gate length has a negligible impact on the memory window of the devices. Hence, various investigated tunnel oxide stacks possess a good memory window with a charge retained up to 87.4%（at room temperature） after a period of ten years. We also examine the use of a metal gate instead of a polysilicon gate, which shows improved P/E speed and retention time.展开更多
基金Project supported by the National Natural Science Foundation of China (Grant Nos. 10964003 and 11164014)the Natural Science Foundation of Gansu Province, China (Grant No. 096RJZA102)+1 种基金the Specialized Research Fund for the Doctoral Program of Higher Education, China (Grant No. 20096201120002)the China Postdoctoral Science Foundation (Grant Nos. 20100470886 and 201104324)
文摘Classical atomistic simulations based on the lattice dynalnics theory and the Born core-shell model are performed to systematically study the crystal structure and thermal properties of high-k Hfl-xSixO2. The coefficients of thermal expansion, specific heat, Griineisen parameters, phonon densities of states and Debye temperatures are calculated at different temperatures and for different Si-doping concentrations. With the increase of the Si-doping concentration, the lattice constant decreases. At the same time, both the coefficient of thermal expansion and the specific heat at a constant volume of Hf1-mSixO2 also decreases. The Griineisen parameter is about 0.95 at temperatures less than 100 K. Compared with Si-doped HfO2, pure HfO2 has a higher Debye temperature when the temperature is less than 25 K, while it has lower Debye temperature when the temperature is higher than 50 K. Some simulation results fit well with the experimental data. We expect that our results will be helpful for understanding the local lattice structure and thermal properties of Hf1-mSixO2.
基金supported by the National Key Research and Development Program of China(Grant No.2022YFF0605800)the CAS Project for Young Scientists in Basic Research(No.YSBR-056)the MIND Project(Grant No.MINDKT202403).
文摘The gate dielectric plays a critical role in field-effect transistors since it determines the capability of gate control and the reliability of the device.In modern large scale integrated circuits,the stacking of high-k oxides has become an indispensable strategy to enable the continuous shrinking of the device.However,the multiple interfaces,various kinds and large number of defects have brought about significant reliability issues such as threshold voltage shift,gate leakage current,random noise,hysteresis,fixed charges and so on.Effectively dealing with these reliability issues has become the main challenge of dielectric design.On the other hand,with the emerging of twodimensional(2D)channel materials,traditional oxide dielectrics turn out to be nonideal due to their surface dangling bonds.The development and design of new gate dielectrics become urgent and attractive.In this review,we will summarize the advantages and challenges of different dielectrics that are applicable to several mainstream channel materials,including Si,SiC,GaN and 2D materials.For each kind of dielectric,possible strategies to improve its reliability are discussed.
文摘Growing a silicon(Si) layer on top of stacked Si-germanium(Ge) compressive layer can introduce a tensile strain on the former, resulting in superior device characteristics. Such a structure can be used for high performance complementary metal-oxide-semiconductor(CMOS) circuits. Down scaling metal-oxide-semiconductor field-effect transistors(MOSFETs) into the deep submicron/nanometer regime forces the source(S) and drain(D) series resistance to become comparable with the channel resistance and thus it cannot be neglected. Owing to the persisting technological importance of strained Si devices, in this work, we propose a multi-iterative technique for evaluating the performance of strained-Si/strained-Si_(1-y)Ge_y/relaxed-Si_(1-x)Ge_x MOSFETs and its related circuits in the presence of S/D series resistance, leading to the development of a simulator that can faithfully plot the performance of the device and related digital circuits. The impact of strain on device/circuit performance is also investigated with emphasis on metal gate and high-k dielectric materials.
基金M.Y.acknowledges the funding support(Nos:1-BE47 and ZE2F)from The Hong Kong Polytechnic University.
文摘The integration of high-k dielectrics with two-dimensional(2D)semiconductors is a critical step towards high-performance nanoelectronics,which however remains challenging due to the high density of interface states and the damage to the monolayer 2D semiconductors.In this study,we propose a selective hydrogenation strategy to improve the interface properties while the 2D semiconductors are not affected.Using the interface of monolayer molybdenum disulfide(MoS_(2))and silicon nitride as an example,we show substantially improved interface properties for electronic applications after the interfacial hydrogenation,as evidenced by reduced inhomogeneous charge redistribution,increased band offset,and nearly intact electronic properties of MoS_(2).Importantly,this hydrogenation process selectively occurs only at the silicon nitride surface and is compatible with the current semiconductor fabrication process.We further show that this strategy is general and applicable to other interfaces between high-k dielectrics and 2D semiconductors such as hafnium dioxide(HfO_(2))on the monolayer MoS_(2).Our results demonstrate a simple yet viable way to improve the integration of high-k dielectrics on a broad range of 2D transition metal disulfide semiconductors,shedding light on practical electronic and optoelectronic applications.
文摘We investigate the effect of a high-k dielectric in the tunnel layer to improve the erase speed-retention trade-off. Here, the proposed stack in the tunnel layer is AlLaO_3/Hf AlO/SiO_2. These proposed materials possess low valence band offset with high permittivity to improve both the erase speed and retention time in barrier engineered silicon-oxide-nitride-oxide-silicon（BE-SONOS）. In the proposed structure Hf Al O and AlLaO_3 replace Si_3N_4 and the top SiO_2 layer in a conventional oxide/nitride/oxide（ONO） tunnel stack. Due to the lower conduction band offset（CBO） and high permittivity of the proposed material in the tunnel layer, it offers better program/erase（P/E） speed and retention time. In this work the gate length is also scaled down from 220 to 55 nm to observe the effect of high-k materials while scaling, for the same equivalent oxide thickness（EOT）. We found that the scaling down of the gate length has a negligible impact on the memory window of the devices. Hence, various investigated tunnel oxide stacks possess a good memory window with a charge retained up to 87.4%（at room temperature） after a period of ten years. We also examine the use of a metal gate instead of a polysilicon gate, which shows improved P/E speed and retention time.
