This paper presents a ZUC-256 stream cipher algorithm hardware system in order to prevent the advanced security threats for 5 G wireless network.The main innovation of the hardware system is that a six-stage pipeline ...This paper presents a ZUC-256 stream cipher algorithm hardware system in order to prevent the advanced security threats for 5 G wireless network.The main innovation of the hardware system is that a six-stage pipeline scheme comprised of initialization and work stage is employed to enhance the solving speed of the critical logical paths.Moreover,the pipeline scheme adopts a novel optimized hardware structure to fast complete the Mod(231-1)calculation.The function of the hardware system has been validated experimentally in detail.The hardware system shows great superiorities.Compared with the same type system in recent literatures,the logic delay reduces by 47%with an additional hardware resources of only 4 multiplexers,the throughput rate reaches 5.26 Gbps and yields at least 45%better performance,the throughput rate per unit area increases 14.8%.The hardware system provides a faster and safer encryption module for the 5G wireless network.展开更多
Emerging memristive devices offer enormous advantages for applications such as non-volatile memories and inmemory computing(IMC),but there is a rising interest in using memristive technologies for security application...Emerging memristive devices offer enormous advantages for applications such as non-volatile memories and inmemory computing(IMC),but there is a rising interest in using memristive technologies for security applications in the era of internet of things(IoT).In this review article,for achieving secure hardware systems in IoT,lowpower design techniques based on emerging memristive technology for hardware security primitives/systems are presented.By reviewing the state-of-the-art in three highlighted memristive application areas,i.e.memristive non-volatile memory,memristive reconfigurable logic computing and memristive artificial intelligent computing,their application-level impacts on the novel implementations of secret key generation,crypto functions and machine learning attacks are explored,respectively.For the low-power security applications in IoT,it is essential to understand how to best realize cryptographic circuitry using memristive circuitries,and to assess the implications of memristive crypto implementations on security and to develop novel computing paradigms that will enhance their security.This review article aims to help researchers to explore security solutions,to analyze new possible threats and to develop corresponding protections for the secure hardware systems based on low-cost memristive circuit designs.展开更多
Microcontroller <span><span><span style="font-family:;" "="">is </span></span></span><span><span><span style="font-family:;" "...Microcontroller <span><span><span style="font-family:;" "="">is </span></span></span><span><span><span style="font-family:;" "="">widely</span></span></span><span><span><span style="font-family:;" "=""> </span></span></span><span><span><span style="font-family:;" "="">used in the intelligent life of modern society. Intelligent development based</span></span></span><span><span><span style="font-family:;" "=""> </span></span></span><span><span><span style="font-family:;" "="">on Microcontroller to solve the actual needs of people</span></span></span><span><span><span style="font-family:;" "="">’</span></span></span><span><span><span style="font-family:;" "="">s life, work, study and</span></span></span><span><span><span style="font-family:;" "=""> </span></span></span><span><span><span style="font-family:;" "="">other fields is the core of Microcontroller application.</span></span></span><span><span><span style="font-family:;" "=""> </span></span></span><span><span><span style="font-family:;" "="">Therefore, it is a task for researchers to understand the structure and performance of microcontroller, develop software, and be familiar with the method and process of intelligent development based on microcontroller. And with that in mind</span></span></span><span><span><span style="font-family:;" "="">, t</span></span></span><span><span><span style="font-family:;" "="">his paper designs and produces a physical hardware system for indoor environment detection based on STM32 microcontroller. The system can detect the light intensity, temperature and humidity, and CO gas concentration in the indoor environment;and the data is integrated and processed by the STM32 microcontroller to display the current parameter values of each quantity in the indoor environment on a 3.5-inch resistive screen;at the same time, the PC can also log in to the OneNET cloud platform through the web page, and display the light intensity, temperature and humidity, and CO gas concentration values in the indoor environment in real time in the device created by OneNET for real-time viewing. The system can also display the light intensity, temperature and humidity, and CO gas concentration values in the indoor environment in real time. The hardware system has been tested and tested to achieve its function.</span></span></span>展开更多
We report a design and implementation of a field-programmable-gate-arrays(FPGA)based hardware platform,which is used to realize control and signal readout of trapped-ion-based multi-level quantum systems.This platform...We report a design and implementation of a field-programmable-gate-arrays(FPGA)based hardware platform,which is used to realize control and signal readout of trapped-ion-based multi-level quantum systems.This platform integrates a four-channel 2.8 Gsps@14 bits arbitrary waveform generator,a 16-channel 1 Gsps@14 bits direct-digital-synthesisbased radio-frequency generator,a 16-channel 8 ns resolution pulse generator,a 10-channel 16 bits digital-to-analogconverter module,and a 2-channel proportion integration differentiation controller.The hardware platform can be applied in the trapped-ion-based multi-level quantum systems,enabling quantum control of multi-level quantum system and highdimensional quantum simulation.The platform is scalable and more channels for control and signal readout can be implemented by utilizing more parallel duplications of the hardware.The hardware platform also has a bright future to be applied in scaled trapped-ion-based quantum systems.展开更多
In this paper,the spectral efficiency(SE)of an uplink hardware-constrained cell-free massive multi-input multi-output(MIMO)system with maximal ratio combining(MRC)receiver filters in the context of superimposed pilots...In this paper,the spectral efficiency(SE)of an uplink hardware-constrained cell-free massive multi-input multi-output(MIMO)system with maximal ratio combining(MRC)receiver filters in the context of superimposed pilots(SPs)is investigated.Tractable closed-form SE expressions for the considered system are derived,which share us with opportunities to explore the impacts of the hardware quality coefficient,the length of coherence interval,and the power balance factor between pilot and data signals.Numerical results indicate that the achievable SE deteriorates as the hardware quality decreases and is more susceptible to the hardware impairments at the user equipments(UEs).Besides,we observe that SPs outperform regular pilots(RPs)in terms of SE and this performance gain is heavily dependent on the values of power balance factor and coherence interval.However,the superiorities of SPs over RPs have vanished when severe hardware imperfections are considered.展开更多
Embedded Ethernet technology has been utilized increasingly widely as the communication mode in the substation automation system(SAS).This paper introduces the current applying situation about embedded Ethernet in SAS...Embedded Ethernet technology has been utilized increasingly widely as the communication mode in the substation automation system(SAS).This paper introduces the current applying situation about embedded Ethernet in SAS First.After analyzing the protocol levels used in SAS based on embedded Ethernet and the differences between the TCP and UDP,UDP/IP is selected as the communication protocol between the station-level and bay-level devices for its real-time characteristic.Then a new kind of implementation of the embedded Ethernet is presented based on hardware protocol stack.The designed scheme can be implemented easily,reduce cost significantly and shorten developing cycle.展开更多
This paper investigates the system outage performance of a simultaneous wireless information and power transfer(SWIPT)based two-way decodeand-forward(DF)relay network,where potential hardware impairments(HIs)in all tr...This paper investigates the system outage performance of a simultaneous wireless information and power transfer(SWIPT)based two-way decodeand-forward(DF)relay network,where potential hardware impairments(HIs)in all transceivers are considered.After harvesting energy and decoding messages simultaneously via a power splitting scheme,the energy-limited relay node forwards the decoded information to both terminals.Each terminal combines the signals from the direct and relaying links via selection combining.We derive the system outage probability under independent but non-identically distributed Nakagami-m fading channels.It reveals an overall system ceiling(OSC)effect,i.e.,the system falls in outage if the target rate exceeds an OSC threshold that is determined by the levels of HIs.Furthermore,we derive the diversity gain of the considered network.The result reveals that when the transmission rate is below the OSC threshold,the achieved diversity gain equals the sum of the shape parameter of the direct link and the smaller shape parameter of the terminalto-relay links;otherwise,the diversity gain is zero.This is different from the amplify-and-forward(AF)strategy,under which the relaying links have no contribution to the diversity gain.Simulation results validate the analytical results and reveal that compared with the AF strategy,the SWIPT based two-way relaying links under the DF strategy are more robust to HIs and achieve a lower system outage probability.展开更多
Nowadays, digital camera based remote controllers are widely used in people’s daily lives. It is known that the edge detection process plays an essential role in remote controlled applications. In this paper, a syste...Nowadays, digital camera based remote controllers are widely used in people’s daily lives. It is known that the edge detection process plays an essential role in remote controlled applications. In this paper, a system verification platform of hardware optimization based on the edge detection is proposed. The Field-Programmable Gate Array (FPGA) validation is an important step in the Integrated Circuit (IC) design workflow. The Sobel edge detection algorithm is chosen and optimized through the FPGA verification platform. Hardware optimization techniques are used to create a high performance, low cost design. The Sobel edge detection operator is designed and mounted through the system Advanced High-performance Bus (AHB). Different FPGA boards are used for evaluation purposes. It is proved that with the proposed hardware optimization method, the hardware design of the Sobel edge detection operator can save 6% of on-chip resources for the Sobel core calculation and 42% for the whole frame calculation.展开更多
This work presents a novel wavelet-based denoising technique for improving the signal-to-noise ratio(SNR)of nonsteady vibration signals in hardware redundant systems.The proposed method utilizes the relationship betwe...This work presents a novel wavelet-based denoising technique for improving the signal-to-noise ratio(SNR)of nonsteady vibration signals in hardware redundant systems.The proposed method utilizes the relationship between redundant hardware components to effectively separate fault-related components from the vibration signature,thus enhancing fault detection accuracy.The study evaluates the proposed technique on two mechanically identical subsystems that are simultaneously controlled under the same speed and load inputs,with and without the proposed denoising step.The results demonstrate an increase in detection accuracy when incorporating the proposed denoising method into a fault detection system designed for hardware redundant machinery.This work is original in its application of a new method for improving performance when using residual analysis for fault detection in hardware redundant machinery configurations.Moreover,the proposed methodology is applicable to nonstationary equipment that experiences changes in both speed and load.展开更多
The problems of current highly redundant flight control system are analyzed in this paper. Our study gives methods of utilizing other information to reduce physical components on the condition of meeting the reliabili...The problems of current highly redundant flight control system are analyzed in this paper. Our study gives methods of utilizing other information to reduce physical components on the condition of meeting the reliability requirements for flight control system. The strategies presented in this paper mainly include information redundancy, multi-thread, time redundancy, geometry space redundancy, etc.. Analysis and simulation show these non-hardware based methods can reduce the requirement of system hardware level and thus reduce the system complexity, weight, space, costs and R＆D （research and development） time.展开更多
In this paper, the storage capacity of communication among cores and processors is taken into account and a maximum D-value-first algorithm is proposed. By improving the hardware parallelism in the task execution proc...In this paper, the storage capacity of communication among cores and processors is taken into account and a maximum D-value-first algorithm is proposed. By improving the hardware parallelism in the task execution process, the maximum storage requirements for communication are minimized. Experimental results with various directed acyclic graph models showed that compared with the earliest-task-first algorithm, the storage requirements for communication were reduced by 22.46%, on average, while the average of makespan only increased by 0.82%,.展开更多
A new task mode, hardware logic task mode, is presented. Its architecture, schedule and implementation are described with HDI.（ Hardware Description Language ）, and the validity of the system has been proved by logi...A new task mode, hardware logic task mode, is presented. Its architecture, schedule and implementation are described with HDI.（ Hardware Description Language ）, and the validity of the system has been proved by logic simulation. It has advantage for real-time applications and overheadsaving for operating .system, so it is profitable for the controller in the embedded system. The relationship among RTOS （Real-Time Operating System）, SoC（System on Chip）, VIA （Virtual Interface Architecture） and hardware logic task is also discussed in the paper.展开更多
Depth estimation is an active research area with the developing of stereo vision in recent years. It is one of the key technologies to resolve the large data of stereo vision communication. Now depth estimation still ...Depth estimation is an active research area with the developing of stereo vision in recent years. It is one of the key technologies to resolve the large data of stereo vision communication. Now depth estimation still has some problems, such as occlusion, fuzzy edge, real-time processing, etc. Many algorithms have been proposed base on software, however the performance of the computer configurations limits the software processing speed. The other resolution is hardware design and the great developments of the digital signal processor （DSP）, and application specific integrated circuit （ASIC） and field programmable gate array （FPGA） provide the opportunity of flexible applications. In this work, by analyzing the procedures of depth estimation, the proper algorithms which can be used in hardware design to execute real-time depth estimation are proposed. The different methods of calibration, matching and post-processing are analyzed based on the hardware design requirements. At last some tests for the algorithm have been analyzed. The results show that the algorithms proposed for hardware design can provide credited depth map for further view synthesis and are suitable for hardware design.展开更多
Recently there has been great interest in the idea that evolvable system based on the principle of artifcial intelligence can be used to continuously and autonomously adapt the behaviour of physically embedded systems...Recently there has been great interest in the idea that evolvable system based on the principle of artifcial intelligence can be used to continuously and autonomously adapt the behaviour of physically embedded systems such as autonomous mobile robots and intelligent home devices. Meanwhile, we have seen the introduction of evolvable hardware(EHW): new integrated electronic circuits that are able to continuously evolve to adapt the chages in the environment implemented by evolutionary algorithms such as genetic algorithm(GA) and reinforcement learning. This paper concentrates on developing a robotic navigation system whose basic behaviours are obstacle avoidance and light source navigation. The results demonstrate that the intrinsic evolvable hardware system is able to create the stable robotiiuc behaviours as required in the real world instead of the traditional hardware systems.展开更多
Nowadays, from home monitoring to large airport security, a lot of digital video surveillance systems have been used. Digital surveillance system usually requires streaming video processing abilities. As an advanced v...Nowadays, from home monitoring to large airport security, a lot of digital video surveillance systems have been used. Digital surveillance system usually requires streaming video processing abilities. As an advanced video coding method, H.264 is introduced to reduce the large video data dramatically (usually by 70X or more). However, computational overhead occurs when coding and decoding H.264 video. In this paper, a System-on-a-Chip (SoC) based hardware acceleration solution for video codec is proposed, which can also be used for other software applications. The characteristics of the video codec are analyzed by using the profiling tool. The Hadamard function, which is the bottleneck of H.264, is identified not only by execution time but also another two attributes, such as cycle per loop and loop round. The Co-processor approach is applied to accelerate the Hadamard function by transforming it to hardware. Performance improvement, resource costs and energy consumption are compared and analyzed. Experimental results indicate that 76.5% energy deduction and 8.09X speedup can be reached after balancing these three key factors.展开更多
This paper deals with a new hardware/software embedded system design methodology based on design pattern approach by development of a new design tool called smartcell. Three main constraints of embedded systems design...This paper deals with a new hardware/software embedded system design methodology based on design pattern approach by development of a new design tool called smartcell. Three main constraints of embedded systems design process are investigated: the complexity, the partitioning between hardware and software aspects and the reusability. Two intermediate models are carried out in order to solve the complexity problem. The partitioning problem deals with the proposed hardware/software partitioning algorithm based on Ant Colony Optimisation. The reusability problem is resolved by synthesis of intellectual property blocks. Specification and integration of an intelligent controller on heterogeneous platform are considered to illustrate the proposed approach.展开更多
An embedded system generally comprises gffour parts （embedded microprocessor unit, peripheral hardware equipment, embedded operating system, and user application）, and its core function is to complete the control of...An embedded system generally comprises gffour parts （embedded microprocessor unit, peripheral hardware equipment, embedded operating system, and user application）, and its core function is to complete the control of different equipments as well as necessary monitoring and management measures. Initialization is to set a variable as ＂default value＂, including system initialization, software initialization and hardware initialization. However, these three types of initialization are classified in accordance with different layers. This is studied in this paper.展开更多
Moving object detection including background subtraction and morphological processing is a critical research topic for video surveillance because of its high computational loading and power consumption. This paper pro...Moving object detection including background subtraction and morphological processing is a critical research topic for video surveillance because of its high computational loading and power consumption. This paper proposes a hardware design to accelerate the computation of background subtraction with low power consumption. A real-time background subtraction method is designed with a frame-buffer scheme and function partition to improve throughput, and implemented using Verilog HDL on FPGA. The design parallelizes the computations of background update and subtraction with a seven-stage pipeline. A stripe-based morphological processing and accounting for the completion of detected objects is devised. Simulation results for videos of VGA resolutions on a low-end FPGA device show 368 fps throughput for only the real-time background subtraction module, and 51 fps for the whole system, including off-chip memory access. Real-time efficiency with low power consumption and low resource utilization is thus demonstrated.展开更多
This article explores the design of a wireless fire alarm system supported by advanced data fusion technology.It includes discussions on the basic design ideas of the wireless fire alarm system,hardware design analysi...This article explores the design of a wireless fire alarm system supported by advanced data fusion technology.It includes discussions on the basic design ideas of the wireless fire alarm system,hardware design analysis,software design analysis,and simulation analysis,all supported by data fusion technology.Hopefully,this analysis can provide some reference for the rational application of data fusion technology to meet the actual design and application requirements of the system.展开更多
This study analyzes the current situation of the practical teaching system of computer hardware courses in local undergraduate colleges,scrutinizes the experimental environment construction,contents,and methods of com...This study analyzes the current situation of the practical teaching system of computer hardware courses in local undergraduate colleges,scrutinizes the experimental environment construction,contents,and methods of computer hardware courses,and proposes a new practical teaching system for computer hardware courses,so as to meet the needs of transformation and development as well as application-oriented talent training.展开更多
基金supported in part by the National R&D Program for Major Research Instruments of China(Grant No:62027814)the National Natural Science Foundation of China(Grant No:62104054)+2 种基金the Natural Science Foundation of Heilongjiang Province(Grant No:F2018010)the Postdoctoral Science Foundation of Heilongjiang Province,China(No:LBH-Z20133)the Fundamental Research Funds for The Central Universities,China(3072021CF0806)。
文摘This paper presents a ZUC-256 stream cipher algorithm hardware system in order to prevent the advanced security threats for 5 G wireless network.The main innovation of the hardware system is that a six-stage pipeline scheme comprised of initialization and work stage is employed to enhance the solving speed of the critical logical paths.Moreover,the pipeline scheme adopts a novel optimized hardware structure to fast complete the Mod(231-1)calculation.The function of the hardware system has been validated experimentally in detail.The hardware system shows great superiorities.Compared with the same type system in recent literatures,the logic delay reduces by 47%with an additional hardware resources of only 4 multiplexers,the throughput rate reaches 5.26 Gbps and yields at least 45%better performance,the throughput rate per unit area increases 14.8%.The hardware system provides a faster and safer encryption module for the 5G wireless network.
基金supported by the DFG(German Research Foundation)Priority Program Nano Security,Project MemCrypto(Projektnummer 439827659/funding id DU 1896/2–1,PO 1220/15–1)the funding by the Fraunhofer Internal Programs under Grant No.Attract 600768。
文摘Emerging memristive devices offer enormous advantages for applications such as non-volatile memories and inmemory computing(IMC),but there is a rising interest in using memristive technologies for security applications in the era of internet of things(IoT).In this review article,for achieving secure hardware systems in IoT,lowpower design techniques based on emerging memristive technology for hardware security primitives/systems are presented.By reviewing the state-of-the-art in three highlighted memristive application areas,i.e.memristive non-volatile memory,memristive reconfigurable logic computing and memristive artificial intelligent computing,their application-level impacts on the novel implementations of secret key generation,crypto functions and machine learning attacks are explored,respectively.For the low-power security applications in IoT,it is essential to understand how to best realize cryptographic circuitry using memristive circuitries,and to assess the implications of memristive crypto implementations on security and to develop novel computing paradigms that will enhance their security.This review article aims to help researchers to explore security solutions,to analyze new possible threats and to develop corresponding protections for the secure hardware systems based on low-cost memristive circuit designs.
文摘Microcontroller <span><span><span style="font-family:;" "="">is </span></span></span><span><span><span style="font-family:;" "="">widely</span></span></span><span><span><span style="font-family:;" "=""> </span></span></span><span><span><span style="font-family:;" "="">used in the intelligent life of modern society. Intelligent development based</span></span></span><span><span><span style="font-family:;" "=""> </span></span></span><span><span><span style="font-family:;" "="">on Microcontroller to solve the actual needs of people</span></span></span><span><span><span style="font-family:;" "="">’</span></span></span><span><span><span style="font-family:;" "="">s life, work, study and</span></span></span><span><span><span style="font-family:;" "=""> </span></span></span><span><span><span style="font-family:;" "="">other fields is the core of Microcontroller application.</span></span></span><span><span><span style="font-family:;" "=""> </span></span></span><span><span><span style="font-family:;" "="">Therefore, it is a task for researchers to understand the structure and performance of microcontroller, develop software, and be familiar with the method and process of intelligent development based on microcontroller. And with that in mind</span></span></span><span><span><span style="font-family:;" "="">, t</span></span></span><span><span><span style="font-family:;" "="">his paper designs and produces a physical hardware system for indoor environment detection based on STM32 microcontroller. The system can detect the light intensity, temperature and humidity, and CO gas concentration in the indoor environment;and the data is integrated and processed by the STM32 microcontroller to display the current parameter values of each quantity in the indoor environment on a 3.5-inch resistive screen;at the same time, the PC can also log in to the OneNET cloud platform through the web page, and display the light intensity, temperature and humidity, and CO gas concentration values in the indoor environment in real time in the device created by OneNET for real-time viewing. The system can also display the light intensity, temperature and humidity, and CO gas concentration values in the indoor environment in real time. The hardware system has been tested and tested to achieve its function.</span></span></span>
基金the Strategic Priority Research Program of CAS(Grant No.XDC07020200)the National Key R&D Program of China(Grants No.2018YFA0306600)+5 种基金the National Natural Science Foundation of China(Grant Nos.11974330 and 92165206)the Chinese Academy of Sciences(Grant No.QYZDY-SSW-SLH004)the Innovation Program for Quantum Science and Technology(Grant Nos.2021ZD0302200 and 2021ZD0301603)the Anhui Initiative in Quantum Information Technologies(Grant No.AHY050000)the Hefei Comprehensive National Science Centerthe Fundamental Research Funds for the Central Universities。
文摘We report a design and implementation of a field-programmable-gate-arrays(FPGA)based hardware platform,which is used to realize control and signal readout of trapped-ion-based multi-level quantum systems.This platform integrates a four-channel 2.8 Gsps@14 bits arbitrary waveform generator,a 16-channel 1 Gsps@14 bits direct-digital-synthesisbased radio-frequency generator,a 16-channel 8 ns resolution pulse generator,a 10-channel 16 bits digital-to-analogconverter module,and a 2-channel proportion integration differentiation controller.The hardware platform can be applied in the trapped-ion-based multi-level quantum systems,enabling quantum control of multi-level quantum system and highdimensional quantum simulation.The platform is scalable and more channels for control and signal readout can be implemented by utilizing more parallel duplications of the hardware.The hardware platform also has a bright future to be applied in scaled trapped-ion-based quantum systems.
基金This work was supported in part by the National Natural Science Foundation of China under Grants 62071246,61771252,61861039,and 61427801in part by the National Key Research and Development Program of China under Grants 2020YFB1806608 and 2018YFC1314903+2 种基金in part by the Jiangsu Province Special Fund Project for Transformation of Scientific and Technological Achievements under Grant BA2019058in part by the Major Natural Science Research Project of Jiangsu Higher Education Institutions under Grant 18KJA510005in part by the Postgraduate Research&Practice Innovation Program of Jiangsu Province under Grants SJKY190740 and KYCX200709.
文摘In this paper,the spectral efficiency(SE)of an uplink hardware-constrained cell-free massive multi-input multi-output(MIMO)system with maximal ratio combining(MRC)receiver filters in the context of superimposed pilots(SPs)is investigated.Tractable closed-form SE expressions for the considered system are derived,which share us with opportunities to explore the impacts of the hardware quality coefficient,the length of coherence interval,and the power balance factor between pilot and data signals.Numerical results indicate that the achievable SE deteriorates as the hardware quality decreases and is more susceptible to the hardware impairments at the user equipments(UEs).Besides,we observe that SPs outperform regular pilots(RPs)in terms of SE and this performance gain is heavily dependent on the values of power balance factor and coherence interval.However,the superiorities of SPs over RPs have vanished when severe hardware imperfections are considered.
文摘Embedded Ethernet technology has been utilized increasingly widely as the communication mode in the substation automation system(SAS).This paper introduces the current applying situation about embedded Ethernet in SAS First.After analyzing the protocol levels used in SAS based on embedded Ethernet and the differences between the TCP and UDP,UDP/IP is selected as the communication protocol between the station-level and bay-level devices for its real-time characteristic.Then a new kind of implementation of the embedded Ethernet is presented based on hardware protocol stack.The designed scheme can be implemented easily,reduce cost significantly and shorten developing cycle.
基金supported in part by the National Natural Science Foundation of China under Grant 62201451in part by the Young Talent fund of University Association for Science and Technology in Shaanxi under Grant 20210121+1 种基金in part by the Shaanxi provincial special fund for Technological innovation guidance(2022CGBX-29)in part by BUPT Excellent Ph.D.Students Foundation under Grant CX2022106.
文摘This paper investigates the system outage performance of a simultaneous wireless information and power transfer(SWIPT)based two-way decodeand-forward(DF)relay network,where potential hardware impairments(HIs)in all transceivers are considered.After harvesting energy and decoding messages simultaneously via a power splitting scheme,the energy-limited relay node forwards the decoded information to both terminals.Each terminal combines the signals from the direct and relaying links via selection combining.We derive the system outage probability under independent but non-identically distributed Nakagami-m fading channels.It reveals an overall system ceiling(OSC)effect,i.e.,the system falls in outage if the target rate exceeds an OSC threshold that is determined by the levels of HIs.Furthermore,we derive the diversity gain of the considered network.The result reveals that when the transmission rate is below the OSC threshold,the achieved diversity gain equals the sum of the shape parameter of the direct link and the smaller shape parameter of the terminalto-relay links;otherwise,the diversity gain is zero.This is different from the amplify-and-forward(AF)strategy,under which the relaying links have no contribution to the diversity gain.Simulation results validate the analytical results and reveal that compared with the AF strategy,the SWIPT based two-way relaying links under the DF strategy are more robust to HIs and achieve a lower system outage probability.
文摘Nowadays, digital camera based remote controllers are widely used in people’s daily lives. It is known that the edge detection process plays an essential role in remote controlled applications. In this paper, a system verification platform of hardware optimization based on the edge detection is proposed. The Field-Programmable Gate Array (FPGA) validation is an important step in the Integrated Circuit (IC) design workflow. The Sobel edge detection algorithm is chosen and optimized through the FPGA verification platform. Hardware optimization techniques are used to create a high performance, low cost design. The Sobel edge detection operator is designed and mounted through the system Advanced High-performance Bus (AHB). Different FPGA boards are used for evaluation purposes. It is proved that with the proposed hardware optimization method, the hardware design of the Sobel edge detection operator can save 6% of on-chip resources for the Sobel core calculation and 42% for the whole frame calculation.
文摘This work presents a novel wavelet-based denoising technique for improving the signal-to-noise ratio(SNR)of nonsteady vibration signals in hardware redundant systems.The proposed method utilizes the relationship between redundant hardware components to effectively separate fault-related components from the vibration signature,thus enhancing fault detection accuracy.The study evaluates the proposed technique on two mechanically identical subsystems that are simultaneously controlled under the same speed and load inputs,with and without the proposed denoising step.The results demonstrate an increase in detection accuracy when incorporating the proposed denoising method into a fault detection system designed for hardware redundant machinery.This work is original in its application of a new method for improving performance when using residual analysis for fault detection in hardware redundant machinery configurations.Moreover,the proposed methodology is applicable to nonstationary equipment that experiences changes in both speed and load.
文摘The problems of current highly redundant flight control system are analyzed in this paper. Our study gives methods of utilizing other information to reduce physical components on the condition of meeting the reliability requirements for flight control system. The strategies presented in this paper mainly include information redundancy, multi-thread, time redundancy, geometry space redundancy, etc.. Analysis and simulation show these non-hardware based methods can reduce the requirement of system hardware level and thus reduce the system complexity, weight, space, costs and R＆D （research and development） time.
基金Supported by the National Natural Science Foundation of China(No.61179045 and No.61350009)
文摘In this paper, the storage capacity of communication among cores and processors is taken into account and a maximum D-value-first algorithm is proposed. By improving the hardware parallelism in the task execution process, the maximum storage requirements for communication are minimized. Experimental results with various directed acyclic graph models showed that compared with the earliest-task-first algorithm, the storage requirements for communication were reduced by 22.46%, on average, while the average of makespan only increased by 0.82%,.
基金Supported bythe National Basic Research Programof China (973 Program2004CB318201) the National Natural Sci-ence Foundation of China (60273074)
文摘A new task mode, hardware logic task mode, is presented. Its architecture, schedule and implementation are described with HDI.（ Hardware Description Language ）, and the validity of the system has been proved by logic simulation. It has advantage for real-time applications and overheadsaving for operating .system, so it is profitable for the controller in the embedded system. The relationship among RTOS （Real-Time Operating System）, SoC（System on Chip）, VIA （Virtual Interface Architecture） and hardware logic task is also discussed in the paper.
基金supported by the National Natural Science Foundation of China(Grant Nos.60832003)the Key Laboratory of Advanced Display and System Applications(Shanghai University),Ministry of Education,China(Grant No.P200801)the Science and Technology Commission of Shanghai Municipality(Grant No.10510500500)
文摘Depth estimation is an active research area with the developing of stereo vision in recent years. It is one of the key technologies to resolve the large data of stereo vision communication. Now depth estimation still has some problems, such as occlusion, fuzzy edge, real-time processing, etc. Many algorithms have been proposed base on software, however the performance of the computer configurations limits the software processing speed. The other resolution is hardware design and the great developments of the digital signal processor （DSP）, and application specific integrated circuit （ASIC） and field programmable gate array （FPGA） provide the opportunity of flexible applications. In this work, by analyzing the procedures of depth estimation, the proper algorithms which can be used in hardware design to execute real-time depth estimation are proposed. The different methods of calibration, matching and post-processing are analyzed based on the hardware design requirements. At last some tests for the algorithm have been analyzed. The results show that the algorithms proposed for hardware design can provide credited depth map for further view synthesis and are suitable for hardware design.
文摘Recently there has been great interest in the idea that evolvable system based on the principle of artifcial intelligence can be used to continuously and autonomously adapt the behaviour of physically embedded systems such as autonomous mobile robots and intelligent home devices. Meanwhile, we have seen the introduction of evolvable hardware(EHW): new integrated electronic circuits that are able to continuously evolve to adapt the chages in the environment implemented by evolutionary algorithms such as genetic algorithm(GA) and reinforcement learning. This paper concentrates on developing a robotic navigation system whose basic behaviours are obstacle avoidance and light source navigation. The results demonstrate that the intrinsic evolvable hardware system is able to create the stable robotiiuc behaviours as required in the real world instead of the traditional hardware systems.
文摘Nowadays, from home monitoring to large airport security, a lot of digital video surveillance systems have been used. Digital surveillance system usually requires streaming video processing abilities. As an advanced video coding method, H.264 is introduced to reduce the large video data dramatically (usually by 70X or more). However, computational overhead occurs when coding and decoding H.264 video. In this paper, a System-on-a-Chip (SoC) based hardware acceleration solution for video codec is proposed, which can also be used for other software applications. The characteristics of the video codec are analyzed by using the profiling tool. The Hadamard function, which is the bottleneck of H.264, is identified not only by execution time but also another two attributes, such as cycle per loop and loop round. The Co-processor approach is applied to accelerate the Hadamard function by transforming it to hardware. Performance improvement, resource costs and energy consumption are compared and analyzed. Experimental results indicate that 76.5% energy deduction and 8.09X speedup can be reached after balancing these three key factors.
文摘This paper deals with a new hardware/software embedded system design methodology based on design pattern approach by development of a new design tool called smartcell. Three main constraints of embedded systems design process are investigated: the complexity, the partitioning between hardware and software aspects and the reusability. Two intermediate models are carried out in order to solve the complexity problem. The partitioning problem deals with the proposed hardware/software partitioning algorithm based on Ant Colony Optimisation. The reusability problem is resolved by synthesis of intellectual property blocks. Specification and integration of an intelligent controller on heterogeneous platform are considered to illustrate the proposed approach.
文摘An embedded system generally comprises gffour parts （embedded microprocessor unit, peripheral hardware equipment, embedded operating system, and user application）, and its core function is to complete the control of different equipments as well as necessary monitoring and management measures. Initialization is to set a variable as ＂default value＂, including system initialization, software initialization and hardware initialization. However, these three types of initialization are classified in accordance with different layers. This is studied in this paper.
文摘Moving object detection including background subtraction and morphological processing is a critical research topic for video surveillance because of its high computational loading and power consumption. This paper proposes a hardware design to accelerate the computation of background subtraction with low power consumption. A real-time background subtraction method is designed with a frame-buffer scheme and function partition to improve throughput, and implemented using Verilog HDL on FPGA. The design parallelizes the computations of background update and subtraction with a seven-stage pipeline. A stripe-based morphological processing and accounting for the completion of detected objects is devised. Simulation results for videos of VGA resolutions on a low-end FPGA device show 368 fps throughput for only the real-time background subtraction module, and 51 fps for the whole system, including off-chip memory access. Real-time efficiency with low power consumption and low resource utilization is thus demonstrated.
基金Chongqing Engineering University Undergraduate Innovation and Entrepreneurship Training Program Project:Wireless Fire Automatic Alarm System(Project No.:CXCY2024017)Chongqing Municipal Education Commission Science and Technology Research Project:Development and Research of Chongqing Wireless Fire Automatic Alarm System(Project No.:KJQN202401906)。
文摘This article explores the design of a wireless fire alarm system supported by advanced data fusion technology.It includes discussions on the basic design ideas of the wireless fire alarm system,hardware design analysis,software design analysis,and simulation analysis,all supported by data fusion technology.Hopefully,this analysis can provide some reference for the rational application of data fusion technology to meet the actual design and application requirements of the system.
文摘This study analyzes the current situation of the practical teaching system of computer hardware courses in local undergraduate colleges,scrutinizes the experimental environment construction,contents,and methods of computer hardware courses,and proposes a new practical teaching system for computer hardware courses,so as to meet the needs of transformation and development as well as application-oriented talent training.
