A high-voltage p-LDMOS（HV-pMOS） with field-oxide as gate dielectric and a RESURF drain drift region to undertake high gate-source voltage and drain-source voltage for the scan driver chip of plasma display panels （...A high-voltage p-LDMOS（HV-pMOS） with field-oxide as gate dielectric and a RESURF drain drift region to undertake high gate-source voltage and drain-source voltage for the scan driver chip of plasma display panels （PDP） is purposed based on the epitaxial bipolar-CMOS-DMOS （BCD） process. The key considerations and parameters of the design are discussed：the thickness of gate dielectrics is 1mm and the area of the device is 80μm × 80μm. Only 18 photoetching steps are needed in the developed process,which is compatible with standard CMOS, bipolar, and VDMOS devices. The breakdown voltage of the HV-pMOS in the process control module （PCM） is more than 200V. The results are favorable for 170V PDP scan driver chips,which contribute to the competitive cost efficiency.展开更多
基金the National High Technology Research and Development Program of China(No.2003AA1Z1410)the Xi'an Science and Technology Planning Project(No.ZX04003)~~
文摘A high-voltage p-LDMOS（HV-pMOS） with field-oxide as gate dielectric and a RESURF drain drift region to undertake high gate-source voltage and drain-source voltage for the scan driver chip of plasma display panels （PDP） is purposed based on the epitaxial bipolar-CMOS-DMOS （BCD） process. The key considerations and parameters of the design are discussed：the thickness of gate dielectrics is 1mm and the area of the device is 80μm × 80μm. Only 18 photoetching steps are needed in the developed process,which is compatible with standard CMOS, bipolar, and VDMOS devices. The breakdown voltage of the HV-pMOS in the process control module （PCM） is more than 200V. The results are favorable for 170V PDP scan driver chips,which contribute to the competitive cost efficiency.
