This paper presents a method using simple physical vapour deposition to form high-quality hafnium silicon oxynitride （HfSiON） on ultrathin SiO2 buffer layer. The gate dielectric with 10A （1A = 0.1 nm） equivalent o...This paper presents a method using simple physical vapour deposition to form high-quality hafnium silicon oxynitride （HfSiON） on ultrathin SiO2 buffer layer. The gate dielectric with 10A （1A = 0.1 nm） equivalent oxide thickness is obtained. The experimental results indicate that the prepared HfSiON gate dielectric exhibits good physical and electrical characteristics, including very good thermal stability up to 1000℃, excellent interface properties, high dielectric constant （k = 14） and low gate-leakage current （Ig = 1.9 × 10^-3 A/cm^2@Vg = Vfb - 1 V for EOT of 10 A）. TaN metal gate electrode is integrated with the HfSiON gate dielectric.The effective work function of TaN on HfSiON is 4.3 eV, meeting the requirements of NMOS for the metal gate. And, the impacts of sputtering ambient and annealing temperature on the electrical properties of HfSiON gate dielectric are investigated.展开更多
Ge and Si p-channel metal-oxide-semiconductor field-effect-transistors （p-MOSFETs） with hafnium silicon oxynitride （HfSiON） gate dielectric and tantalum nitride （TAN） metal gate are fabricated. Self-isolated rin...Ge and Si p-channel metal-oxide-semiconductor field-effect-transistors （p-MOSFETs） with hafnium silicon oxynitride （HfSiON） gate dielectric and tantalum nitride （TAN） metal gate are fabricated. Self-isolated ring-type transistor structures with two masks are employed. W/TaN metal stacks are used as gate electrode and shadow masks of source/drain implantation separately. Capacitance-voltage curve hysteresis of Ge metal-oxide-semiconductor （MOS） capacitors may be caused by charge trapping centres in GeOx （1 〈 x 〈 2）. Effective hole mobilities of Ge and Si transistors are extracted by using a channel conductance method. The peak hole mobilities of Si and Ge transistors are 33.4 cm2/（V.s） and 81.0 cm2/（V.s）, respectively. Ge transistor has a hole mobility 2.4 times higher than that of Si control sample.展开更多
A gate-last process for fabricating HfSiON/TaN n-channel metal-oxide-semiconductor-field-effect transistors （NMOSFETs） is presented. In the process, a HfSiON gate dielectric with an equivalent oxide thickness of 10 ...A gate-last process for fabricating HfSiON/TaN n-channel metal-oxide-semiconductor-field-effect transistors （NMOSFETs） is presented. In the process, a HfSiON gate dielectric with an equivalent oxide thickness of 10 ？ was prepared by a simple physical vapor deposition method. Poly-Si was deposited on the HfSiON gate dielectric as a dummy gate. After the source/drain formation, the poly-Si dummy gate was removed by tetramethylammonium hydroxide （TMAH） wet-etching and replaced by a TaN metal gate. Because the metal gate was formed after the ion-implant doping activation process, the effects of the high temperature process on the metal gate were avoided. The fabricated device exhibits good electrical characteristics, including good driving ability and excellent sub-threshold characteristics. The device’s gate length is 73 nm, the driving current is 117 μA/μm under power supply voltages of VGS=VDS=1.5 V and the off-state current is only 4.4 nA/μ. The lower effective work function of TaN on HfSiON gives the device a suitable threshold voltage （～ 0.24 V） for high performance NMOSFETs. The device’s excellent performance indicates that this novel gate-last process is practical for fabricating high performance MOSFETs.展开更多
A novel dry etching process of a poly-Si/TaN/HfSiON gate stack for advanced complementary metal-oxide-semiconductor（CMOS） devices is investigated.Our strategy to process a poly-Si/TaN/HfSiON gate stack is that each ...A novel dry etching process of a poly-Si/TaN/HfSiON gate stack for advanced complementary metal-oxide-semiconductor（CMOS） devices is investigated.Our strategy to process a poly-Si/TaN/HfSiON gate stack is that each layer of gate stack is selectively etched with a vertical profile.First,a three-step plasma etching process is developed to get a vertical poly-Si profile and a reliable etch-stop on a TaN metal gate.Then different BCl_3-based plasmas are applied to etch the TaN metal gate and find that BCl_3/Cl_2/O_2/Ar plasma is a suitable choice to get a vertical TaN profile.Moreover,considering that Cl_2 almost has no selectivity to Si substrate, BCl_3/Ar plasma is applied to etch HfSiON dielectric to improve the selectivity to Si substrate after the TaN metal gate is vertically etched off by the optimized BCl_3/Cl_2/O_2/Ar plasma.Finally,we have succeeded in etching a poly-Si/TaN/HfSiON stack with a vertical profile and almost no Si loss utilizing these new etching technologies.展开更多
The wet etching properties ofa HfSiON high-k dielectric in HF-based solutions are investigated. HF-based solutions are the most promising wet chemistries for the removal of HfSiON, and etch selectivity of HF-based sol...The wet etching properties ofa HfSiON high-k dielectric in HF-based solutions are investigated. HF-based solutions are the most promising wet chemistries for the removal of HfSiON, and etch selectivity of HF-based solutions can be improved by the addition of an acid and/or an alcohol to the HF solution. Due to densification during annealing, the etch rate of HfSiON annealed at 900℃ for 30 s is significantly reduced compared with as-deposited HfSiON in HF-based solutions. After the HfSiON film has been completely removed by HF-based solutions, it is not possible to etch the interfacial layer and the etched surface does not have a hydrophobic nature, since N diffuses to the interface layer or Si substrate formation of SiN bonds that dissolves very slowly in HF-based solutions. Existing Si-N bonds at the interface between the new high-k dielectric deposit and the Si substrate may degrade the carrier mobility due to Coulomb scattering. In addition, we show that N2 plasma treatment before wet etching is not very effective in increasing the wet etch rate for a thin HfSiON film in our case.展开更多
基金supported by the State Key Development Program for Basic Research of China (Grant No 2006CB302704)the National Natural Science Foundation of China (Grant No 60776030)
文摘This paper presents a method using simple physical vapour deposition to form high-quality hafnium silicon oxynitride （HfSiON） on ultrathin SiO2 buffer layer. The gate dielectric with 10A （1A = 0.1 nm） equivalent oxide thickness is obtained. The experimental results indicate that the prepared HfSiON gate dielectric exhibits good physical and electrical characteristics, including very good thermal stability up to 1000℃, excellent interface properties, high dielectric constant （k = 14） and low gate-leakage current （Ig = 1.9 × 10^-3 A/cm^2@Vg = Vfb - 1 V for EOT of 10 A）. TaN metal gate electrode is integrated with the HfSiON gate dielectric.The effective work function of TaN on HfSiON is 4.3 eV, meeting the requirements of NMOS for the metal gate. And, the impacts of sputtering ambient and annealing temperature on the electrical properties of HfSiON gate dielectric are investigated.
基金Project supported by the National Basic Research Program of China (Grant No. 2006CB302704)
文摘Ge and Si p-channel metal-oxide-semiconductor field-effect-transistors （p-MOSFETs） with hafnium silicon oxynitride （HfSiON） gate dielectric and tantalum nitride （TAN） metal gate are fabricated. Self-isolated ring-type transistor structures with two masks are employed. W/TaN metal stacks are used as gate electrode and shadow masks of source/drain implantation separately. Capacitance-voltage curve hysteresis of Ge metal-oxide-semiconductor （MOS） capacitors may be caused by charge trapping centres in GeOx （1 〈 x 〈 2）. Effective hole mobilities of Ge and Si transistors are extracted by using a channel conductance method. The peak hole mobilities of Si and Ge transistors are 33.4 cm2/（V.s） and 81.0 cm2/（V.s）, respectively. Ge transistor has a hole mobility 2.4 times higher than that of Si control sample.
基金Project supported by the Beijing Natural Science Foundation,China(Grant No.4123106)the National Science and Technology Major Projects of the Ministry of Science and Technology of China(Grant No.2009ZX02035)
文摘A gate-last process for fabricating HfSiON/TaN n-channel metal-oxide-semiconductor-field-effect transistors （NMOSFETs） is presented. In the process, a HfSiON gate dielectric with an equivalent oxide thickness of 10 ？ was prepared by a simple physical vapor deposition method. Poly-Si was deposited on the HfSiON gate dielectric as a dummy gate. After the source/drain formation, the poly-Si dummy gate was removed by tetramethylammonium hydroxide （TMAH） wet-etching and replaced by a TaN metal gate. Because the metal gate was formed after the ion-implant doping activation process, the effects of the high temperature process on the metal gate were avoided. The fabricated device exhibits good electrical characteristics, including good driving ability and excellent sub-threshold characteristics. The device’s gate length is 73 nm, the driving current is 117 μA/μm under power supply voltages of VGS=VDS=1.5 V and the off-state current is only 4.4 nA/μ. The lower effective work function of TaN on HfSiON gives the device a suitable threshold voltage （～ 0.24 V） for high performance NMOSFETs. The device’s excellent performance indicates that this novel gate-last process is practical for fabricating high performance MOSFETs.
基金Project supported by the Special Funds for Major State Basic Research Projects,China(No.2006CB302704 )the National Natural Science Foundation of China(No.60776030)
文摘A novel dry etching process of a poly-Si/TaN/HfSiON gate stack for advanced complementary metal-oxide-semiconductor（CMOS） devices is investigated.Our strategy to process a poly-Si/TaN/HfSiON gate stack is that each layer of gate stack is selectively etched with a vertical profile.First,a three-step plasma etching process is developed to get a vertical poly-Si profile and a reliable etch-stop on a TaN metal gate.Then different BCl_3-based plasmas are applied to etch the TaN metal gate and find that BCl_3/Cl_2/O_2/Ar plasma is a suitable choice to get a vertical TaN profile.Moreover,considering that Cl_2 almost has no selectivity to Si substrate, BCl_3/Ar plasma is applied to etch HfSiON dielectric to improve the selectivity to Si substrate after the TaN metal gate is vertically etched off by the optimized BCl_3/Cl_2/O_2/Ar plasma.Finally,we have succeeded in etching a poly-Si/TaN/HfSiON stack with a vertical profile and almost no Si loss utilizing these new etching technologies.
基金supported by the Special Funds for Major State Basic Research Projects(No.2006CB302704)the National Natural Science Foundation of China(No.60776030).
文摘The wet etching properties ofa HfSiON high-k dielectric in HF-based solutions are investigated. HF-based solutions are the most promising wet chemistries for the removal of HfSiON, and etch selectivity of HF-based solutions can be improved by the addition of an acid and/or an alcohol to the HF solution. Due to densification during annealing, the etch rate of HfSiON annealed at 900℃ for 30 s is significantly reduced compared with as-deposited HfSiON in HF-based solutions. After the HfSiON film has been completely removed by HF-based solutions, it is not possible to etch the interfacial layer and the etched surface does not have a hydrophobic nature, since N diffuses to the interface layer or Si substrate formation of SiN bonds that dissolves very slowly in HF-based solutions. Existing Si-N bonds at the interface between the new high-k dielectric deposit and the Si substrate may degrade the carrier mobility due to Coulomb scattering. In addition, we show that N2 plasma treatment before wet etching is not very effective in increasing the wet etch rate for a thin HfSiON film in our case.
文摘随着微电子技术的不断发展,MOSFET 的特征尺寸已缩小至100nm 以下,SiO_2作为栅介质材料已不能满足技术发展的需求,因此必须寻求一种新型高 K 的介质材料来取代 SiO_2。当今普遍认为 Hf 基栅介质材料是最有希望取代 SiO_2而成为下一代 MOSFET 的栅介质材料。综述了高 K 栅介质材料的意义、Hf 基高 K 栅介质材料的最新研究进展和 Hf 基高 K 栅介质材料在克服自身缺陷时使用的一些技术;介绍了一款由 Hf 基高 K 介质材料作为栅绝缘层制作的 MOSFET。
