In this work, we investigate the back-gate I-V characteristics for two kinds of NMOSFET/SIMOX transistors with H gate structure fabricated on two different SOI wafers. A transistors are made on the wafer implanted wit...In this work, we investigate the back-gate I-V characteristics for two kinds of NMOSFET/SIMOX transistors with H gate structure fabricated on two different SOI wafers. A transistors are made on the wafer implanted with Si^＋ and then annealed in N2, and B transistors are made on the wafer without implantation and annealing. It is demonstrated experimentally that A transistors have much less back-gate threshold voltage shift △Vth than B transistors under X-ray total dose irradiation. Subthreshold charge separation technique is employed to estimate the build-up of oxide charge and interface traps during irradiation, showing that the reduced AVth for A transistors is mainly due to its less build-up of oxide charge than B transistors. Photo- luminescence （PL） research indicates that Si implantation results in the formation of silicon nanocrystalline （nanocluster） whose size increases with the implant dose. This structure can trap electrons to compensate the positive charge build-up in the buried oxide during irradiation, and thus reduce the threshold voltage negative shift.展开更多
为提高空间环境下电子设备的可靠性,提升抗辐射加固SOI(Silicon on Insulator)集成电路的设计效率,通过构建完整的建库流程,自主设计开发了基于3.3V-0.35μm-PD(Partly)SOI CMOS(ComplementaryMetal-Semiconductor)工艺平台,并面向Synop...为提高空间环境下电子设备的可靠性,提升抗辐射加固SOI(Silicon on Insulator)集成电路的设计效率,通过构建完整的建库流程,自主设计开发了基于3.3V-0.35μm-PD(Partly)SOI CMOS(ComplementaryMetal-Semiconductor)工艺平台,并面向Synopsys电子设计自动化软件的抗辐射加固标准单元库。标准单元采用H型栅及源漏非对称注入结构,以提高抗辐射性能,最后对该单元库进行了电子设计自动化工具流程验证和测试验证。实验结果表明,检错纠错验证电路功能符合设计要求,抗总剂量水平大于300krad(Si)。展开更多
文摘In this work, we investigate the back-gate I-V characteristics for two kinds of NMOSFET/SIMOX transistors with H gate structure fabricated on two different SOI wafers. A transistors are made on the wafer implanted with Si^＋ and then annealed in N2, and B transistors are made on the wafer without implantation and annealing. It is demonstrated experimentally that A transistors have much less back-gate threshold voltage shift △Vth than B transistors under X-ray total dose irradiation. Subthreshold charge separation technique is employed to estimate the build-up of oxide charge and interface traps during irradiation, showing that the reduced AVth for A transistors is mainly due to its less build-up of oxide charge than B transistors. Photo- luminescence （PL） research indicates that Si implantation results in the formation of silicon nanocrystalline （nanocluster） whose size increases with the implant dose. This structure can trap electrons to compensate the positive charge build-up in the buried oxide during irradiation, and thus reduce the threshold voltage negative shift.
文摘设计了一种用于D类音频功率放大器中产生死区时间的互锁电路,通过对功率管的输出状态进行检测,使得在每种状态下只有一个功率管导通,有效地防止了上下功率管的同时导通,从而减小了功率级的损耗,提高了放大器的效率.针对该互锁电路提出了一种死区时间设计方法,使得在有效抑制功率管导通的同时引入最小的失真,同时对引入死区时间所产生的影响做了详细分析.仿真结果表明:该互锁电路在输出信号的上升沿产生的死区时间为13.6 ns,在输出信号的下降沿产生的死区时间为15.5 ns.
文摘为提高空间环境下电子设备的可靠性,提升抗辐射加固SOI(Silicon on Insulator)集成电路的设计效率,通过构建完整的建库流程,自主设计开发了基于3.3V-0.35μm-PD(Partly)SOI CMOS(ComplementaryMetal-Semiconductor)工艺平台,并面向Synopsys电子设计自动化软件的抗辐射加固标准单元库。标准单元采用H型栅及源漏非对称注入结构,以提高抗辐射性能,最后对该单元库进行了电子设计自动化工具流程验证和测试验证。实验结果表明,检错纠错验证电路功能符合设计要求,抗总剂量水平大于300krad(Si)。
