In order to increase the hardware utilization and minimize the chip area a multi-transform coding architecture which includes 4 ×4 forward integer transform 4 ×4 inverse integer transform 4 ×4 Hadamard ...In order to increase the hardware utilization and minimize the chip area a multi-transform coding architecture which includes 4 ×4 forward integer transform 4 ×4 inverse integer transform 4 ×4 Hadamard transform and 2 ×2 Hadamard transform is proposed. By simplifying these transforms and exploring their similarities the proposed design merges the architectures processing individual transforms into a high-performance multi-transform coding architecture.Using a semiconductor manufacturing international corporation SMIC 0.18 μm complementary metal oxide semiconductor CMOS technology the proposed architecture achieves the maximum operating clock frequency of 200 MHz and the throughput rate of 800 ×106 pixel/s with the hardware cost of 3 704 gates.The results demonstrate that the data throughput rate per unit area DTUA of this design is at least 40.28%higher than that of the reference design.This design can meet the requirements of real-time decoding digital cinema video 4 096 ×2 048@30 Hz at 62.9 MHz which helps to reduce the power consumption.展开更多
作为视频通信中非常重要的关键技术之一,码率控制用于调整视频码流以满足带宽受限的条件,能够直接影响视频编码器输出码率的稳定性和保证视频质量。首先描述码率控制问题,给出码率控制算法的分类准则;然后对众多的H.264/先进视频编码(ad...作为视频通信中非常重要的关键技术之一,码率控制用于调整视频码流以满足带宽受限的条件,能够直接影响视频编码器输出码率的稳定性和保证视频质量。首先描述码率控制问题,给出码率控制算法的分类准则;然后对众多的H.264/先进视频编码(advanced video coding,AVC)码率控制算法根据应用目的进行具体描述;最后从适用标准和应用目的两个方面,详细指出码率控制技术今后的研究方向。展开更多
基金The National Key Technology R&D Program of China during the 12th Five Year Plan Period(No.2013BAJ05B03)
文摘In order to increase the hardware utilization and minimize the chip area a multi-transform coding architecture which includes 4 ×4 forward integer transform 4 ×4 inverse integer transform 4 ×4 Hadamard transform and 2 ×2 Hadamard transform is proposed. By simplifying these transforms and exploring their similarities the proposed design merges the architectures processing individual transforms into a high-performance multi-transform coding architecture.Using a semiconductor manufacturing international corporation SMIC 0.18 μm complementary metal oxide semiconductor CMOS technology the proposed architecture achieves the maximum operating clock frequency of 200 MHz and the throughput rate of 800 ×106 pixel/s with the hardware cost of 3 704 gates.The results demonstrate that the data throughput rate per unit area DTUA of this design is at least 40.28%higher than that of the reference design.This design can meet the requirements of real-time decoding digital cinema video 4 096 ×2 048@30 Hz at 62.9 MHz which helps to reduce the power consumption.
文摘作为视频通信中非常重要的关键技术之一,码率控制用于调整视频码流以满足带宽受限的条件,能够直接影响视频编码器输出码率的稳定性和保证视频质量。首先描述码率控制问题,给出码率控制算法的分类准则;然后对众多的H.264/先进视频编码(advanced video coding,AVC)码率控制算法根据应用目的进行具体描述;最后从适用标准和应用目的两个方面,详细指出码率控制技术今后的研究方向。
