The Ocean 4A scatterometer, expected to be launched in 2024, is poised to be the world’s first spaceborne microwave scatterometer utilizing a digital beamforming system. To ensure high-precision measurements and perf...The Ocean 4A scatterometer, expected to be launched in 2024, is poised to be the world’s first spaceborne microwave scatterometer utilizing a digital beamforming system. To ensure high-precision measurements and performance sta-bility across diverse environments, stringent requirements are placed on the dynamic range of its receiving system. This paper provides a detailed exposition of a field-programmable gate array (FPGA)-based automatic gain control (AGC) design for the spaceborne scatterometer. Implemented on an FPGA, the algo-rithm harnesses its parallel processing capabilities and high-speed performance to monitor the received echo signals in real time. Employing an adaptive AGC algorithm, the system gene-rates gain control codes applicable to the intermediate fre-quency variable attenuator, enabling rapid and stable adjust-ment of signal amplitudes from the intermediate frequency amplifier to an optimal range. By adopting a purely digital pro-cessing approach, experimental results demonstrate that the AGC algorithm exhibits several advantages, including fast con-vergence, strong flexibility, high precision, and outstanding sta-bility. This innovative design lays a solid foundation for the high-precision measurements of the Ocean 4A scatterometer, with potential implications for the future of spaceborne microwave scatterometers.展开更多
A novel wide-range CMOS variable gain amplifier （VGA） topology is presented. The proposed VGA is composed of a variable transconductor and a novel variable output resistor and can offer a high gain variation range o...A novel wide-range CMOS variable gain amplifier （VGA） topology is presented. The proposed VGA is composed of a variable transconductor and a novel variable output resistor and can offer a high gain variation range of 80dB while using a single variable-gain stage. Temperature-compensation and decibel-linear gain characteristic are achieved by using a control circuit that provides a gain error lower than ±1.5dB over the full temperature and gain ranges. Realized in 0.25μm CMOS technology, a prototype of the proposed VGA provides a total gain range of 64.5dB with 55.6dB-linear range,a P-1dB varying from - 17.5 to 11.5dBm,and a 3dB-bandwith varying from 65 to 860MHz while dissipating 16.5mW from a 2.5V supply voltage.展开更多
This paper presented an automatic gain control （AGC） circuit suitable for FM/cw ladar. The proposed architecture was based on two-stage variable gain amplifier （VGA） chain with a novel DC offset canceller circuit,...This paper presented an automatic gain control （AGC） circuit suitable for FM/cw ladar. The proposed architecture was based on two-stage variable gain amplifier （VGA） chain with a novel DC offset canceller circuit, which contained an improved Gilbert cell and a Gm-C feedback loop. To keep the VGA with a linearity in dB characteristic, an improved exponential gain control circuit was introduced. The AGC was implemented in 0.18 gm standard CMOS process. Simulation and measurement results verified that its gain ranged from -20 dB to 30 dB, and band- width ranged from 100 kHz to 10 MHz. Its power consumption was 19.8 mW under a voltage supply of 3.3 V.展开更多
This work presents modelling aspects of automatic gain control （AGC） loops based on linear-in-dB variable gain amplifiers （VGAs）. In these loops, the VGA control voltage is also an excellent received signal streng...This work presents modelling aspects of automatic gain control （AGC） loops based on linear-in-dB variable gain amplifiers （VGAs）. In these loops, the VGA control voltage is also an excellent received signal strength indicator （RSSI）. The VGA gain is however nonlinearly related to the control voltage. Moreover, VGAs and detectors undergo nonlinear compression under high input amplitudes during settling transients. The main contribution in this work is a proposed nonlinear model based on simple and readily available components from the ＂analogLib＂ and ＂functional＂ libraries in CADENCE design environment -making it very easy and fast to build and simulate-that captures the nonlinear effects of AGC loops. The model is capable of verifying the AGC loop stability and capturing the loop dynamics with high accuracy compared to time consuming circuit level simulations. This provides insights into system level parameters such as AGC loop bandwidth, phase margin, settling time as well as estimating the AGC range and RSSI voltage vs. input power. Measurement results from a fabricated AGC prototype are in good agreement with simulation and modelling results thus validating the proposed modelling approach.展开更多
High signal-to-noise ratio can be achieved with the electron multiplying charge-coupled-device（EMCCD） applied in the Shack–Hartmann wavefront sensor（S–H WFS） in adaptive optics（AO）.However,when the brightness ...High signal-to-noise ratio can be achieved with the electron multiplying charge-coupled-device（EMCCD） applied in the Shack–Hartmann wavefront sensor（S–H WFS） in adaptive optics（AO）.However,when the brightness of the target changes in a large scale,the fixed electron multiplying（EM） gain will not be suited to the sensing limitation.Therefore an auto-gain-control method based on the brightness of light-spots array in S–H WFS is proposed in this paper.The control value is the average of the maximum signals of every light spot in an array,which has been demonstrated to be kept stable even under the influence of some noise and turbulence,and sensitive enough to the change of target brightness.A goal value is needed in the control process and it is predetermined based on the characters of EMCCD.Simulations and experiments have demonstrated that this auto-gain-control method is valid and robust,the sensing SNR reaches the maximum for the corresponding signal level,and especially is greatly improved for those dim targets from 6 to 4 magnitude in the visual band.展开更多
A low noise distributed amplifier consisting of 9 gain cells is presented.The chip is fabricated with 0.15-μm GaAs pseudomorphic high electron mobility transistor（PHEMT） technology from Win Semiconductor of Taiwan....A low noise distributed amplifier consisting of 9 gain cells is presented.The chip is fabricated with 0.15-μm GaAs pseudomorphic high electron mobility transistor（PHEMT） technology from Win Semiconductor of Taiwan.A special optional gate bias technique is introduced to allow an adjustable gain control range of 10 dB.A novel cascode structure is adopted to extend the output voltage and bandwidth.The measurement results show that the amplifier gives an average gain of 15 dB with a gain flatness of±1 dB in the 2-20 GHz band.The noise figure is between 2 and 4.1 dB during the band from 2 to 20 GHz.The amplifier also provides 13.8 dBm of output power at a 1 dB gain compression point and 10.5 dBm of input third order intercept point（IIP3）,which demonstrates the excellent performance of linearity.The power consumption is 300 mW with a supply of 5 V,and the chip area is 2.36×1.01 mm^2.展开更多
Gain-scheduling has got its wide applications in modern flight control, in which control gains are scheduled with variables such as dynamic pressure and Mach number, to meet dynamic response requirements in different ...Gain-scheduling has got its wide applications in modern flight control, in which control gains are scheduled with variables such as dynamic pressure and Mach number, to meet dynamic response requirements in different flight conditions. Classical gain-scheduling approaches may result in some problems, which can not guarantee global robustness and stability in transitions of different flight conditions. Gain-scheduling problem is systematically investigated from robustness point of view in the paper. Detailed procedures for gain-scheduled controller to achieve both robustness and stability performance are given and applied to a typical flight control system. For switching stability problems of different flight conditions in flight control systems, a new approach is proposed, in which different flight conditions are reduced into a parameter varying plant using interpolation firstly, and then parameter-varying controller design goes next. Though interpolation errors may exist, the robust parameter varying controller design can compensate for those uncertainties and errors, and finally achieve good performance of robustness and switching stability during transitions. Illustrative simulation at last shows satisfactory results.展开更多
This paper proposes a fast-locking bang-bang phase-locked loop（BBPLL）. A novel adaptive loop gain controller（ALGC） is proposed to increase the locking speed of the BBPLL. A novel bang-bang phase/frequency detector...This paper proposes a fast-locking bang-bang phase-locked loop（BBPLL）. A novel adaptive loop gain controller（ALGC） is proposed to increase the locking speed of the BBPLL. A novel bang-bang phase/frequency detector（BBPFD） with adaptive-mode-selective circuits is proposed to select the locking mode of the BBPLL during the locking process. Based on the detected results of the BBPFD, the ALGC can dynamically adjust the overall gain of the loop for fast-locking procedure. Compared with the conventional BBPFD, only a few gates are added in the proposed BBPFD. Therefore, the proposed BBPFD with adaptive-mode-selective circuits is realized with little area and power penalties. The fast-locking BBPLL is implemented in a 65 nm CMOS technology. The core area of the BBPLL is 0.022 mm;. Measured results show that the BBPLL operates at a frequency range from0.6 to 2.4 GHz. When operating at 1.8 GHz, the power consumption is 3.1 mW with a 0.9-V supply voltage. With the proposed techniques, the BBPLL achieves a normalized locked time of 1.1μs @ 100 MHz frequency jump.The figure-of-merit of the fast-locking BBPLL is-334 dB.展开更多
Automatic gain control （AGC） has been used in many applications. The key features of AGC, including a steady state output and static/dynamic timing response, depend mainly on key parameters such as the reference and...Automatic gain control （AGC） has been used in many applications. The key features of AGC, including a steady state output and static/dynamic timing response, depend mainly on key parameters such as the reference and the filter coefficients. A simple model developed to describe AGC systems based on several simple assumptions shows that AGC always converges to the reference and that the timing constant depends on the filter coefficients. Measures are given to prevent oscillations and limit cycle effects. The simple AGC system is adapted to a multiple AGC system for a TV tuner in a much more efficient model. Simulations using the C language are 16 times faster than those with MATLAB, and 10 times faster than those with a mixed register transfer level （RTL）-simulation program with integrated circuit emphasis （SPICE） model.展开更多
A differential automatic gain control （AGC） circuit is presented. The AGC architecture contains twostage variable gain amplifiers （VGAs） which are implemented with a Gilbert cell, a peak detector （PD）, a low pas...A differential automatic gain control （AGC） circuit is presented. The AGC architecture contains twostage variable gain amplifiers （VGAs） which are implemented with a Gilbert cell, a peak detector （PD）, a low pass filter, an operational amplifier, and two voltage to current （V-I） convertors. One stage VGA achieves 30 dB gain due to the use of active load. The AGC circuit is implemented in UMC 0.18-um single-poly six-metal CMOS process technology. Measurement results show that the final differential output swing of the 2nd stage VGA is about 0.9-Vpp; the total gain of the two VGAs can be varied linearly from -10 to 50 dB when the control voltage varies from 0.3 to 0.9 V. The final circuit （containing output buffers and a band-gap reference） consumes 37 mA from single 1.8 V voltage supply. For a 50 mV amplitude 60% modulation depth input AM signal it needs 100 us to stabilize the output. The frequency response of the circuit has almost a constant -3 dB bandwidth of 2.2 MHz. Its OIP3 result is at 19 dBm.展开更多
A low-power, configurable auto-gain control loop for a digital hearing aid system on a chip （SoC） is presented. By adopting a mixed-signal feedback control structure and peak detection and judgment, it can work in a...A low-power, configurable auto-gain control loop for a digital hearing aid system on a chip （SoC） is presented. By adopting a mixed-signal feedback control structure and peak detection and judgment, it can work in automatic gain or variable gain control modes through a digital signal processing unit. A noise-reduction and dynamic range （DR） improvement technique is also used to ensure the DR of the circuit in a low-voltage supply. The circuit is implemented in an SMIC 0.13 μm 1P8M CMOS process. The measurement results show that in a I V power supply, 1.6 kHz input frequency and 200 mVp-p, the SFDR is 74.3 dB, the THD is 66.1 dB, and the total power is 89 μW, meeting the application requirements of hearing aid SoCs.展开更多
This paper presents the design and implementation of a digitally calibrated CMOS wideband radio frequency(RF) root-mean-square(RMS) power detector for high accuracy RF automatic gain control(AGC).The proposed RMS powe...This paper presents the design and implementation of a digitally calibrated CMOS wideband radio frequency(RF) root-mean-square(RMS) power detector for high accuracy RF automatic gain control(AGC).The proposed RMS power detector demonstrates accurate power detection in the presence of process,supply voltage, and temperature(PVT) variations by employing a digital calibration scheme.It also consumes low power and occupies a small chip area.The measurement results show that the scheme improves the accuracy of the detector to better than 0.3 dB over the PVT variations and wide operating frequency range from 0.2 to 0.8 GHz.Implemented in a 0.18μm CMOS process and occupying a small die area of 263×214μm^2,the proposed digitally calibrated CMOS RMS power detector only consumes 1.6 mA in power detection mode and 2.1 mA in digital calibration mode from a 1.8 V supply voltage.展开更多
A current mode feed-forward gain control（CMFGC）technique is presented,which is applied in the front-end system of a hearing aid chip.Compared with conventional automatic gain control（AGC）,CMFGC significantly impro...A current mode feed-forward gain control（CMFGC）technique is presented,which is applied in the front-end system of a hearing aid chip.Compared with conventional automatic gain control（AGC）,CMFGC significantly improves the total harmonic distortion（THD）by digital gain control.To attain the digital gain control codes according to the extremely weak output signal from the microphone,a rectifier and a state controller implemented in current mode are proposed.A prototype chip has been designed based on a 0.13μm standard CMOS process.The measurement results show that the supply voltage can be as low as 0.6 V.And with the 0.8 V supply voltage,the THD is improved and below 0.06%（-64 dB）at the output level of 500 mV_（p-p）,yet the power consumption is limited to 40μW.In addition,the input referred noise is only 4μV_（rms）and the maximum gain is maintained at 33 dB.展开更多
An analog/digital reconfigurable automatic gain control （AGC） circuit with a novel DC offset cancel- lation circuit for a direct-conversion receiver is presented. The AGC is analog/digital reconfigurable in order to...An analog/digital reconfigurable automatic gain control （AGC） circuit with a novel DC offset cancel- lation circuit for a direct-conversion receiver is presented. The AGC is analog/digital reconfigurable in order to be compatible with different baseband chips. What＇s more, a novel DC offset cancellation （DCOC） circuit with an HPCF （high pass cutoff frequency） less than 10 kHz is proposed. The AGC is fabricated by a 0.18μm CMOS process. Under analog control mode, the AGC achieves a 70 dB dynamic range with a 3 dB-bandwidth larger than 60 MHz. Under digital control mode, through a 5-bit digital control word, the AGC shows a 64 dB gain control range by 2 dB each step with a gain error of less than 0.3 dB. The DC offset cancellation circuits can suppress the output DC offset voltage to be less than 1.5 mV, while the offset voltage of 40 mV is introduced into the input. The overall power consumption is less than 3.5 mA, and the die area is 800 ×300μm2.展开更多
An output amplitude configurable wideband automatic gain control（AGC） with high gain step accuracy for the GNSS receiver is presented.The amplitude of an AGC is configurable in order to cooperate with baseband chips...An output amplitude configurable wideband automatic gain control（AGC） with high gain step accuracy for the GNSS receiver is presented.The amplitude of an AGC is configurable in order to cooperate with baseband chips to achieve interference suppression and be compatible with different full range ADCs.And what’s more,the gain-boosting technology is introduced and the circuit is improved to increase the step accuracy.A zero,which is composed by the source feedback resistance and the source capacity,is introduced to compensate for the pole.The AGC is fabricated in a 0.18μm CMOS process.The AGC shows a 62 dB gain control range by 1 dB each step with a gain error of less than 0.2 dB.The AGC provides 3 dB bandwidth larger than 80 MHz and the overall power consumption is less than 1.8 mA,and the die area is 800 x 300μm^2.展开更多
This paper proposes a new structure to lower the power consumption of a variable gain amplifier（VGA） and keep the linearity of the VGA unchanged.The structure is used in a high rate amplitude-shift keying（ASK） bas...This paper proposes a new structure to lower the power consumption of a variable gain amplifier（VGA） and keep the linearity of the VGA unchanged.The structure is used in a high rate amplitude-shift keying（ASK） based IF-stage.It includes an automatic gain control（AGC） loop and ASK demodulator.The AGC mainly consists of sixstage VGAs.The IF-stage is realized in 0.18μm CMOS technology.The measurement results show that the power consumption of the whole system is very low.The system consumes 730μA while operating at 1.8 V.The minimum ASK signal the system could detect is 0.7 mV（peak to peak amplitude）.展开更多
The fundamental challenges for full-duplex(FD)relay networks are the self-interference cancellation(SIC)and the cooperative transmission design at the relay.This paper presents a practical amplify-and-forward(AF)FD on...The fundamental challenges for full-duplex(FD)relay networks are the self-interference cancellation(SIC)and the cooperative transmission design at the relay.This paper presents a practical amplify-and-forward(AF)FD one-way relay scheme for orthogonal frequency division multiplexing(OFDM)transmission with multi-domain SIC.It is found that the residual self-interference(SI)signals at the relay can be regarded as an equivalent multipath model.The effects of the residual sI at the relay are incorporated into the equivalent end-to-end channel model,and the inter-block interference can be removed at the destination by using cyclic prefix(CP)protection.Based on the equivalent multipath model,we present a solution for optimizing the amplification factor on the performance of signal-to-interference-plus-noise ratio(SINR)when the equivalent multipath length is longer than the CP.Furthermore,a practical one way FD relay network with 3 nodes is built and measured.The simulation and measured results verify the superior performance of the proposed scheme.展开更多
Consider the design and implementation of an electro-hydraulic control system for a robotic excavator, namely the Lancaster University computerized and intelligent excavator (LUCIE). The excavator was developed to aut...Consider the design and implementation of an electro-hydraulic control system for a robotic excavator, namely the Lancaster University computerized and intelligent excavator (LUCIE). The excavator was developed to autonomously dig trenches without human intervention. One stumbling block is the achievement of adequate, accurate, quick and smooth movement under automatic control, which is difficult for traditional control algorithm, e.g. PI/PID. A gain scheduling design, based on the true digital proportional-integral-plus (PIP) control methodology, was utilized to regulate the nonlinear joint dynamics. Simulation and initial field tests both demonstrated the feasibility and robustness of proposed technique to the uncertainties of parameters, time delay and load disturbances, with the excavator arm directed along specified trajectories in a smooth, fast and accurate manner. The tracking error magnitudes for oblique straight line and horizontal straight line are less than 20 mm and 50 mm, respectively, while the velocity reaches 9 m/min.展开更多
This paper proposes an adaptive augmentation control design approach of the gain-scheduled controller.This extension is motivated by the need for augmentation of the baseline gainscheduled controller.The proposed appr...This paper proposes an adaptive augmentation control design approach of the gain-scheduled controller.This extension is motivated by the need for augmentation of the baseline gainscheduled controller.The proposed approach can be utilized to design flight control systems for advanced aerospace vehicles with a large parameter variation.The flight dynamics within the flight envelope is described by a switched nonlinear system,which is essentially a switched polytopic system with uncertainties.The flight control system consists of a baseline gain-scheduled controller and a model reference adaptive augmentation controller,while the latter can recover the nominal performance of the gainscheduled controlled system under large uncertainties.By the multiple Lyapunov functions method,it is proved that the switched nonlinear system is uniformly ultimately bounded.To validate the effectiveness of the proposed approach,this approach is applied to a generic hypersonic vehicle,and the simulation results show that the system output tracks the command signal well even when large uncertainties exist.展开更多
This article investigates gain self-scheduled H 1 robust control system design for a tailless fold- ing-wing morphing aircraft in the wing shape varying process. During the wing morphing phase, the aircraft＇s dynamic...This article investigates gain self-scheduled H 1 robust control system design for a tailless fold- ing-wing morphing aircraft in the wing shape varying process. During the wing morphing phase, the aircraft＇s dynamic response will be governed by time-varying aerodynamic forces and moments. Nonlinear dynamic equations of the morphing aircraft are linearized by using Jacobian linearization approach, and a linear parameter varying （LPV） model of the morphing aircraft in wing folding is obtained. A multi-loop controller for the morphing aircraft is formulated to guarantee stability for the wing shape transition process. The proposed controller uses a set of inner-loop gains to provide stability using classical techniques, whereas a gain self-scheduled H 1 outer-loop controller is devised to guarantee a specific level of robust stability and performance for the time-varying dynamics. The closed-loop simulations show that speed and altitude vary slightly during the whole wing folding process, and they converge rapidly after the process ends. This proves that the gain self-scheduled H 1 robust controller can guarantee a satisfactory dynamic performance for the morphing aircraft during the whole wing shape transition process. Finally, the flight control system＇s robustness for the wing folding process is verified according to uncertainties of the aerodynamic parameters in the nonlinear model.展开更多
文摘The Ocean 4A scatterometer, expected to be launched in 2024, is poised to be the world’s first spaceborne microwave scatterometer utilizing a digital beamforming system. To ensure high-precision measurements and performance sta-bility across diverse environments, stringent requirements are placed on the dynamic range of its receiving system. This paper provides a detailed exposition of a field-programmable gate array (FPGA)-based automatic gain control (AGC) design for the spaceborne scatterometer. Implemented on an FPGA, the algo-rithm harnesses its parallel processing capabilities and high-speed performance to monitor the received echo signals in real time. Employing an adaptive AGC algorithm, the system gene-rates gain control codes applicable to the intermediate fre-quency variable attenuator, enabling rapid and stable adjust-ment of signal amplitudes from the intermediate frequency amplifier to an optimal range. By adopting a purely digital pro-cessing approach, experimental results demonstrate that the AGC algorithm exhibits several advantages, including fast con-vergence, strong flexibility, high precision, and outstanding sta-bility. This innovative design lays a solid foundation for the high-precision measurements of the Ocean 4A scatterometer, with potential implications for the future of spaceborne microwave scatterometers.
文摘A novel wide-range CMOS variable gain amplifier （VGA） topology is presented. The proposed VGA is composed of a variable transconductor and a novel variable output resistor and can offer a high gain variation range of 80dB while using a single variable-gain stage. Temperature-compensation and decibel-linear gain characteristic are achieved by using a control circuit that provides a gain error lower than ±1.5dB over the full temperature and gain ranges. Realized in 0.25μm CMOS technology, a prototype of the proposed VGA provides a total gain range of 64.5dB with 55.6dB-linear range,a P-1dB varying from - 17.5 to 11.5dBm,and a 3dB-bandwith varying from 65 to 860MHz while dissipating 16.5mW from a 2.5V supply voltage.
基金Supported by the National Science and Technology Major Project of the Ministry of Science and Technology of China(No.2012ZX03004008)
文摘This paper presented an automatic gain control （AGC） circuit suitable for FM/cw ladar. The proposed architecture was based on two-stage variable gain amplifier （VGA） chain with a novel DC offset canceller circuit, which contained an improved Gilbert cell and a Gm-C feedback loop. To keep the VGA with a linearity in dB characteristic, an improved exponential gain control circuit was introduced. The AGC was implemented in 0.18 gm standard CMOS process. Simulation and measurement results verified that its gain ranged from -20 dB to 30 dB, and band- width ranged from 100 kHz to 10 MHz. Its power consumption was 19.8 mW under a voltage supply of 3.3 V.
文摘This work presents modelling aspects of automatic gain control （AGC） loops based on linear-in-dB variable gain amplifiers （VGAs）. In these loops, the VGA control voltage is also an excellent received signal strength indicator （RSSI）. The VGA gain is however nonlinearly related to the control voltage. Moreover, VGAs and detectors undergo nonlinear compression under high input amplitudes during settling transients. The main contribution in this work is a proposed nonlinear model based on simple and readily available components from the ＂analogLib＂ and ＂functional＂ libraries in CADENCE design environment -making it very easy and fast to build and simulate-that captures the nonlinear effects of AGC loops. The model is capable of verifying the AGC loop stability and capturing the loop dynamics with high accuracy compared to time consuming circuit level simulations. This provides insights into system level parameters such as AGC loop bandwidth, phase margin, settling time as well as estimating the AGC range and RSSI voltage vs. input power. Measurement results from a fabricated AGC prototype are in good agreement with simulation and modelling results thus validating the proposed modelling approach.
基金Project supported by the National Natural Science Foundation of China(Grant Nos.11174274,61205021,and 61405194)the State Key Laboratory of Applied Optics,Changchun Institute of Optics,Fine Mechanics and Physics,Chinese Academy of Sciences
文摘High signal-to-noise ratio can be achieved with the electron multiplying charge-coupled-device（EMCCD） applied in the Shack–Hartmann wavefront sensor（S–H WFS） in adaptive optics（AO）.However,when the brightness of the target changes in a large scale,the fixed electron multiplying（EM） gain will not be suited to the sensing limitation.Therefore an auto-gain-control method based on the brightness of light-spots array in S–H WFS is proposed in this paper.The control value is the average of the maximum signals of every light spot in an array,which has been demonstrated to be kept stable even under the influence of some noise and turbulence,and sensitive enough to the change of target brightness.A goal value is needed in the control process and it is predetermined based on the characters of EMCCD.Simulations and experiments have demonstrated that this auto-gain-control method is valid and robust,the sensing SNR reaches the maximum for the corresponding signal level,and especially is greatly improved for those dim targets from 6 to 4 magnitude in the visual band.
基金Project supported by the National Natural Science Foundation of China(No.61106021)the Chinese Postdoctoral Science Foundation(Nos. 20090461049.20090461048)the Innovation Fund of Ministry of Science & Technology for Small and Medium Sized Enterprises, China(No.11C26213211234)
文摘A low noise distributed amplifier consisting of 9 gain cells is presented.The chip is fabricated with 0.15-μm GaAs pseudomorphic high electron mobility transistor（PHEMT） technology from Win Semiconductor of Taiwan.A special optional gate bias technique is introduced to allow an adjustable gain control range of 10 dB.A novel cascode structure is adopted to extend the output voltage and bandwidth.The measurement results show that the amplifier gives an average gain of 15 dB with a gain flatness of±1 dB in the 2-20 GHz band.The noise figure is between 2 and 4.1 dB during the band from 2 to 20 GHz.The amplifier also provides 13.8 dBm of output power at a 1 dB gain compression point and 10.5 dBm of input third order intercept point（IIP3）,which demonstrates the excellent performance of linearity.The power consumption is 300 mW with a supply of 5 V,and the chip area is 2.36×1.01 mm^2.
文摘Gain-scheduling has got its wide applications in modern flight control, in which control gains are scheduled with variables such as dynamic pressure and Mach number, to meet dynamic response requirements in different flight conditions. Classical gain-scheduling approaches may result in some problems, which can not guarantee global robustness and stability in transitions of different flight conditions. Gain-scheduling problem is systematically investigated from robustness point of view in the paper. Detailed procedures for gain-scheduled controller to achieve both robustness and stability performance are given and applied to a typical flight control system. For switching stability problems of different flight conditions in flight control systems, a new approach is proposed, in which different flight conditions are reduced into a parameter varying plant using interpolation firstly, and then parameter-varying controller design goes next. Though interpolation errors may exist, the robust parameter varying controller design can compensate for those uncertainties and errors, and finally achieve good performance of robustness and switching stability during transitions. Illustrative simulation at last shows satisfactory results.
基金Project supported by the National Nature Science Foundation of China(Nos.61331003,61474108)the National Key Technology Research and Development Program of the Ministry of Science and Technology of China(No.2016ZX03001002)
文摘This paper proposes a fast-locking bang-bang phase-locked loop（BBPLL）. A novel adaptive loop gain controller（ALGC） is proposed to increase the locking speed of the BBPLL. A novel bang-bang phase/frequency detector（BBPFD） with adaptive-mode-selective circuits is proposed to select the locking mode of the BBPLL during the locking process. Based on the detected results of the BBPFD, the ALGC can dynamically adjust the overall gain of the loop for fast-locking procedure. Compared with the conventional BBPFD, only a few gates are added in the proposed BBPFD. Therefore, the proposed BBPFD with adaptive-mode-selective circuits is realized with little area and power penalties. The fast-locking BBPLL is implemented in a 65 nm CMOS technology. The core area of the BBPLL is 0.022 mm;. Measured results show that the BBPLL operates at a frequency range from0.6 to 2.4 GHz. When operating at 1.8 GHz, the power consumption is 3.1 mW with a 0.9-V supply voltage. With the proposed techniques, the BBPLL achieves a normalized locked time of 1.1μs @ 100 MHz frequency jump.The figure-of-merit of the fast-locking BBPLL is-334 dB.
基金Supported by the National Natural Science Foundation of China (No. 60572087)
文摘Automatic gain control （AGC） has been used in many applications. The key features of AGC, including a steady state output and static/dynamic timing response, depend mainly on key parameters such as the reference and the filter coefficients. A simple model developed to describe AGC systems based on several simple assumptions shows that AGC always converges to the reference and that the timing constant depends on the filter coefficients. Measures are given to prevent oscillations and limit cycle effects. The simple AGC system is adapted to a multiple AGC system for a TV tuner in a much more efficient model. Simulations using the C language are 16 times faster than those with MATLAB, and 10 times faster than those with a mixed register transfer level （RTL）-simulation program with integrated circuit emphasis （SPICE） model.
基金Project supported by the National High Technology Research and Development Program of China(No.2008AA04A 102)
文摘A differential automatic gain control （AGC） circuit is presented. The AGC architecture contains twostage variable gain amplifiers （VGAs） which are implemented with a Gilbert cell, a peak detector （PD）, a low pass filter, an operational amplifier, and two voltage to current （V-I） convertors. One stage VGA achieves 30 dB gain due to the use of active load. The AGC circuit is implemented in UMC 0.18-um single-poly six-metal CMOS process technology. Measurement results show that the final differential output swing of the 2nd stage VGA is about 0.9-Vpp; the total gain of the two VGAs can be varied linearly from -10 to 50 dB when the control voltage varies from 0.3 to 0.9 V. The final circuit （containing output buffers and a band-gap reference） consumes 37 mA from single 1.8 V voltage supply. For a 50 mV amplitude 60% modulation depth input AM signal it needs 100 us to stabilize the output. The frequency response of the circuit has almost a constant -3 dB bandwidth of 2.2 MHz. Its OIP3 result is at 19 dBm.
基金supported by the Chinese National Science and Technology Expertise Program(No.Y1GZ212001)
文摘A low-power, configurable auto-gain control loop for a digital hearing aid system on a chip （SoC） is presented. By adopting a mixed-signal feedback control structure and peak detection and judgment, it can work in automatic gain or variable gain control modes through a digital signal processing unit. A noise-reduction and dynamic range （DR） improvement technique is also used to ensure the DR of the circuit in a low-voltage supply. The circuit is implemented in an SMIC 0.13 μm 1P8M CMOS process. The measurement results show that in a I V power supply, 1.6 kHz input frequency and 200 mVp-p, the SFDR is 74.3 dB, the THD is 66.1 dB, and the total power is 89 μW, meeting the application requirements of hearing aid SoCs.
基金supported by the National High Technology Research and Development Program of China(No.2009AA011608)the Chinese National Major Science and Technology Projects Program(No.2009ZX01031-002-011-001)
文摘This paper presents the design and implementation of a digitally calibrated CMOS wideband radio frequency(RF) root-mean-square(RMS) power detector for high accuracy RF automatic gain control(AGC).The proposed RMS power detector demonstrates accurate power detection in the presence of process,supply voltage, and temperature(PVT) variations by employing a digital calibration scheme.It also consumes low power and occupies a small chip area.The measurement results show that the scheme improves the accuracy of the detector to better than 0.3 dB over the PVT variations and wide operating frequency range from 0.2 to 0.8 GHz.Implemented in a 0.18μm CMOS process and occupying a small die area of 263×214μm^2,the proposed digitally calibrated CMOS RMS power detector only consumes 1.6 mA in power detection mode and 2.1 mA in digital calibration mode from a 1.8 V supply voltage.
基金Project supported by the National High Technology Research and Development Program of China(No2008AA010701)
文摘A current mode feed-forward gain control（CMFGC）technique is presented,which is applied in the front-end system of a hearing aid chip.Compared with conventional automatic gain control（AGC）,CMFGC significantly improves the total harmonic distortion（THD）by digital gain control.To attain the digital gain control codes according to the extremely weak output signal from the microphone,a rectifier and a state controller implemented in current mode are proposed.A prototype chip has been designed based on a 0.13μm standard CMOS process.The measurement results show that the supply voltage can be as low as 0.6 V.And with the 0.8 V supply voltage,the THD is improved and below 0.06%（-64 dB）at the output level of 500 mV_（p-p）,yet the power consumption is limited to 40μW.In addition,the input referred noise is only 4μV_（rms）and the maximum gain is maintained at 33 dB.
基金Project supported by the Major Projects for the Core Electronic Devices,High-End General Chips and Basic Software Products(No. 2009ZX01031-002-008)
文摘An analog/digital reconfigurable automatic gain control （AGC） circuit with a novel DC offset cancel- lation circuit for a direct-conversion receiver is presented. The AGC is analog/digital reconfigurable in order to be compatible with different baseband chips. What＇s more, a novel DC offset cancellation （DCOC） circuit with an HPCF （high pass cutoff frequency） less than 10 kHz is proposed. The AGC is fabricated by a 0.18μm CMOS process. Under analog control mode, the AGC achieves a 70 dB dynamic range with a 3 dB-bandwidth larger than 60 MHz. Under digital control mode, through a 5-bit digital control word, the AGC shows a 64 dB gain control range by 2 dB each step with a gain error of less than 0.3 dB. The DC offset cancellation circuits can suppress the output DC offset voltage to be less than 1.5 mV, while the offset voltage of 40 mV is introduced into the input. The overall power consumption is less than 3.5 mA, and the die area is 800 ×300μm2.
基金supported by the Core Electronic Devices,High-End General Chips and Basic Software Products Major Projects,China(No. 2009ZX01031-002-008)the National High Technology Research and Development Program of China(No.2009AA011601)
文摘An output amplitude configurable wideband automatic gain control（AGC） with high gain step accuracy for the GNSS receiver is presented.The amplitude of an AGC is configurable in order to cooperate with baseband chips to achieve interference suppression and be compatible with different full range ADCs.And what’s more,the gain-boosting technology is introduced and the circuit is improved to increase the step accuracy.A zero,which is composed by the source feedback resistance and the source capacity,is introduced to compensate for the pole.The AGC is fabricated in a 0.18μm CMOS process.The AGC shows a 62 dB gain control range by 1 dB each step with a gain error of less than 0.2 dB.The AGC provides 3 dB bandwidth larger than 80 MHz and the overall power consumption is less than 1.8 mA,and the die area is 800 x 300μm^2.
基金supported by the National High-Tech Research and Development Program of China(Nos.2008AA010703,2009AA011606)the National Natural Science Foundation of China(No.60976023)
文摘This paper proposes a new structure to lower the power consumption of a variable gain amplifier（VGA） and keep the linearity of the VGA unchanged.The structure is used in a high rate amplitude-shift keying（ASK） based IF-stage.It includes an automatic gain control（AGC） loop and ASK demodulator.The AGC mainly consists of sixstage VGAs.The IF-stage is realized in 0.18μm CMOS technology.The measurement results show that the power consumption of the whole system is very low.The system consumes 730μA while operating at 1.8 V.The minimum ASK signal the system could detect is 0.7 mV（peak to peak amplitude）.
基金supported in part by the National Key R&D Program of China(2021YFA0716500)the National 111 Project(B08038).
文摘The fundamental challenges for full-duplex(FD)relay networks are the self-interference cancellation(SIC)and the cooperative transmission design at the relay.This paper presents a practical amplify-and-forward(AF)FD one-way relay scheme for orthogonal frequency division multiplexing(OFDM)transmission with multi-domain SIC.It is found that the residual self-interference(SI)signals at the relay can be regarded as an equivalent multipath model.The effects of the residual sI at the relay are incorporated into the equivalent end-to-end channel model,and the inter-block interference can be removed at the destination by using cyclic prefix(CP)protection.Based on the equivalent multipath model,we present a solution for optimizing the amplification factor on the performance of signal-to-interference-plus-noise ratio(SINR)when the equivalent multipath length is longer than the CP.Furthermore,a practical one way FD relay network with 3 nodes is built and measured.The simulation and measured results verify the superior performance of the proposed scheme.
基金Project(K5117827)supported by Scientific Research Foundation for the Returned Overseas Chinese ScholarsProject(08KJB510021)supported by the Natural Science Research Council of Jiangsu Province,China+1 种基金Project(Q3117918)supported by Scientific Research Foundation for Young Teachers of Soochow University,ChinaProject(60910001)supported by National Natural Science Foundation of China
文摘Consider the design and implementation of an electro-hydraulic control system for a robotic excavator, namely the Lancaster University computerized and intelligent excavator (LUCIE). The excavator was developed to autonomously dig trenches without human intervention. One stumbling block is the achievement of adequate, accurate, quick and smooth movement under automatic control, which is difficult for traditional control algorithm, e.g. PI/PID. A gain scheduling design, based on the true digital proportional-integral-plus (PIP) control methodology, was utilized to regulate the nonlinear joint dynamics. Simulation and initial field tests both demonstrated the feasibility and robustness of proposed technique to the uncertainties of parameters, time delay and load disturbances, with the excavator arm directed along specified trajectories in a smooth, fast and accurate manner. The tracking error magnitudes for oblique straight line and horizontal straight line are less than 20 mm and 50 mm, respectively, while the velocity reaches 9 m/min.
基金supported by the National Natural Science Fundation of China(6097401461273083)
文摘This paper proposes an adaptive augmentation control design approach of the gain-scheduled controller.This extension is motivated by the need for augmentation of the baseline gainscheduled controller.The proposed approach can be utilized to design flight control systems for advanced aerospace vehicles with a large parameter variation.The flight dynamics within the flight envelope is described by a switched nonlinear system,which is essentially a switched polytopic system with uncertainties.The flight control system consists of a baseline gain-scheduled controller and a model reference adaptive augmentation controller,while the latter can recover the nominal performance of the gainscheduled controlled system under large uncertainties.By the multiple Lyapunov functions method,it is proved that the switched nonlinear system is uniformly ultimately bounded.To validate the effectiveness of the proposed approach,this approach is applied to a generic hypersonic vehicle,and the simulation results show that the system output tracks the command signal well even when large uncertainties exist.
基金co-supported by China Postdoctoral Science Foundation(Nos.20110490259,2012T50038)
文摘This article investigates gain self-scheduled H 1 robust control system design for a tailless fold- ing-wing morphing aircraft in the wing shape varying process. During the wing morphing phase, the aircraft＇s dynamic response will be governed by time-varying aerodynamic forces and moments. Nonlinear dynamic equations of the morphing aircraft are linearized by using Jacobian linearization approach, and a linear parameter varying （LPV） model of the morphing aircraft in wing folding is obtained. A multi-loop controller for the morphing aircraft is formulated to guarantee stability for the wing shape transition process. The proposed controller uses a set of inner-loop gains to provide stability using classical techniques, whereas a gain self-scheduled H 1 outer-loop controller is devised to guarantee a specific level of robust stability and performance for the time-varying dynamics. The closed-loop simulations show that speed and altitude vary slightly during the whole wing folding process, and they converge rapidly after the process ends. This proves that the gain self-scheduled H 1 robust controller can guarantee a satisfactory dynamic performance for the morphing aircraft during the whole wing shape transition process. Finally, the flight control system＇s robustness for the wing folding process is verified according to uncertainties of the aerodynamic parameters in the nonlinear model.
