A specially designed experiment is performed for investigating gate-induced drain leakage （GIDL） current in 90nm CMOS technology using lightly-doped drain （LDD） NMOSFET. This paper shows that the drain bias VD has...A specially designed experiment is performed for investigating gate-induced drain leakage （GIDL） current in 90nm CMOS technology using lightly-doped drain （LDD） NMOSFET. This paper shows that the drain bias VD has a strong effect on GIDL current as compared with the gate bias VG at the same drain-gate voltage VDG. It is found that the difference between ID in the off-state ID - VG characteristics and the corresponding one in the off-state ID - VD characteristics, which is defined as IDIFF, versus VDG shows a peak. The difference between the influences of VD and VG on GIDL current is shown quantitatively by IDIFF, especially in 90nm scale. The difference is due to different hole tunnellings, Furthermore, the maximum IDIFF（IDIFF,MAX） varies linearly with VDG in logarithmic coordiuates and also VDG at IDIFF,MAX with VF which is the characteristic voltage of IDIFF, The relations are studied and some related expressions are given.展开更多
A novel n-type junctionless field-effect transistor(JLFET) with a step-gate-oxide(SGO) structure is proposed to suppress the gate-induced drain leakage(GIDL) effect and off-state current I_(off).Introducing a 6-nm-thi...A novel n-type junctionless field-effect transistor(JLFET) with a step-gate-oxide(SGO) structure is proposed to suppress the gate-induced drain leakage(GIDL) effect and off-state current I_(off).Introducing a 6-nm-thick tunnel-gateoxide and maintaining 3-nm-thick control-gate-oxide,lateral band-to-band tunneling(L-BTBT) width is enlarged and its tunneling probability is reduced at the channel-drain surface,leading the off-state current I_(off) to decrease finally.Also,the thicker tunnel-gate-oxide can reduce the influence on the total gate capacitance of JLFET,which could alleviate the capacitive load of the transistor in the circuit applications.Sentaurus simulation shows that I_(off) of the new optimized JLFET reduced significantly with little impaction on its on-state current Ion and threshold voltage V_(TH) becoming less,thus showing an improved I_(on)/I_(off) ratio(5×10^(4)) and subthreshold swing(84 mV/dec),compared with the scenario of the normal JLFET.The influence of the thickness and length of SGO structure on the performance of JLFET are discussed in detail,which could provide useful instruction for the device design.展开更多
A novel operation mechanism of capacitorless SOl-DRAM （silicon on insulator dynamic random access memory） cell using impact ionization and GIDL （gated-induce drain leakage） effects for write ＂1＂ operation was pr...A novel operation mechanism of capacitorless SOl-DRAM （silicon on insulator dynamic random access memory） cell using impact ionization and GIDL （gated-induce drain leakage） effects for write ＂1＂ operation was proposed. The conventional capacitorless DRAM cell with single charge generating effect is either high speed or low power, while the proposed DG-FinFET （double-gate fin field effect transistor） cell employs the efficient integration of impact ionization and GIDL effects by coupling the front and back gates with optimal body doping profile and proper bias conditions, yielding high speed low power performance. The simulation results demonstrate ideal characteristics in both cell operations and power consumption. Low power consumption is achieved by using GIDL current at 0. luA when the coupling between the front and back gates restrains the impact ionization current in the first phase. The write operation of the cell is within Ins attributed to significant current of the impact ionization effect in the second phase. By shortening second phase, power consumption could be further decreased. The ratio of read ＂1＂ and read ＂0＂ current is more than 9.38E5. Moreover, the cell has great retention characteristics.展开更多
The degradation of gate-induced drain leakage （GIDL） current in LDD nMOSFET under hot holes stress is studied in depth based on its parameter IDIFF. IDIFF is the difference of GIDL currents measured under two condit...The degradation of gate-induced drain leakage （GIDL） current in LDD nMOSFET under hot holes stress is studied in depth based on its parameter IDIFF. IDIFF is the difference of GIDL currents measured under two conditions of drain voltage VD = 1.4 V and gate voltage VG = -1.4 V while FoG is fixed. After the stress GIDL currents decay due to holes trapping in the oxide around the gate-to-drain overlap region. These trapped holes diminish A Ex which is the deference of the lateral electrical field of these two symmetrical measurement conditions in the overlap region so as to make IDIFF lessening. IOIFF extracted from GIDL currents decreases with increasing stress time t. The degradation shifts of IDIFF, MAX （A IDWF, MAX） follows a power law against t： △IDIFF＇ MAX （x t^m, m = 0.3. Hot electron stress is performed to validate the related mechanism.展开更多
The degradation of device under GIDL （gate-induced drain leakage current） stress has been studied using LDD NMOSFETs with 1.4 nm gate oxides. Experimental result shows that the degradation of device parameters depen...The degradation of device under GIDL （gate-induced drain leakage current） stress has been studied using LDD NMOSFETs with 1.4 nm gate oxides. Experimental result shows that the degradation of device parameters depends more strongly on Vd than on Vg. The characteristics of the GIDL current are used to analyze the damage generated during the stress. It is clearly found that the change of GIDL current before and after stress can be divided into two stages. The trapping of holes in the oxide is dominant in the first stage, but that of electrons in the oxide is dominant in the second stage. It is due to the common effects of edge direct tunneling and band-to-band tunneling. SILC（stress induced leakage current）in the NMOSFET decreases with increasing stress time under GIDL stress. The degradation characteristic of SILC also shows saturating time dependence. SILC is strongly dependent on the measured gate voltage. The higher the measured gate voltage, the less serious the degradation of the gate current. A likely mechanism is presented to explain the origin of SILC during GIDL stress.展开更多
绝缘体上硅(Silicon on insulator,SOI)技术在200~400℃高温器件和集成电路方面有着广泛的应用前景,但对于沟道长度≤0.18μm的短沟道器件在200℃以上的高温下阈值电压漂移量达40%以上,漏电流达μA级,无法满足电路设计要求。本文研究了...绝缘体上硅(Silicon on insulator,SOI)技术在200~400℃高温器件和集成电路方面有着广泛的应用前景,但对于沟道长度≤0.18μm的短沟道器件在200℃以上的高温下阈值电压漂移量达40%以上,漏电流达μA级,无法满足电路设计要求。本文研究了基于0.15μm SOI工艺的1.5 V MOS器件电特性在高温下的退化机理和抑制方法,通过增加栅氧厚度、降低阱浓度、调整轻掺杂漏离子注入工艺等优化方法,实现了一种性能良好的短沟道高温SOI CMOS器件,在25~250℃温度范围内,该器件阈值电压漂移量<30%,饱和电流漂移量<15%,漏电流<1 nA/μm。此外采用仿真的方法分析了器件在高温下的漏区电势和电场的变化规律,将栅诱导漏极泄漏电流效应与器件高温漏电流关联起来,从而定性地解释了SOI短沟道器件高温漏电流退化的机理。展开更多
The hot carrier effects under off- state stress m ode( Vgs=0 ,Vds<0 ) have been investigated on9nm P- MOSFETs with channel length varying from1.0 2 5 μm to0 .5 2 5 μm.Both on- and off- state currents are discuss...The hot carrier effects under off- state stress m ode( Vgs=0 ,Vds<0 ) have been investigated on9nm P- MOSFETs with channel length varying from1.0 2 5 μm to0 .5 2 5 μm.Both on- and off- state currents are discussed. It is found that the off- state leakage current decreases after a higher voltage stressing,which is induced by the charge injection occurred close to the drain junction.However,the leakage current increases after a lower voltage stressing because of the newly generated interface traps.It is also found that the on state saturation current and threshold voltage degrade significantly with the stress tim e,which we believe is due to the charges injected near the gate- drain overlapping region and/ or the stress- induced interface trap generation.The degradation of Idsatcan be ex- pressed as a function of the product of the gate current( Ig) and the num ber of charges injected into the gate oxide ( Qinj) in a simple power law.Finally,a lifetime prediction model based on the degradation of Idsatis proposed.展开更多
In this paper, a novel junctionless field effect transistor（JLFET） is proposed. In the presence of a field plate between gate and drain, the gate-induced drain leakage（GIDL） effect is suppressed due to the decreas...In this paper, a novel junctionless field effect transistor（JLFET） is proposed. In the presence of a field plate between gate and drain, the gate-induced drain leakage（GIDL） effect is suppressed due to the decrease of lateral band-to-band tunneling probability. Thus, the off-state current Ioff, which is mainly provided by the GIDL current, is reduced. Sentaurus simulation shows that the Ioffof the new optimized JLFET is reduced by ～ 2 orders and its sub-threshold swing can reach76.8 mV/decade with little influence on its on-state current Ion, so its Ion/Ioff ratio is improved by 2 orders of magnitude compared with that of the normal JLFET. Optimization of device parameters such as Φfps（the work difference between field plate and substrate） and LFP（the length of field plate）, is also discussed in detail.展开更多
The major purpose of this paper is to find an alternative configuration that not only minimizes the limitations of single-gate（SG） MOSFETs but also provides the better replacement for future technology.In this paper...The major purpose of this paper is to find an alternative configuration that not only minimizes the limitations of single-gate（SG） MOSFETs but also provides the better replacement for future technology.In this paper,the electrical characteristics of SiGe double-gate N-MOSFET are demonstrated and compared with electrical characteristics of Si double-gate N-MOSFET.Furthermore,in this paper the electrical characteristics of Si doublegate N-MOSFET are demonstrated and compared with electrical characteristics of Si single-gate N-MOSFET.The simulations are carried out for the device at different operational voltages using Cogenda Visual TCAD tool.Moreover,we have designed its structure and studied both Id-Vg characteristics for different voltages namely 0.05,0.1,0.5,0.8,1 and 1.5 V and Id-Vd characteristics for different voltages namely 0.1,0.5,1 and 1.5 V at work functions 4.5,4.6 and 4.8 eV for this structure.The performance parameters investigated in this paper are threshold voltage,DIBL,subthreshold slope,GIDL,volume inversion and MMCR.展开更多
基金Project supported by the National High Technology Research and Development Program of China （Grant No 2003AA1Z1630） and the National Natural Science Foundation of China （Grant No 60376024）.
文摘A specially designed experiment is performed for investigating gate-induced drain leakage （GIDL） current in 90nm CMOS technology using lightly-doped drain （LDD） NMOSFET. This paper shows that the drain bias VD has a strong effect on GIDL current as compared with the gate bias VG at the same drain-gate voltage VDG. It is found that the difference between ID in the off-state ID - VG characteristics and the corresponding one in the off-state ID - VD characteristics, which is defined as IDIFF, versus VDG shows a peak. The difference between the influences of VD and VG on GIDL current is shown quantitatively by IDIFF, especially in 90nm scale. The difference is due to different hole tunnellings, Furthermore, the maximum IDIFF（IDIFF,MAX） varies linearly with VDG in logarithmic coordiuates and also VDG at IDIFF,MAX with VF which is the characteristic voltage of IDIFF, The relations are studied and some related expressions are given.
基金Project supported by the National Natural Science Foundation of China(Grant No.61704130)the Fund from the Science and Technology on Analog Integrated Circuit Laboratory,China(Grant No.JCKY2019210C029)。
文摘A novel n-type junctionless field-effect transistor(JLFET) with a step-gate-oxide(SGO) structure is proposed to suppress the gate-induced drain leakage(GIDL) effect and off-state current I_(off).Introducing a 6-nm-thick tunnel-gateoxide and maintaining 3-nm-thick control-gate-oxide,lateral band-to-band tunneling(L-BTBT) width is enlarged and its tunneling probability is reduced at the channel-drain surface,leading the off-state current I_(off) to decrease finally.Also,the thicker tunnel-gate-oxide can reduce the influence on the total gate capacitance of JLFET,which could alleviate the capacitive load of the transistor in the circuit applications.Sentaurus simulation shows that I_(off) of the new optimized JLFET reduced significantly with little impaction on its on-state current Ion and threshold voltage V_(TH) becoming less,thus showing an improved I_(on)/I_(off) ratio(5×10^(4)) and subthreshold swing(84 mV/dec),compared with the scenario of the normal JLFET.The influence of the thickness and length of SGO structure on the performance of JLFET are discussed in detail,which could provide useful instruction for the device design.
文摘A novel operation mechanism of capacitorless SOl-DRAM （silicon on insulator dynamic random access memory） cell using impact ionization and GIDL （gated-induce drain leakage） effects for write ＂1＂ operation was proposed. The conventional capacitorless DRAM cell with single charge generating effect is either high speed or low power, while the proposed DG-FinFET （double-gate fin field effect transistor） cell employs the efficient integration of impact ionization and GIDL effects by coupling the front and back gates with optimal body doping profile and proper bias conditions, yielding high speed low power performance. The simulation results demonstrate ideal characteristics in both cell operations and power consumption. Low power consumption is achieved by using GIDL current at 0. luA when the coupling between the front and back gates restrains the impact ionization current in the first phase. The write operation of the cell is within Ins attributed to significant current of the impact ionization effect in the second phase. By shortening second phase, power consumption could be further decreased. The ratio of read ＂1＂ and read ＂0＂ current is more than 9.38E5. Moreover, the cell has great retention characteristics.
基金supported by the Specialized Research Fund of the Education Department of Shaanxi Province,China(No.11JK0902)the Innovational Fund for Applied Materials of Xi'an,China(No.XA-AM-201012)
文摘The degradation of gate-induced drain leakage （GIDL） current in LDD nMOSFET under hot holes stress is studied in depth based on its parameter IDIFF. IDIFF is the difference of GIDL currents measured under two conditions of drain voltage VD = 1.4 V and gate voltage VG = -1.4 V while FoG is fixed. After the stress GIDL currents decay due to holes trapping in the oxide around the gate-to-drain overlap region. These trapped holes diminish A Ex which is the deference of the lateral electrical field of these two symmetrical measurement conditions in the overlap region so as to make IDIFF lessening. IOIFF extracted from GIDL currents decreases with increasing stress time t. The degradation shifts of IDIFF, MAX （A IDWF, MAX） follows a power law against t： △IDIFF＇ MAX （x t^m, m = 0.3. Hot electron stress is performed to validate the related mechanism.
基金supported by the National Natural Science Foundation of China (Nos. 60736033, 60506020)
文摘The degradation of device under GIDL （gate-induced drain leakage current） stress has been studied using LDD NMOSFETs with 1.4 nm gate oxides. Experimental result shows that the degradation of device parameters depends more strongly on Vd than on Vg. The characteristics of the GIDL current are used to analyze the damage generated during the stress. It is clearly found that the change of GIDL current before and after stress can be divided into two stages. The trapping of holes in the oxide is dominant in the first stage, but that of electrons in the oxide is dominant in the second stage. It is due to the common effects of edge direct tunneling and band-to-band tunneling. SILC（stress induced leakage current）in the NMOSFET decreases with increasing stress time under GIDL stress. The degradation characteristic of SILC also shows saturating time dependence. SILC is strongly dependent on the measured gate voltage. The higher the measured gate voltage, the less serious the degradation of the gate current. A likely mechanism is presented to explain the origin of SILC during GIDL stress.
文摘绝缘体上硅(Silicon on insulator,SOI)技术在200~400℃高温器件和集成电路方面有着广泛的应用前景,但对于沟道长度≤0.18μm的短沟道器件在200℃以上的高温下阈值电压漂移量达40%以上,漏电流达μA级,无法满足电路设计要求。本文研究了基于0.15μm SOI工艺的1.5 V MOS器件电特性在高温下的退化机理和抑制方法,通过增加栅氧厚度、降低阱浓度、调整轻掺杂漏离子注入工艺等优化方法,实现了一种性能良好的短沟道高温SOI CMOS器件,在25~250℃温度范围内,该器件阈值电压漂移量<30%,饱和电流漂移量<15%,漏电流<1 nA/μm。此外采用仿真的方法分析了器件在高温下的漏区电势和电场的变化规律,将栅诱导漏极泄漏电流效应与器件高温漏电流关联起来,从而定性地解释了SOI短沟道器件高温漏电流退化的机理。
文摘The hot carrier effects under off- state stress m ode( Vgs=0 ,Vds<0 ) have been investigated on9nm P- MOSFETs with channel length varying from1.0 2 5 μm to0 .5 2 5 μm.Both on- and off- state currents are discussed. It is found that the off- state leakage current decreases after a higher voltage stressing,which is induced by the charge injection occurred close to the drain junction.However,the leakage current increases after a lower voltage stressing because of the newly generated interface traps.It is also found that the on state saturation current and threshold voltage degrade significantly with the stress tim e,which we believe is due to the charges injected near the gate- drain overlapping region and/ or the stress- induced interface trap generation.The degradation of Idsatcan be ex- pressed as a function of the product of the gate current( Ig) and the num ber of charges injected into the gate oxide ( Qinj) in a simple power law.Finally,a lifetime prediction model based on the degradation of Idsatis proposed.
基金supported by the National Natural Science Foundation of China(Grant No.61704130)the Fundamental Research Funds for the Central Universities,China(Grant No.20101166085)the Opening Project of Key Laboratory of Microelectronic Devices&Integrated Technology from Institute of Microelectronics,Chinese Academy of Sciences(Grant No.90109162905)
文摘In this paper, a novel junctionless field effect transistor（JLFET） is proposed. In the presence of a field plate between gate and drain, the gate-induced drain leakage（GIDL） effect is suppressed due to the decrease of lateral band-to-band tunneling probability. Thus, the off-state current Ioff, which is mainly provided by the GIDL current, is reduced. Sentaurus simulation shows that the Ioffof the new optimized JLFET is reduced by ～ 2 orders and its sub-threshold swing can reach76.8 mV/decade with little influence on its on-state current Ion, so its Ion/Ioff ratio is improved by 2 orders of magnitude compared with that of the normal JLFET. Optimization of device parameters such as Φfps（the work difference between field plate and substrate） and LFP（the length of field plate）, is also discussed in detail.
文摘The major purpose of this paper is to find an alternative configuration that not only minimizes the limitations of single-gate（SG） MOSFETs but also provides the better replacement for future technology.In this paper,the electrical characteristics of SiGe double-gate N-MOSFET are demonstrated and compared with electrical characteristics of Si double-gate N-MOSFET.Furthermore,in this paper the electrical characteristics of Si doublegate N-MOSFET are demonstrated and compared with electrical characteristics of Si single-gate N-MOSFET.The simulations are carried out for the device at different operational voltages using Cogenda Visual TCAD tool.Moreover,we have designed its structure and studied both Id-Vg characteristics for different voltages namely 0.05,0.1,0.5,0.8,1 and 1.5 V and Id-Vd characteristics for different voltages namely 0.1,0.5,1 and 1.5 V at work functions 4.5,4.6 and 4.8 eV for this structure.The performance parameters investigated in this paper are threshold voltage,DIBL,subthreshold slope,GIDL,volume inversion and MMCR.
