In this paper, we describe resourceefficient hardware architectures for softwaredefined radio （SDR） frontends. These architectures are made efficient by using a polyphase channelizer that performs arbitrary sample r...In this paper, we describe resourceefficient hardware architectures for softwaredefined radio （SDR） frontends. These architectures are made efficient by using a polyphase channelizer that performs arbitrary sample rate changes, frequency selection, and bandwidth control. We discuss area, time, and power optimization for field programmable gate array （FPGA） based architectures in an Mpath polyphase filter bank with modified Npath polyphase filter. Such systems allow resampling by arbitrary ratios while simultaneously performing baseband aliasing from center frequencies at Nyquist zones that are not multiples of the output sample rate. A nonmaximally decimated polyphase filter bank, where the number of data loads is not equal to the number of M subfilters, processes M subfilters in a time period that is either less than or greater than the Mdataload ＇ s time period. We present a loadprocess architecture （LPA） and a runtime architecture （RA） （based on serial polyphase structure） which have different scheduling. In LPA, Nsubfilters are loaded, and then M subfilters are processed at a clock rate that is a multiple of the input data rate. This is necessary to meet the output time constraint of the down-sampled data. In RA, Msubfilters processes are efficiently scheduled within Ndataload time while simultaneously loading N subfilters. This requires reduced clock rates compared with LPA, and potentially less power is consumed. A polyphase filter bank that uses different resampling factors for maximally decimated, underdecimated, overdecimated, and combined upand downsampled scenarios is used as a case study, and an analysis of area, time, and power for their FPGA architectures is given. For resourceoptimized SDR frontends, RA is superior for reducing operating clock rates and dynamic power consumption. RA is also superior for reducing area resources, except when indices are prestored in LUTs.展开更多
In radio receivers,complete implementation of the software defined radio(SDR) concept is mainly limited by frontend.Based on bandpass sampling(BPS) theory,a flexible digital frontend(DFE) platform for SDR receiver is ...In radio receivers,complete implementation of the software defined radio(SDR) concept is mainly limited by frontend.Based on bandpass sampling(BPS) theory,a flexible digital frontend(DFE) platform for SDR receiver is designed.In order to increase the processing speed,Gigabit Ethernet was applied in the platform at speed of 5×10~8 bit/s.By appropriate design of interpolant according to the position of input RF signals,multi-band receiving can be realized in the platform with suppression more than 35 d B without changing hardware.展开更多
After an introduction to the implementation of supervisory computer control (SCC) through networks and the relevant security issues, this paper centers on the core of network security design: intelligent front-end pro...After an introduction to the implementation of supervisory computer control (SCC) through networks and the relevant security issues, this paper centers on the core of network security design: intelligent front-end processor (FEP), encryption/decryption method and authentication protocol. Some other system-specific security measures are also proposed. Although these are examples only, the techniques discussed can also be used in and provide reference for other remote control systems.展开更多
This paper presents an AC coupling ultrasound analog front-end(AFE)architecture with a three-stage DC offset correction(DCOC)circuit.In ultrasound systems,the low noise amplifier(LNA),time gain control(TGC),and low pa...This paper presents an AC coupling ultrasound analog front-end(AFE)architecture with a three-stage DC offset correction(DCOC)circuit.In ultrasound systems,the low noise amplifier(LNA),time gain control(TGC),and low pass filter(LPF)constitute the AFE,which achieves low noise,time-varying gain compensation,and filtering for the received ultrasound signal.The inherent asymmetry in LNA,layout asymmetry and the process variation introduce DC offset and the TGC changes it into low-frequency offset drift.The proposed DCOC circuit for LNA is composed of a transconductance amplifier and an off-chip capacitor,while a fully differential operational amplifier and a pseudo resistor are used for other amplification stages.The AC coupling scheme is also used to reduce the offset and drift.The simulation result shows when the DCOC and the AC coupling are adopted,the offset and drift are almost perfectly suppressed.The proposed AFE has been fabricated by a 28-nm CMOS process,and it achieves an 85 dB gain range with low input-referred noise of 2.43 nV/√Hz at 5 MHz,and it also has a tunable bandwidth of 15/30 MHz and switchable input impedance of 50/100 ohms.展开更多
This paper presents a dual-band low noise amplifier for the receiver of a global navigation satellite system. The differences between single band and multi-band design methods are discussed. The relevant parameter ana...This paper presents a dual-band low noise amplifier for the receiver of a global navigation satellite system. The differences between single band and multi-band design methods are discussed. The relevant parameter analysis and the details of circuit design are presented. The test chip was implemented in a TSMC 0.18 μm 1P4M RF CMOS process. The LNA achieves a gain of 16.8 dB/18.9 dB on 1.27 GHz/1.575 GHz. The measured noise figure is around 1.5-1.7 dB on both bands. The LNA consumes less than 4.3 mA of current from a 1.8 V power supply. The measurement results show consistency with the design. And the LNA can fully satisfy the demands of the GNSS receiver.展开更多
This paper introduces a fully integrated low power consumption radio receiver frontend circuit for a Compass（Beidou） and GPS dual mode dual channel system with 2.5 dB NF,1.02 mm^2 areas,and 8 mA of current in 0.18μ...This paper introduces a fully integrated low power consumption radio receiver frontend circuit for a Compass（Beidou） and GPS dual mode dual channel system with 2.5 dB NF,1.02 mm^2 areas,and 8 mA of current in 0.18μm TSMC CMOS process.Except for a few passive components for input matching,other components such as an off-chip low noise amplifier or a balun are not required.With a non-tunable passive image rejection filter,the receiver frontend can achieve around 60 dB gain and 34 dB image rejection.展开更多
This paper presents the design and implementation of a fully integrated multi-band RF receiver frontend for GNSS applications on L-band.A single RF signal channel with a low-IF architecture is adopted for multi-band o...This paper presents the design and implementation of a fully integrated multi-band RF receiver frontend for GNSS applications on L-band.A single RF signal channel with a low-IF architecture is adopted for multi-band operation on the RF section,which mainly consists of a low noise amplifier（LNA）,a down-converter,polyphase filters and summing circuits.An improved cascode source degenerated LNA with a multi-band shared off-chip matching network and band switches is implemented in the first amplifying stage.Also,a re-designed wideband double balance mixer is implemented in the down conversion stage,which provides better gain,noise figure and linearity performances.Using a TSMC 0.18μm 1P4M RF CMOS process,a compact 1.27 GHz/1.575 GHz dualband GNSS frontend is realized in the proposed low-IF topology.The measurements exhibit the gains of 45 dB and 43 dB,and noise figures are controlled at 3.35 dB and 3.9 dB of the two frequency bands,respectively.The frontend model consumes about 11.8-13.5 mA current on a 1.8 V power supply.The core occupies 1.91×0.53 mm2 while the total die area with ESD is 2.45×2.36 mm^2.展开更多
This paper presents an improved merged architecture for a low-IF GNSS receiver frontend,where the bias current and functions are reused in a stacked quadrature LNA-mixer-VCO.Only a single spiral inductor is implemente...This paper presents an improved merged architecture for a low-IF GNSS receiver frontend,where the bias current and functions are reused in a stacked quadrature LNA-mixer-VCO.Only a single spiral inductor is implemented for the LC resonator and an extra 1/2 frequency divider is added as the quadrature LO signal generator. The details of the design are presented.The gain plan and noise figure are discussed.The phase noise,quadrature accuracy and power consumption are improved.The test chip is fabricated though a 0.18μm RF CMOS process. The measured noise figure is 5.4 dB on average,with a gain of 43 dB and a IIP3 of-39 dBm.The measured phase noise is better than -105 dBc/Hz at 1 MHz offset.The total power consumption is 19.8 mW with a 1.8 V supply. The experimental results satisfy the requirements for GNSS applications.展开更多
文摘In this paper, we describe resourceefficient hardware architectures for softwaredefined radio （SDR） frontends. These architectures are made efficient by using a polyphase channelizer that performs arbitrary sample rate changes, frequency selection, and bandwidth control. We discuss area, time, and power optimization for field programmable gate array （FPGA） based architectures in an Mpath polyphase filter bank with modified Npath polyphase filter. Such systems allow resampling by arbitrary ratios while simultaneously performing baseband aliasing from center frequencies at Nyquist zones that are not multiples of the output sample rate. A nonmaximally decimated polyphase filter bank, where the number of data loads is not equal to the number of M subfilters, processes M subfilters in a time period that is either less than or greater than the Mdataload ＇ s time period. We present a loadprocess architecture （LPA） and a runtime architecture （RA） （based on serial polyphase structure） which have different scheduling. In LPA, Nsubfilters are loaded, and then M subfilters are processed at a clock rate that is a multiple of the input data rate. This is necessary to meet the output time constraint of the down-sampled data. In RA, Msubfilters processes are efficiently scheduled within Ndataload time while simultaneously loading N subfilters. This requires reduced clock rates compared with LPA, and potentially less power is consumed. A polyphase filter bank that uses different resampling factors for maximally decimated, underdecimated, overdecimated, and combined upand downsampled scenarios is used as a case study, and an analysis of area, time, and power for their FPGA architectures is given. For resourceoptimized SDR frontends, RA is superior for reducing operating clock rates and dynamic power consumption. RA is also superior for reducing area resources, except when indices are prestored in LUTs.
基金Project(2013QNA49)supported by the Fundamental Research Funds for the Central Universities,China
文摘In radio receivers,complete implementation of the software defined radio(SDR) concept is mainly limited by frontend.Based on bandpass sampling(BPS) theory,a flexible digital frontend(DFE) platform for SDR receiver is designed.In order to increase the processing speed,Gigabit Ethernet was applied in the platform at speed of 5×10~8 bit/s.By appropriate design of interpolant according to the position of input RF signals,multi-band receiving can be realized in the platform with suppression more than 35 d B without changing hardware.
文摘After an introduction to the implementation of supervisory computer control (SCC) through networks and the relevant security issues, this paper centers on the core of network security design: intelligent front-end processor (FEP), encryption/decryption method and authentication protocol. Some other system-specific security measures are also proposed. Although these are examples only, the techniques discussed can also be used in and provide reference for other remote control systems.
基金supported by the National Key Research and Development Project under Grant 2020YFC0122101.
文摘This paper presents an AC coupling ultrasound analog front-end(AFE)architecture with a three-stage DC offset correction(DCOC)circuit.In ultrasound systems,the low noise amplifier(LNA),time gain control(TGC),and low pass filter(LPF)constitute the AFE,which achieves low noise,time-varying gain compensation,and filtering for the received ultrasound signal.The inherent asymmetry in LNA,layout asymmetry and the process variation introduce DC offset and the TGC changes it into low-frequency offset drift.The proposed DCOC circuit for LNA is composed of a transconductance amplifier and an off-chip capacitor,while a fully differential operational amplifier and a pseudo resistor are used for other amplification stages.The AC coupling scheme is also used to reduce the offset and drift.The simulation result shows when the DCOC and the AC coupling are adopted,the offset and drift are almost perfectly suppressed.The proposed AFE has been fabricated by a 28-nm CMOS process,and it achieves an 85 dB gain range with low input-referred noise of 2.43 nV/√Hz at 5 MHz,and it also has a tunable bandwidth of 15/30 MHz and switchable input impedance of 50/100 ohms.
文摘This paper presents a dual-band low noise amplifier for the receiver of a global navigation satellite system. The differences between single band and multi-band design methods are discussed. The relevant parameter analysis and the details of circuit design are presented. The test chip was implemented in a TSMC 0.18 μm 1P4M RF CMOS process. The LNA achieves a gain of 16.8 dB/18.9 dB on 1.27 GHz/1.575 GHz. The measured noise figure is around 1.5-1.7 dB on both bands. The LNA consumes less than 4.3 mA of current from a 1.8 V power supply. The measurement results show consistency with the design. And the LNA can fully satisfy the demands of the GNSS receiver.
基金supported by the Economic & Information Commission Program of Guangdong,China(No.2011912004)the Department of Science and Technology of Guangdong Province Program,China(Nos.2011 B0 10700065,2011A090200106)the High-Tech Industry Development Funding of Guangdong Province,China(No.2010A011300006)
文摘This paper introduces a fully integrated low power consumption radio receiver frontend circuit for a Compass（Beidou） and GPS dual mode dual channel system with 2.5 dB NF,1.02 mm^2 areas,and 8 mA of current in 0.18μm TSMC CMOS process.Except for a few passive components for input matching,other components such as an off-chip low noise amplifier or a balun are not required.With a non-tunable passive image rejection filter,the receiver frontend can achieve around 60 dB gain and 34 dB image rejection.
文摘This paper presents the design and implementation of a fully integrated multi-band RF receiver frontend for GNSS applications on L-band.A single RF signal channel with a low-IF architecture is adopted for multi-band operation on the RF section,which mainly consists of a low noise amplifier（LNA）,a down-converter,polyphase filters and summing circuits.An improved cascode source degenerated LNA with a multi-band shared off-chip matching network and band switches is implemented in the first amplifying stage.Also,a re-designed wideband double balance mixer is implemented in the down conversion stage,which provides better gain,noise figure and linearity performances.Using a TSMC 0.18μm 1P4M RF CMOS process,a compact 1.27 GHz/1.575 GHz dualband GNSS frontend is realized in the proposed low-IF topology.The measurements exhibit the gains of 45 dB and 43 dB,and noise figures are controlled at 3.35 dB and 3.9 dB of the two frequency bands,respectively.The frontend model consumes about 11.8-13.5 mA current on a 1.8 V power supply.The core occupies 1.91×0.53 mm2 while the total die area with ESD is 2.45×2.36 mm^2.
基金Project supported by the National Natural Science Foundation of China(No.61076101)
文摘This paper presents an improved merged architecture for a low-IF GNSS receiver frontend,where the bias current and functions are reused in a stacked quadrature LNA-mixer-VCO.Only a single spiral inductor is implemented for the LC resonator and an extra 1/2 frequency divider is added as the quadrature LO signal generator. The details of the design are presented.The gain plan and noise figure are discussed.The phase noise,quadrature accuracy and power consumption are improved.The test chip is fabricated though a 0.18μm RF CMOS process. The measured noise figure is 5.4 dB on average,with a gain of 43 dB and a IIP3 of-39 dBm.The measured phase noise is better than -105 dBc/Hz at 1 MHz offset.The total power consumption is 19.8 mW with a 1.8 V supply. The experimental results satisfy the requirements for GNSS applications.
