In radio receivers,complete implementation of the software defined radio(SDR) concept is mainly limited by frontend.Based on bandpass sampling(BPS) theory,a flexible digital frontend(DFE) platform for SDR receiver is ...In radio receivers,complete implementation of the software defined radio(SDR) concept is mainly limited by frontend.Based on bandpass sampling(BPS) theory,a flexible digital frontend(DFE) platform for SDR receiver is designed.In order to increase the processing speed,Gigabit Ethernet was applied in the platform at speed of 5×10~8 bit/s.By appropriate design of interpolant according to the position of input RF signals,multi-band receiving can be realized in the platform with suppression more than 35 d B without changing hardware.展开更多
This paper introduces a fully integrated low power consumption radio receiver frontend circuit for a Compass（Beidou） and GPS dual mode dual channel system with 2.5 dB NF,1.02 mm^2 areas,and 8 mA of current in 0.18μ...This paper introduces a fully integrated low power consumption radio receiver frontend circuit for a Compass（Beidou） and GPS dual mode dual channel system with 2.5 dB NF,1.02 mm^2 areas,and 8 mA of current in 0.18μm TSMC CMOS process.Except for a few passive components for input matching,other components such as an off-chip low noise amplifier or a balun are not required.With a non-tunable passive image rejection filter,the receiver frontend can achieve around 60 dB gain and 34 dB image rejection.展开更多
This paper presents the design and implementation of a fully integrated multi-band RF receiver frontend for GNSS applications on L-band.A single RF signal channel with a low-IF architecture is adopted for multi-band o...This paper presents the design and implementation of a fully integrated multi-band RF receiver frontend for GNSS applications on L-band.A single RF signal channel with a low-IF architecture is adopted for multi-band operation on the RF section,which mainly consists of a low noise amplifier（LNA）,a down-converter,polyphase filters and summing circuits.An improved cascode source degenerated LNA with a multi-band shared off-chip matching network and band switches is implemented in the first amplifying stage.Also,a re-designed wideband double balance mixer is implemented in the down conversion stage,which provides better gain,noise figure and linearity performances.Using a TSMC 0.18μm 1P4M RF CMOS process,a compact 1.27 GHz/1.575 GHz dualband GNSS frontend is realized in the proposed low-IF topology.The measurements exhibit the gains of 45 dB and 43 dB,and noise figures are controlled at 3.35 dB and 3.9 dB of the two frequency bands,respectively.The frontend model consumes about 11.8-13.5 mA current on a 1.8 V power supply.The core occupies 1.91×0.53 mm2 while the total die area with ESD is 2.45×2.36 mm^2.展开更多
This paper presents an improved merged architecture for a low-IF GNSS receiver frontend,where the bias current and functions are reused in a stacked quadrature LNA-mixer-VCO.Only a single spiral inductor is implemente...This paper presents an improved merged architecture for a low-IF GNSS receiver frontend,where the bias current and functions are reused in a stacked quadrature LNA-mixer-VCO.Only a single spiral inductor is implemented for the LC resonator and an extra 1/2 frequency divider is added as the quadrature LO signal generator. The details of the design are presented.The gain plan and noise figure are discussed.The phase noise,quadrature accuracy and power consumption are improved.The test chip is fabricated though a 0.18μm RF CMOS process. The measured noise figure is 5.4 dB on average,with a gain of 43 dB and a IIP3 of-39 dBm.The measured phase noise is better than -105 dBc/Hz at 1 MHz offset.The total power consumption is 19.8 mW with a 1.8 V supply. The experimental results satisfy the requirements for GNSS applications.展开更多
基金Project(2013QNA49)supported by the Fundamental Research Funds for the Central Universities,China
文摘In radio receivers,complete implementation of the software defined radio(SDR) concept is mainly limited by frontend.Based on bandpass sampling(BPS) theory,a flexible digital frontend(DFE) platform for SDR receiver is designed.In order to increase the processing speed,Gigabit Ethernet was applied in the platform at speed of 5×10~8 bit/s.By appropriate design of interpolant according to the position of input RF signals,multi-band receiving can be realized in the platform with suppression more than 35 d B without changing hardware.
基金supported by the Economic & Information Commission Program of Guangdong,China(No.2011912004)the Department of Science and Technology of Guangdong Province Program,China(Nos.2011 B0 10700065,2011A090200106)the High-Tech Industry Development Funding of Guangdong Province,China(No.2010A011300006)
文摘This paper introduces a fully integrated low power consumption radio receiver frontend circuit for a Compass（Beidou） and GPS dual mode dual channel system with 2.5 dB NF,1.02 mm^2 areas,and 8 mA of current in 0.18μm TSMC CMOS process.Except for a few passive components for input matching,other components such as an off-chip low noise amplifier or a balun are not required.With a non-tunable passive image rejection filter,the receiver frontend can achieve around 60 dB gain and 34 dB image rejection.
文摘This paper presents the design and implementation of a fully integrated multi-band RF receiver frontend for GNSS applications on L-band.A single RF signal channel with a low-IF architecture is adopted for multi-band operation on the RF section,which mainly consists of a low noise amplifier（LNA）,a down-converter,polyphase filters and summing circuits.An improved cascode source degenerated LNA with a multi-band shared off-chip matching network and band switches is implemented in the first amplifying stage.Also,a re-designed wideband double balance mixer is implemented in the down conversion stage,which provides better gain,noise figure and linearity performances.Using a TSMC 0.18μm 1P4M RF CMOS process,a compact 1.27 GHz/1.575 GHz dualband GNSS frontend is realized in the proposed low-IF topology.The measurements exhibit the gains of 45 dB and 43 dB,and noise figures are controlled at 3.35 dB and 3.9 dB of the two frequency bands,respectively.The frontend model consumes about 11.8-13.5 mA current on a 1.8 V power supply.The core occupies 1.91×0.53 mm2 while the total die area with ESD is 2.45×2.36 mm^2.
基金Project supported by the National Natural Science Foundation of China(No.61076101)
文摘This paper presents an improved merged architecture for a low-IF GNSS receiver frontend,where the bias current and functions are reused in a stacked quadrature LNA-mixer-VCO.Only a single spiral inductor is implemented for the LC resonator and an extra 1/2 frequency divider is added as the quadrature LO signal generator. The details of the design are presented.The gain plan and noise figure are discussed.The phase noise,quadrature accuracy and power consumption are improved.The test chip is fabricated though a 0.18μm RF CMOS process. The measured noise figure is 5.4 dB on average,with a gain of 43 dB and a IIP3 of-39 dBm.The measured phase noise is better than -105 dBc/Hz at 1 MHz offset.The total power consumption is 19.8 mW with a 1.8 V supply. The experimental results satisfy the requirements for GNSS applications.
