In this paper, the design of a novel low-noise front-end readout circuit for Cadmium zinc telluride (CdZnTe) X-ray and γ-ray detectors is described. The front-end readout circuits include the charge sensitive amplifi...In this paper, the design of a novel low-noise front-end readout circuit for Cadmium zinc telluride (CdZnTe) X-ray and γ-ray detectors is described. The front-end readout circuits include the charge sensitive amplifier (CSA) and the CR-RC shaper is implemented in TSMC 0.35 μm mixed-signal CMOS technology. The die size of the prototype chip is 4.9 mm × 2.2 mm. The simulation results show that, the noise performance is 46 electrons + 10 electrons/pF, and power consumption is 1.65 mW per channel.展开更多
The development of low-cost,non-enzymatic glucose biosensors is crucial for advancing accessible diabetes management.This paper presents the experimental testing of an extended-gate field-effect transistor(EG-FET)that...The development of low-cost,non-enzymatic glucose biosensors is crucial for advancing accessible diabetes management.This paper presents the experimental testing of an extended-gate field-effect transistor(EG-FET)that uses a gold film as the sensing structure.The system innovatively employs a custom-designed inverting operational amplifier circuit for precise signal acquisition and an Arduino Nano platform for real-time data processing and visualization,eliminating the need for expensive laboratory equipment.At the core of the design is a depletion-mode MOSFET,whose current-voltage properties were characterized.The function of the sensor was demonstrated by testing its response to phosphate-buffered saline containing glucose at different concentrations.A clear modulation of the drain current in the linear region of the EG-FET was observed,and a preliminary analysis revealed a linear correlation between the output current and glucose concentration,indicating the system’s potential for quantitative detection.This study successfully validates the feasibility of a compact,cost-effective,and non-enzymatic EG-FET biosensing platform,establishing a solid foundation for future development of point-of-care diagnostic devices.展开更多
Novel schemes for a charge sensitive amplifier （CSA） and a CR-（RC）, semi-Gaussian shaper in a fully integrated CMOS readout circuit for particle detectors are presented. The CSA is designed with poly-resistors as ...Novel schemes for a charge sensitive amplifier （CSA） and a CR-（RC）, semi-Gaussian shaper in a fully integrated CMOS readout circuit for particle detectors are presented. The CSA is designed with poly-resistors as feedback components to reduce noise. Compared with conventional CSA, the input referred equivalent noise charge（ENC） is simulated to be reduced from 5036e to 2381e with a large detector capacitance of 150pF at the cost of 0.5V output swing loss. The CR-（RC）,semi-Gaussian shaper uses MOS transistors in the triode region in series with poly-resistors to compensate process variation without much linearity reduction.展开更多
Based on an avalanche photodiode（ APD） detecting array working in Geiger mode（ GM-APD）, a high-performance infrared sensor readout integrated circuit（ ROIC） used for infrared 3D（ three-dimensional） imaging is ...Based on an avalanche photodiode（ APD） detecting array working in Geiger mode（ GM-APD）, a high-performance infrared sensor readout integrated circuit（ ROIC） used for infrared 3D（ three-dimensional） imaging is proposed. The system mainly consists of three functional modules, including active quenching circuit（ AQC）, time-to-digital converter（ TDC） circuit and other timing controller circuit. Each AQC and TDC circuit together constitutes the pixel circuit. Under the cooperation with other modules, the current signal generated by the GM-APD sensor is detected by the AQC, and the photon time-of-flight（ TOF） is measured and converted to a digital signal output to achieve a better noise suppression and a higher detection sensitivity by the TDC. The ROIC circuit is fabricated by the CSMC 0. 5 μm standard CMOS technology. The array size is 8 × 8, and the center distance of two adjacent cells is 100μm. The measurement results of the chip showthat the performance of the circuit is good, and the chip can achieve 1 ns time resolution with a 250 MHz reference clock, and the circuit can be used in the array structure of the infrared detection system or focal plane array（ FPA）.展开更多
The diode infrared focal plane array uses the silicon diodes as a sensitive device for infrared signal measurement. By the infrared radiation, the infrared focal plane can produces small voltage signals. For the tradi...The diode infrared focal plane array uses the silicon diodes as a sensitive device for infrared signal measurement. By the infrared radiation, the infrared focal plane can produces small voltage signals. For the traditional readout circuit structures are designed to process current signals, they cannot be applied to it. In this paper, a new readout circuit for the diode un-cooled infrared focal plane array is developed. The principle of detector array signal readout and small signal amplification is given in detail. The readout circuit is designed and simulated by using the Central Semiconductor Manufacturing Corporation （CSMC） 0.5 μm complementary metal-oxide-semiconductor transistor （CMOS） technology library. Cadence Spectre simulation results show that the scheme can be applied to the CMOS readout integrated circuit （ROIC） with a larger array, such as 320×240 size array.展开更多
A novel ultra-low-power readout integrated circuit(ROIC) for 1 024×1 024 ultraviolet(UV) AlGaN focal plane arrays(FPA) with 18 μm-pitch was presented. In order to optimize power consumption for UVFPA readout cir...A novel ultra-low-power readout integrated circuit(ROIC) for 1 024×1 024 ultraviolet(UV) AlGaN focal plane arrays(FPA) with 18 μm-pitch was presented. In order to optimize power consumption for UVFPA readout circuit these methods were adopted, which including single-terminal amplifier under subthreshold region as CTIA amplifier, common current source load for source follow(SF) buffer in column pixels and level shift circuits, and time-sharing tail current source for column buffer. The smallest operational current of CTIA in pixel unit is only 8.5 nA with 3.3 V power supply by using single-terminal amplifier. The ROIC has been fabricated in SMIC 0.18 μm 1P6M mixed signal process and also achieved better performances with the novel design of bias current adjustable. Furthermore, the overall power consumption of the chip is 67.3 mW at 2 MHz in 8-outputs mode by the above methods according to the experimental results.展开更多
Integrated circuits of deep submicron(DSM) CMOS technology are advantageous in volume density, power consumption and thermal noise for multichannel particle detection systems,but there are challenges in the front-end ...Integrated circuits of deep submicron(DSM) CMOS technology are advantageous in volume density, power consumption and thermal noise for multichannel particle detection systems,but there are challenges in the front-end circuit design.In this paper,we present a 0.18μm CMOS front-end readout circuit for low noise CdZnTe detectors in tens of pF capacitance.Solutions to the noise and gate leak problems in DSM technologies are discussed in detail.A prototype chip was designed,with a charge sensitive preamplifier,a 4th order semi-Gaussian shaper and several output drivers.Test results show that the chip has an equivalent noise charge of 164 e,without connecting it to a detector,with an integral nonlinearity of<0.21%and differential nonlinearity of<3.75%.展开更多
A low-noise readout integrated circuit for high-energy particle detector is presented.The noise of charge sensitive amplifier was suppressed by using single-side amplifier and resistors as source degeneration.Continuo...A low-noise readout integrated circuit for high-energy particle detector is presented.The noise of charge sensitive amplifier was suppressed by using single-side amplifier and resistors as source degeneration.Continuous-time semi-Gaussian filter is chosen to avoid switch noise.The peaking time of pulse shaper and the gain can be programmed to satisfy multi-application.The readout integrated circuit has been designed and fabricated using a 0.35 μm double-poly triple-metal CMOS technology.Test results show the functions of the readout integrated circuit are correct.The equivalent noise charge with no detector connected is 500–700 e in the typical mode,the gain is tunable within 13–130 mV/fC and the peaking time varies from 0.7 to 1.6 μs,in which the average gain is about 20.5 mV/fC,and the linearity reaches 99.2%.展开更多
This paper describes a low-noise front-end readout circuit for CZT detectors based on TSMC 0.35 um mixed-single CMOS technology;mainly analyzes the noise model of the detector-preamplifier and presents the low-noise c...This paper describes a low-noise front-end readout circuit for CZT detectors based on TSMC 0.35 um mixed-single CMOS technology;mainly analyzes the noise model of the detector-preamplifier and presents the low-noise circuit schematic of charge sensitive preamplifier and shaper. Considering the parasitical influences, the circuit and layout-design are optimized to reduce noise. The preliminary simulation results show that, the equivalent noise charge (ENC) is 74 e﹣ (rms), noise slope is 9 e﹣/pF, power consumption is 2 mW, and non-linearity展开更多
A high injection, large dynamic range, stable detector bias, small area and low power consumption CMOS readout circuit with background current suppression and correlated double sampling (CDS) for a high-resolution inf...A high injection, large dynamic range, stable detector bias, small area and low power consumption CMOS readout circuit with background current suppression and correlated double sampling (CDS) for a high-resolution infrared focal plane array applications is proposed. The detector bias error in this structure is less than 0.1 mV. The input resistance is ideally zero, which is important to obtain high injection efficiency. Unit-cell occupies 10 μm × 15 μm area and consumes less than 0.4 mW power. Charge storag...展开更多
The structure of the extended gate ion sensitive field effect transistor (EGISFET) is similar to the structure of the ion sensitive field effect transistor (ISFET).Moreover,the non-ideal effect of EGISFET is the mai...The structure of the extended gate ion sensitive field effect transistor (EGISFET) is similar to the structure of the ion sensitive field effect transistor (ISFET).Moreover,the non-ideal effect of EGISFET is the main impediment to development of commercial processes for sensitive devices.It is necessary to promote the stability and reliability of the devices by employing calibration circuits and the better fabrication conditions.The temporal drift exists in the entire measurement experiment. Furthermore,in this study we can reduce the temporal drift effect which influences the stability of the TiN sensitive electrode with the differential front-end offset circuit.The measurement system combines with shifting circuit,differential and instrument amplifiers.We employ the calibration circuit to compare with the variations of the output voltage,and expectably improve the stability and reliability of the TiN sensitive electrode by the novel calibration circuit.展开更多
Presented is a low noise interface circuit that is tuned to the needs of self-assembly monolayers biosensor SoC. The correlated double sampling(CDS) unit of the readout circuit can reduce 1/f noise, KTC noise and fixe...Presented is a low noise interface circuit that is tuned to the needs of self-assembly monolayers biosensor SoC. The correlated double sampling(CDS) unit of the readout circuit can reduce 1/f noise, KTC noise and fixed noise of micro arrays effectively. The circuit is simulated in a 0.6 μm/level 7 standard CMOS process, and the simulated results show the output voltage has a good linearity with the transducing current of the micro arrays. This is a novel circuit including four amplifiers sharing a common half-circuit and the noise reducing CDS unit. It could be widely used for micro array biosensors.展开更多
The output of uncooled microbolometer is nonuniform, and the traditional two-point nonuniformity correction method requires a tight restriction on substrate temperature. The circuit proposed by this article can relax ...The output of uncooled microbolometer is nonuniform, and the traditional two-point nonuniformity correction method requires a tight restriction on substrate temperature. The circuit proposed by this article can relax the restriction on the substrate temperature and perform nonuniformity correction when reading out the image signal. The dummy pixels reduce static current. And the Column shared DACs transfer correction data to the gates of MOS transistors and the positive reference edge of amplifier, to control the bias current of detector and dummy one, and set the start point of integration. This circuit has higher sensitivity, wider dynamic range, and frame frequency of more than 30 Hz for 128×128 array. PSPICE simulation results seem that this circuit functions well.展开更多
The architecture of a multi-channel front-end system is important for realizing a high-resolution PET system. We propose a novel front-end readout electronic system with TDC to deal with time information for PET syste...The architecture of a multi-channel front-end system is important for realizing a high-resolution PET system. We propose a novel front-end readout electronic system with TDC to deal with time information for PET system which can easily design the timing control. Each channel consists of a charge preamplifier, slow/fast shaper, discriminator and an analog memory. There are an ADC and a TDC to process the energy information and time information for each channel at the same time. In this paper, the whole system signals flow is all simulated by MATLAB. The simulation results show that the proposed system can process slender current from the detector and achieve the energy and time information. The proposed architecture can be applied to high-resolution PET imaging systems with multi-channel ASICs.展开更多
In the future, the Very Large Area gamma-ray Space Telescope is expected to observe high-energy electrons and gamma rays in the MeV to TeV range with unprecedented acceptance. As part of the detector suite, a high-ene...In the future, the Very Large Area gamma-ray Space Telescope is expected to observe high-energy electrons and gamma rays in the MeV to TeV range with unprecedented acceptance. As part of the detector suite, a high-energy imaging calorimeter(HEIC) is currently being developed as a homogeneous calorimeter that utilizes long bismuth germanate(BGO) scintillation crystals as both absorbers and detectors. To accurately measure the energy deposition in the BGO bar of HEIC, a highdynamic-range readout method using a silicon photomultiplier(SiPM) and multiphotodiode(PD) with different active areas has been proposed. A prototype readout system that adopts multichannel charge measurement ASICs was also developed to read out the combined system of SiPMs and PDs. Preliminary tests confirmed the feasibility of the readout scheme, which is expected to have a dynamic range close to 10~6.展开更多
There is an urgent need for high-quality and high-frequency clock generators for high-energy physics experiments.The transmission data rate exceeds 10 Gbps for a single channel in future readout electronics of silicon...There is an urgent need for high-quality and high-frequency clock generators for high-energy physics experiments.The transmission data rate exceeds 10 Gbps for a single channel in future readout electronics of silicon pixel detectors.Others,such as time measurement detectors,require a high time resolution based on the time-to-digital readout architecture.A phase-locked loop(PLL)is an essential and broadly used circuit in these applications.This study presents an application-specific integrated circuit of a low-jitter,low-power LC-tank that is PLL fabricated using 55-nm CMOS technology.It includes a 3rd-order frequency synthesis loop with a programmable bandwidth,a divide-by-2 pre-scaler,standard low-voltage differential signaling interfaces,and a current mode logic(CML)driver for clock transmissions.All the d-flip-flop dividers and phase-frequency detectors are protected from single-event upsets using the triple modular redundancy technique.The proposed VCO uses low-pass filters to suppress the noise from bias circuits.The tested LC-PLL covers a frequency locking range between 4.74 GHz and 5.92 GHz with two sub-bands.The jitter measurements of the frequency-halved clock(2.56 GHz)are less than 460 fs and 0.8 ps for the random and deterministic jitters,respectively,and a total of 7.5 ps peak-to-peak with a bit error rate of 10^(-12).The random and total jitter values for frequencies of 426 MHz and 20 MHz are less than 1.8 ps and 65 ps,respectively.The LC-PLL consumed 27 mW for the core and 73.8 mW in total.The measured results nearly coincided with the simulations and validated the analyses and tests.展开更多
A new wide-range fast readout system capable of adaptive identification is designed for wire scanners,which are used to measure beam profiles and emittance.This system is capable of handling varying current signals wi...A new wide-range fast readout system capable of adaptive identification is designed for wire scanners,which are used to measure beam profiles and emittance.This system is capable of handling varying current signals with Gaussian distributions and current pulses up to 1000 counts/s, as well as an input current range of 1 n A–1 m A. When tested, the resolution was found to exceed 3.68% for full scale, the nonlinearity was found to be less than 0.11%, and the measurement sensibility was found to be less than 5 p A. We believe that the system will play a crucial role in improving the measurement accuracy of beam diagnosis and the efficiency of accelerator operation,as well as decreasing the time required for beam tuning.This system was applied to the beam diagnosis of an injector II prototype for an accelerator-driven subcritical system and produced excellent measurement results. A description of the adaptive fast readout system for wire scanners is presented in this paper.展开更多
A readout electronics has been developed for the silicon strip array detector system of HIRFL-CSR-ETF.It consists of 48 front end electronics(FEE)boards,12 PXI-DAQ boards and one trigger board.It can implement energy ...A readout electronics has been developed for the silicon strip array detector system of HIRFL-CSR-ETF.It consists of 48 front end electronics(FEE)boards,12 PXI-DAQ boards and one trigger board.It can implement energy and time measurements of 4608 channels.Each FEE board is based on 6 ASICs(ATHED),which implements energy and time measurements of 96 channels.The PXI-DAQ board meets requirements of high-speed counting and amount of readout channels and can process signals of 4 FEEs.The trigger board is developed to select the valid events.The energy linearity of the readout electronics is better than 0.3%in the dynamic range of 0.1-0.7V.In the test with a standard triple alpha source,the energy resolution was 1.8%at 5.48 MeV.This readout electronics enables the silicon strip array system to identify particles of A<14.展开更多
文摘In this paper, the design of a novel low-noise front-end readout circuit for Cadmium zinc telluride (CdZnTe) X-ray and γ-ray detectors is described. The front-end readout circuits include the charge sensitive amplifier (CSA) and the CR-RC shaper is implemented in TSMC 0.35 μm mixed-signal CMOS technology. The die size of the prototype chip is 4.9 mm × 2.2 mm. The simulation results show that, the noise performance is 46 electrons + 10 electrons/pF, and power consumption is 1.65 mW per channel.
文摘The development of low-cost,non-enzymatic glucose biosensors is crucial for advancing accessible diabetes management.This paper presents the experimental testing of an extended-gate field-effect transistor(EG-FET)that uses a gold film as the sensing structure.The system innovatively employs a custom-designed inverting operational amplifier circuit for precise signal acquisition and an Arduino Nano platform for real-time data processing and visualization,eliminating the need for expensive laboratory equipment.At the core of the design is a depletion-mode MOSFET,whose current-voltage properties were characterized.The function of the sensor was demonstrated by testing its response to phosphate-buffered saline containing glucose at different concentrations.A clear modulation of the drain current in the linear region of the EG-FET was observed,and a preliminary analysis revealed a linear correlation between the output current and glucose concentration,indicating the system’s potential for quantitative detection.This study successfully validates the feasibility of a compact,cost-effective,and non-enzymatic EG-FET biosensing platform,establishing a solid foundation for future development of point-of-care diagnostic devices.
文摘Novel schemes for a charge sensitive amplifier （CSA） and a CR-（RC）, semi-Gaussian shaper in a fully integrated CMOS readout circuit for particle detectors are presented. The CSA is designed with poly-resistors as feedback components to reduce noise. Compared with conventional CSA, the input referred equivalent noise charge（ENC） is simulated to be reduced from 5036e to 2381e with a large detector capacitance of 150pF at the cost of 0.5V output swing loss. The CR-（RC）,semi-Gaussian shaper uses MOS transistors in the triode region in series with poly-resistors to compensate process variation without much linearity reduction.
基金The Natural Science Foundation of Jiangsu Province(No.BK2012559)Qing Lan Project of Jiangsu Province
文摘Based on an avalanche photodiode（ APD） detecting array working in Geiger mode（ GM-APD）, a high-performance infrared sensor readout integrated circuit（ ROIC） used for infrared 3D（ three-dimensional） imaging is proposed. The system mainly consists of three functional modules, including active quenching circuit（ AQC）, time-to-digital converter（ TDC） circuit and other timing controller circuit. Each AQC and TDC circuit together constitutes the pixel circuit. Under the cooperation with other modules, the current signal generated by the GM-APD sensor is detected by the AQC, and the photon time-of-flight（ TOF） is measured and converted to a digital signal output to achieve a better noise suppression and a higher detection sensitivity by the TDC. The ROIC circuit is fabricated by the CSMC 0. 5 μm standard CMOS technology. The array size is 8 × 8, and the center distance of two adjacent cells is 100μm. The measurement results of the chip showthat the performance of the circuit is good, and the chip can achieve 1 ns time resolution with a 250 MHz reference clock, and the circuit can be used in the array structure of the infrared detection system or focal plane array（ FPA）.
基金supported by the Fundamental Research Funds for the Central Universities under Grant No. 2009JBM001
文摘The diode infrared focal plane array uses the silicon diodes as a sensitive device for infrared signal measurement. By the infrared radiation, the infrared focal plane can produces small voltage signals. For the traditional readout circuit structures are designed to process current signals, they cannot be applied to it. In this paper, a new readout circuit for the diode un-cooled infrared focal plane array is developed. The principle of detector array signal readout and small signal amplification is given in detail. The readout circuit is designed and simulated by using the Central Semiconductor Manufacturing Corporation （CSMC） 0.5 μm complementary metal-oxide-semiconductor transistor （CMOS） technology library. Cadence Spectre simulation results show that the scheme can be applied to the CMOS readout integrated circuit （ROIC） with a larger array, such as 320×240 size array.
文摘A novel ultra-low-power readout integrated circuit(ROIC) for 1 024×1 024 ultraviolet(UV) AlGaN focal plane arrays(FPA) with 18 μm-pitch was presented. In order to optimize power consumption for UVFPA readout circuit these methods were adopted, which including single-terminal amplifier under subthreshold region as CTIA amplifier, common current source load for source follow(SF) buffer in column pixels and level shift circuits, and time-sharing tail current source for column buffer. The smallest operational current of CTIA in pixel unit is only 8.5 nA with 3.3 V power supply by using single-terminal amplifier. The ROIC has been fabricated in SMIC 0.18 μm 1P6M mixed signal process and also achieved better performances with the novel design of bias current adjustable. Furthermore, the overall power consumption of the chip is 67.3 mW at 2 MHz in 8-outputs mode by the above methods according to the experimental results.
基金supported by the National Natural Science Foundation of China (No.61006021)
文摘Integrated circuits of deep submicron(DSM) CMOS technology are advantageous in volume density, power consumption and thermal noise for multichannel particle detection systems,but there are challenges in the front-end circuit design.In this paper,we present a 0.18μm CMOS front-end readout circuit for low noise CdZnTe detectors in tens of pF capacitance.Solutions to the noise and gate leak problems in DSM technologies are discussed in detail.A prototype chip was designed,with a charge sensitive preamplifier,a 4th order semi-Gaussian shaper and several output drivers.Test results show that the chip has an equivalent noise charge of 164 e,without connecting it to a detector,with an integral nonlinearity of<0.21%and differential nonlinearity of<3.75%.
基金Supported by the National Natural Science Foundation of China (No.40704025)
文摘A low-noise readout integrated circuit for high-energy particle detector is presented.The noise of charge sensitive amplifier was suppressed by using single-side amplifier and resistors as source degeneration.Continuous-time semi-Gaussian filter is chosen to avoid switch noise.The peaking time of pulse shaper and the gain can be programmed to satisfy multi-application.The readout integrated circuit has been designed and fabricated using a 0.35 μm double-poly triple-metal CMOS technology.Test results show the functions of the readout integrated circuit are correct.The equivalent noise charge with no detector connected is 500–700 e in the typical mode,the gain is tunable within 13–130 mV/fC and the peaking time varies from 0.7 to 1.6 μs,in which the average gain is about 20.5 mV/fC,and the linearity reaches 99.2%.
文摘This paper describes a low-noise front-end readout circuit for CZT detectors based on TSMC 0.35 um mixed-single CMOS technology;mainly analyzes the noise model of the detector-preamplifier and presents the low-noise circuit schematic of charge sensitive preamplifier and shaper. Considering the parasitical influences, the circuit and layout-design are optimized to reduce noise. The preliminary simulation results show that, the equivalent noise charge (ENC) is 74 e﹣ (rms), noise slope is 9 e﹣/pF, power consumption is 2 mW, and non-linearity
文摘A high injection, large dynamic range, stable detector bias, small area and low power consumption CMOS readout circuit with background current suppression and correlated double sampling (CDS) for a high-resolution infrared focal plane array applications is proposed. The detector bias error in this structure is less than 0.1 mV. The input resistance is ideally zero, which is important to obtain high injection efficiency. Unit-cell occupies 10 μm × 15 μm area and consumes less than 0.4 mW power. Charge storag...
文摘The structure of the extended gate ion sensitive field effect transistor (EGISFET) is similar to the structure of the ion sensitive field effect transistor (ISFET).Moreover,the non-ideal effect of EGISFET is the main impediment to development of commercial processes for sensitive devices.It is necessary to promote the stability and reliability of the devices by employing calibration circuits and the better fabrication conditions.The temporal drift exists in the entire measurement experiment. Furthermore,in this study we can reduce the temporal drift effect which influences the stability of the TiN sensitive electrode with the differential front-end offset circuit.The measurement system combines with shifting circuit,differential and instrument amplifiers.We employ the calibration circuit to compare with the variations of the output voltage,and expectably improve the stability and reliability of the TiN sensitive electrode by the novel calibration circuit.
基金Natural Science Foundation Project of CQ(2007BB2176)
文摘Presented is a low noise interface circuit that is tuned to the needs of self-assembly monolayers biosensor SoC. The correlated double sampling(CDS) unit of the readout circuit can reduce 1/f noise, KTC noise and fixed noise of micro arrays effectively. The circuit is simulated in a 0.6 μm/level 7 standard CMOS process, and the simulated results show the output voltage has a good linearity with the transducing current of the micro arrays. This is a novel circuit including four amplifiers sharing a common half-circuit and the noise reducing CDS unit. It could be widely used for micro array biosensors.
基金the National Science Foundation of China (No:60377036).
文摘The output of uncooled microbolometer is nonuniform, and the traditional two-point nonuniformity correction method requires a tight restriction on substrate temperature. The circuit proposed by this article can relax the restriction on the substrate temperature and perform nonuniformity correction when reading out the image signal. The dummy pixels reduce static current. And the Column shared DACs transfer correction data to the gates of MOS transistors and the positive reference edge of amplifier, to control the bias current of detector and dummy one, and set the start point of integration. This circuit has higher sensitivity, wider dynamic range, and frame frequency of more than 30 Hz for 128×128 array. PSPICE simulation results seem that this circuit functions well.
文摘The architecture of a multi-channel front-end system is important for realizing a high-resolution PET system. We propose a novel front-end readout electronic system with TDC to deal with time information for PET system which can easily design the timing control. Each channel consists of a charge preamplifier, slow/fast shaper, discriminator and an analog memory. There are an ADC and a TDC to process the energy information and time information for each channel at the same time. In this paper, the whole system signals flow is all simulated by MATLAB. The simulation results show that the proposed system can process slender current from the detector and achieve the energy and time information. The proposed architecture can be applied to high-resolution PET imaging systems with multi-channel ASICs.
基金Foundation of China (Nos. 12227805, U1831206, 12103095, 12235012, 12273120, and 11973097)the Scientific Instrument Developing Project of the Chinese Academy of Sciences (No. GJJSTD20210009)。
文摘In the future, the Very Large Area gamma-ray Space Telescope is expected to observe high-energy electrons and gamma rays in the MeV to TeV range with unprecedented acceptance. As part of the detector suite, a high-energy imaging calorimeter(HEIC) is currently being developed as a homogeneous calorimeter that utilizes long bismuth germanate(BGO) scintillation crystals as both absorbers and detectors. To accurately measure the energy deposition in the BGO bar of HEIC, a highdynamic-range readout method using a silicon photomultiplier(SiPM) and multiphotodiode(PD) with different active areas has been proposed. A prototype readout system that adopts multichannel charge measurement ASICs was also developed to read out the combined system of SiPMs and PDs. Preliminary tests confirmed the feasibility of the readout scheme, which is expected to have a dynamic range close to 10~6.
基金supported in part by the National Natural Science Foundation of China(Nos.12005245,12075100,and 11775244)by the Scientific and Technological Innovation Project(No.2020000165)from the Institute of High Energy Physics,Chinese Academy of Sciences+1 种基金partially funded by the Scientific Instrument Development Project of the Chinese Academy of Sciences(No.ZDKYYQ20200007)Youth Innovation Promotion Association of the Chinese Academy of Sciences(No.Y201905).
文摘There is an urgent need for high-quality and high-frequency clock generators for high-energy physics experiments.The transmission data rate exceeds 10 Gbps for a single channel in future readout electronics of silicon pixel detectors.Others,such as time measurement detectors,require a high time resolution based on the time-to-digital readout architecture.A phase-locked loop(PLL)is an essential and broadly used circuit in these applications.This study presents an application-specific integrated circuit of a low-jitter,low-power LC-tank that is PLL fabricated using 55-nm CMOS technology.It includes a 3rd-order frequency synthesis loop with a programmable bandwidth,a divide-by-2 pre-scaler,standard low-voltage differential signaling interfaces,and a current mode logic(CML)driver for clock transmissions.All the d-flip-flop dividers and phase-frequency detectors are protected from single-event upsets using the triple modular redundancy technique.The proposed VCO uses low-pass filters to suppress the noise from bias circuits.The tested LC-PLL covers a frequency locking range between 4.74 GHz and 5.92 GHz with two sub-bands.The jitter measurements of the frequency-halved clock(2.56 GHz)are less than 460 fs and 0.8 ps for the random and deterministic jitters,respectively,and a total of 7.5 ps peak-to-peak with a bit error rate of 10^(-12).The random and total jitter values for frequencies of 426 MHz and 20 MHz are less than 1.8 ps and 65 ps,respectively.The LC-PLL consumed 27 mW for the core and 73.8 mW in total.The measured results nearly coincided with the simulations and validated the analyses and tests.
基金supported by the National Natural Science Foundation of China(Nos.11475233,11705257,and 11775285)
文摘A new wide-range fast readout system capable of adaptive identification is designed for wire scanners,which are used to measure beam profiles and emittance.This system is capable of handling varying current signals with Gaussian distributions and current pulses up to 1000 counts/s, as well as an input current range of 1 n A–1 m A. When tested, the resolution was found to exceed 3.68% for full scale, the nonlinearity was found to be less than 0.11%, and the measurement sensibility was found to be less than 5 p A. We believe that the system will play a crucial role in improving the measurement accuracy of beam diagnosis and the efficiency of accelerator operation,as well as decreasing the time required for beam tuning.This system was applied to the beam diagnosis of an injector II prototype for an accelerator-driven subcritical system and produced excellent measurement results. A description of the adaptive fast readout system for wire scanners is presented in this paper.
基金Supported by the National Natural Science Foundation of China(Nos.11005135 and 11079045)the Important Direction Project of the CAS Knowledge Innovation Program(No.KJCX2-YW-N27)the Foundation of director of Institute Modern Physics,CAS(No.Y207170SZ0)
文摘A readout electronics has been developed for the silicon strip array detector system of HIRFL-CSR-ETF.It consists of 48 front end electronics(FEE)boards,12 PXI-DAQ boards and one trigger board.It can implement energy and time measurements of 4608 channels.Each FEE board is based on 6 ASICs(ATHED),which implements energy and time measurements of 96 channels.The PXI-DAQ board meets requirements of high-speed counting and amount of readout channels and can process signals of 4 FEEs.The trigger board is developed to select the valid events.The energy linearity of the readout electronics is better than 0.3%in the dynamic range of 0.1-0.7V.In the test with a standard triple alpha source,the energy resolution was 1.8%at 5.48 MeV.This readout electronics enables the silicon strip array system to identify particles of A<14.
