An efficient design-for-testability （DFT） technique is proposed to achieve low overhead for scan-based delay fault testing. Existing techniques for delay test such as skewed-load or broadside make the test generatio...An efficient design-for-testability （DFT） technique is proposed to achieve low overhead for scan-based delay fault testing. Existing techniques for delay test such as skewed-load or broadside make the test generation process complex and produce lower coverage for scan-based designs as compared with non-scan designs, whereas techniques such as enhanced-scan test can make the test easy but need an extra holding latch to add substantial hardware overhead. A new tri-state holding logic is presented to replace the common holding latch in enhanced-scan test to get a substantial low hardware overhead. This scheme can achieve low delay overhead by avoiding the holding latch on the critical timing scan path. What＇s more, this method can also keep the state and signal activity in the combinational circuit from the scan during data scan-in operation to reduce the power dissipation. Experiment results on a set of ISCAS89 benchmarks show the efficiency of the proposed scheme.展开更多
As a method for testing a sequential circuit efficiently, a scan design is usually used. But, since this design has some drawbacks, a non-scan testable design should be discussed. The testable design can be implemente...As a method for testing a sequential circuit efficiently, a scan design is usually used. But, since this design has some drawbacks, a non-scan testable design should be discussed. The testable design can be implemented by enhancing controllability and observability. This paper discusses a non-scan testable design for a sequential circuit by only focusing the improvement of controllability. The proposed design modifies a circuit so that all the FFs can be directly controlled by primary input lines in a test mode. Experimental results show that we can get a good testability using this method.展开更多
Parity testing is one of the compact testing techniques, which, traditionally, relies on applying all 2^n input combinations to an n-input combinational circuit without need of knowing the implementation of the circui...Parity testing is one of the compact testing techniques, which, traditionally, relies on applying all 2^n input combinations to an n-input combinational circuit without need of knowing the implementation of the circuits under test. The faults can be detected just by observing and comparing its parity of whole output of circuit with the expectation one. The way seemed to be less interesting to the test eagineers in the past days, mainly due to the reasons of its exhaustive testing and time-cousuming, which became a barrier as the number of input lines gets growing. However its great facility and convenience in testing still interest to the engineers who need to have a quick look at the qualities of the circuits without generating the test patterns for a given circuit to be tested. In this paper, a new approach called pseudo-parity testing is presented to deal with the dilemma we are facing： i. e. to change an exhaustive parity testing into a non-exhaustive one, followed by a pseudo- parity testable design to help realize the new way of pseudo-parity testing. The idea of pseudo-parity testing presented in this paper may resume its spirits towards its promising future.展开更多
The quality factor of class diagram is critical because it has significant influence on overall quality of the product, delivered finally. Testability has been recognized as a key factor to software quality. Estimatin...The quality factor of class diagram is critical because it has significant influence on overall quality of the product, delivered finally. Testability has been recognized as a key factor to software quality. Estimating testability at design stage is a criterion of crucial significance for software designers to make the design more testable. Taking view of this fact, this paper identifies testability factors namely effectiveness and reusability and establishes the correlation among testability, effectiveness and reusability and justifies the correlation with the help of statistical measures. Moreover study developed metric based testability estimation model and developed model has been validated using experimental test. Subsequently, research integrates the empirical validation of the developed model for high level acceptance. Finally a hypothesis test performs by the two standards to test the significance of correlation.展开更多
The quality factor of class diagram is critical because it has a significant influence on overall quality of the product, delivered finally. Testability analysis, when done early in the software creation process, is a...The quality factor of class diagram is critical because it has a significant influence on overall quality of the product, delivered finally. Testability analysis, when done early in the software creation process, is a criterion of critical importance to software quality. Reusability is an important quality factor to testability. Its early measurement in object oriented software especially at design phase, allows a design to be reapplied to a new problem without much extra effort. This research paper proposes a research framework for quantification process and does an extensive review on reusability of object oriented software. A metrics based model “Reusability Quantification of Object Oriented Design” has been proposed by establishing the relationship among design properties and reusability and justifying the correlation with the help of statistical measures. Also, “Reusability Quantification Model” is empirically validated and contextual significance of the study shows the high correlation for model acceptance. This research paper facilitates to software developers and designer, the inclusion of reusability quantification model to access and quantify software reusability for quality product.展开更多
Testable design techniques for systolic motion estimators based on M-testability conditions are proposed in this paper. The whole motion estimator can be viewed as a two-dimensional iterative logic array （ILA） of pr...Testable design techniques for systolic motion estimators based on M-testability conditions are proposed in this paper. The whole motion estimator can be viewed as a two-dimensional iterative logic array （ILA） of processing elements （PEs） and multiplying elements （MULs）. The functions of each PE and MUL are modified to be bijective to meet the M-testable conditions. The number of test patterns is 2^w, where w denotes the word length of a PE. The proposed testable design techniques are also suitable for built-in self-test implementation. According to experimental results, our approaches can achieve 99.27 % fault coverage. The area overhead is about 9 %. To verify our approaches, an experimental chip is also implemented.展开更多
Test selection design(TSD)is an important technique for improving product maintainability,reliability and reducing lifecycle costs.In recent years,although some researchers have addressed the design problem of test se...Test selection design(TSD)is an important technique for improving product maintainability,reliability and reducing lifecycle costs.In recent years,although some researchers have addressed the design problem of test selection,the correlation between test outcomes has not been sufficiently considered in test metrics modeling.This study proposes a new approach that combines copula and D-Vine copula to address the correlation issue in TSD.First,the copula is utilized to model FIR on the joint distribution.Furthermore,the D-Vine copula is applied to model the FDR and FAR.Then,a particle swarm optimization is employed to select the optimal testing scheme.Finally,the efficacy of the proposed method is validated through experimentation on a negative feedback circuit.展开更多
Prognostics and health management （PHM） significantly improves system availability and reliability, and reduces the cost of system operations. Design for testability （DFT） developed concurrently with system design...Prognostics and health management （PHM） significantly improves system availability and reliability, and reduces the cost of system operations. Design for testability （DFT） developed concurrently with system design is an important way to improve PHM capability. Testability modeling and analysis are the foundation of DFT. This paper proposes a novel approach of testability modeling and analysis based on failure evolution mechanisms. At the component level, the fault progression-related information of each unit under test （UUT） in a system is obtained by means of failure modes, evolution mechanisms, effects and criticality analysis （FMEMECA）, and then the failure-symptom dependency can be generated. At the system level, the dynamic attributes of UUTs are assigned by using the bond graph methodology, and then the symptom-test dependency can be obtained by means of the functional flow method. Based on the failure-symptom and symptom-test dependencies, testability analysis for PHM systems can be realized. A shunt motor is used to verify the application of the approach proposed in this paper. Experimental results show that this approach is able to be applied to testability modeling and analysis for PHM systems very well, and the analysis results can provide a guide for engineers to design for testability in order to improve PHM performance.展开更多
Sensor selection and optimization is one of the important parts in design for testability. To address the problems that the traditional sensor optimization selection model does not take the requirements of prognostics...Sensor selection and optimization is one of the important parts in design for testability. To address the problems that the traditional sensor optimization selection model does not take the requirements of prognostics and health management especially fault prognostics for testability into account and does not consider the impacts of sensor actual attributes on fault detectability, a novel sensor optimization selection model is proposed. Firstly, a universal architecture for sensor selection and optimization is provided. Secondly, a new testability index named fault predictable rate is defined to describe fault prognostics requirements for testability. Thirdly, a sensor selection and optimization model for prognostics and health management is constructed, which takes sensor cost as objective function and the defined testability indexes as constraint conditions. Due to NP-hard property of the model, a generic algorithm is designed to obtain the optimal solution. At last, a case study is presented to demonstrate the sensor selection approach for a stable tracking servo platform. The application results and comparison analysis show the proposed model and algorithm are effective and feasible. This approach can be used to select sensors for prognostics and health management of any system.展开更多
In this paper, an Ethernet controller SoC solution and its low power design for testability （DFT） for information appliances are presented. On a single chip, an enhanced one-cycle 8-bit micro controller unit （MCU）...In this paper, an Ethernet controller SoC solution and its low power design for testability （DFT） for information appliances are presented. On a single chip, an enhanced one-cycle 8-bit micro controller unit （MCU）, media access control （MAC） circuit and embedded memories such as static random access memory （SRAM）, read only memory （ROM） and flash are all integrated together. In order to achieve high fault coverage, at the same time with low test power, different DFT techniques are adopted for different circuits： the scan circuit that reduces switching activity is implemented for digital logic circuits; BIST-based method is employed for the on-chip SRAM and ROM. According to the fault-modeling of embedded flash, we resort to a March-like method for flash built in self test （BIST）. By all means above, the result shows that the fault coverage may reach 97%, and the SoC chip is implemented successfully by using 0.25 μm two-poly four-metal mixed signal complementary metal oxide semiconductor （CMOS） technology, the die area is 4.8×4.6 mm^2. Test results show that the maximum throughput of Ethemet packets may reach 7Mb·s^1.展开更多
In view of the low level testability of armored equipment,the important significance of armored equipment testability growth is discussed in this paper.The failure mode effects and criticality analysis( FMECA) method ...In view of the low level testability of armored equipment,the important significance of armored equipment testability growth is discussed in this paper.The failure mode effects and criticality analysis( FMECA) method to realize testability growth is introduced.Centering on the testability growth demands of new armored equipment,the deficiencies of traditional FMECA are analyzed.And an enhanced FMECA( EFMECA) method is proposed.The method increases the analysis contents,combines the information before the failure occurrence and impending failure modes together organically.Then the failure symptoms is analyzed,the failure modes and effects is determined,and the state development trend is predicted.Finally,the application of EFMECA method is illustrated by the example of the failure mode of typical armored equipment engine.展开更多
This paper proposes a non-scan design-for-testability method for register-transfer level circuits where a circuit consists of a controller and a data path. It achieves complete fault efficiency with low hardware overh...This paper proposes a non-scan design-for-testability method for register-transfer level circuits where a circuit consists of a controller and a data path. It achieves complete fault efficiency with low hardware overhead and at-speed testing.展开更多
This paper presents a new BIST method for RTL data paths based on single-control testability, a new concept of testability. The BIST method adopts hierarchical test. Test pattern generators are placed only on primary ...This paper presents a new BIST method for RTL data paths based on single-control testability, a new concept of testability. The BIST method adopts hierarchical test. Test pattern generators are placed only on primary inputs and test patterns are propagated to and fed into each module. Test responses are similarly propagated to response analyzers placed only on primary outputs. For the propagation of test patterns and test responses paths existing in the data path are utilized. The DFT method for the single-control testability is also proposed. The advantages of the proposed method are high fault coverage (for single Stuck-at faults), low hardware overhead and capability of at-speed test. Moreover, test patterns generated by test pattern generators can be fed into each module at consecutive system clocks, and thus, the BIST can also detect some faults of other fault models (e.g., transition faults and delay faults) that require consecutive application of test patterns at speed of system clock.展开更多
Frameworks are time-tested highly reusable architectural skeleton structures. They are designed ‘abstract’ and ‘inco- mplete’ and are designed with predefined points of variability, known as hot spots, to be custo...Frameworks are time-tested highly reusable architectural skeleton structures. They are designed ‘abstract’ and ‘inco- mplete’ and are designed with predefined points of variability, known as hot spots, to be customized later at the time of framework reuse. Frameworks are reusable entities thus demand stricter and rigorous testing in comparison to one- time use application. The overall cost of framework development may be reduced by designing frameworks with high testability. This paper aims at discussing a few metric models for testability analysis of object-oriented frameworks in an attempt to having quantitative data on testability to be used to plan and monitor framework testing activities so that the framework testing effort and hence the overall framework development effort may be brought down.展开更多
Nowadays, application model systems for decision-making based on non-classical logic such as Paraconsistent Logic are used successfully in the treatment of uncertainties. The method presented in this paper is based on...Nowadays, application model systems for decision-making based on non-classical logic such as Paraconsistent Logic are used successfully in the treatment of uncertainties. The method presented in this paper is based on the fundamental concepts of Paraconsistent Annotated Logic with annotation of 2 values (PAL2v). In this study, two algorithms based on PAL2v are presented gradually, to extract the effects of the contradiction in signals of information from a database of uncertain knowledge. The Paraconsistent Extractors Algorithms of Contradiction Effect-Para Extrctr is applied to filters of networks of analyses (PANets) of signal information, where uncertain and contradictory signals may be found. Software test case scenarios are subordinated to an application model of Paraconsistent decision-making, which provides an analysis using Paraconsistent Logic in the treatment of uncertainties for design software testing strategies. This quality-quantity criterion to evaluate the software product quality is based on the characteristics of software testability analysis. The Para consistent reasoning application model system presented in this case study, reveals itself to be more efficient than the traditional methods because it has the potential to offer an appropriate treatment to different originally contradicting source information.展开更多
基金This project was supported by the National Natural Science Foundation of China (90407007).
文摘An efficient design-for-testability （DFT） technique is proposed to achieve low overhead for scan-based delay fault testing. Existing techniques for delay test such as skewed-load or broadside make the test generation process complex and produce lower coverage for scan-based designs as compared with non-scan designs, whereas techniques such as enhanced-scan test can make the test easy but need an extra holding latch to add substantial hardware overhead. A new tri-state holding logic is presented to replace the common holding latch in enhanced-scan test to get a substantial low hardware overhead. This scheme can achieve low delay overhead by avoiding the holding latch on the critical timing scan path. What＇s more, this method can also keep the state and signal activity in the combinational circuit from the scan during data scan-in operation to reduce the power dissipation. Experiment results on a set of ISCAS89 benchmarks show the efficiency of the proposed scheme.
文摘As a method for testing a sequential circuit efficiently, a scan design is usually used. But, since this design has some drawbacks, a non-scan testable design should be discussed. The testable design can be implemented by enhancing controllability and observability. This paper discusses a non-scan testable design for a sequential circuit by only focusing the improvement of controllability. The proposed design modifies a circuit so that all the FFs can be directly controlled by primary input lines in a test mode. Experimental results show that we can get a good testability using this method.
基金This work was supported by National Natural Science Foundation of China under the grant No .60173029 and 60473033
文摘Parity testing is one of the compact testing techniques, which, traditionally, relies on applying all 2^n input combinations to an n-input combinational circuit without need of knowing the implementation of the circuits under test. The faults can be detected just by observing and comparing its parity of whole output of circuit with the expectation one. The way seemed to be less interesting to the test eagineers in the past days, mainly due to the reasons of its exhaustive testing and time-cousuming, which became a barrier as the number of input lines gets growing. However its great facility and convenience in testing still interest to the engineers who need to have a quick look at the qualities of the circuits without generating the test patterns for a given circuit to be tested. In this paper, a new approach called pseudo-parity testing is presented to deal with the dilemma we are facing： i. e. to change an exhaustive parity testing into a non-exhaustive one, followed by a pseudo- parity testable design to help realize the new way of pseudo-parity testing. The idea of pseudo-parity testing presented in this paper may resume its spirits towards its promising future.
文摘The quality factor of class diagram is critical because it has significant influence on overall quality of the product, delivered finally. Testability has been recognized as a key factor to software quality. Estimating testability at design stage is a criterion of crucial significance for software designers to make the design more testable. Taking view of this fact, this paper identifies testability factors namely effectiveness and reusability and establishes the correlation among testability, effectiveness and reusability and justifies the correlation with the help of statistical measures. Moreover study developed metric based testability estimation model and developed model has been validated using experimental test. Subsequently, research integrates the empirical validation of the developed model for high level acceptance. Finally a hypothesis test performs by the two standards to test the significance of correlation.
文摘The quality factor of class diagram is critical because it has a significant influence on overall quality of the product, delivered finally. Testability analysis, when done early in the software creation process, is a criterion of critical importance to software quality. Reusability is an important quality factor to testability. Its early measurement in object oriented software especially at design phase, allows a design to be reapplied to a new problem without much extra effort. This research paper proposes a research framework for quantification process and does an extensive review on reusability of object oriented software. A metrics based model “Reusability Quantification of Object Oriented Design” has been proposed by establishing the relationship among design properties and reusability and justifying the correlation with the help of statistical measures. Also, “Reusability Quantification Model” is empirically validated and contextual significance of the study shows the high correlation for model acceptance. This research paper facilitates to software developers and designer, the inclusion of reusability quantification model to access and quantify software reusability for quality product.
文摘Testable design techniques for systolic motion estimators based on M-testability conditions are proposed in this paper. The whole motion estimator can be viewed as a two-dimensional iterative logic array （ILA） of processing elements （PEs） and multiplying elements （MULs）. The functions of each PE and MUL are modified to be bijective to meet the M-testable conditions. The number of test patterns is 2^w, where w denotes the word length of a PE. The proposed testable design techniques are also suitable for built-in self-test implementation. According to experimental results, our approaches can achieve 99.27 % fault coverage. The area overhead is about 9 %. To verify our approaches, an experimental chip is also implemented.
基金supported by the National Natural Science Foundation of China(No.62303293,62303414)the China Postdoctoral Science Foundation(No.2023M732176,2023M741821)the Zhejiang Province Postdoctoral Selected Foundation(No.ZJ2023143).
文摘Test selection design(TSD)is an important technique for improving product maintainability,reliability and reducing lifecycle costs.In recent years,although some researchers have addressed the design problem of test selection,the correlation between test outcomes has not been sufficiently considered in test metrics modeling.This study proposes a new approach that combines copula and D-Vine copula to address the correlation issue in TSD.First,the copula is utilized to model FIR on the joint distribution.Furthermore,the D-Vine copula is applied to model the FDR and FAR.Then,a particle swarm optimization is employed to select the optimal testing scheme.Finally,the efficacy of the proposed method is validated through experimentation on a negative feedback circuit.
基金the National Natural Science Foundation of China(No.51175502)
文摘Prognostics and health management （PHM） significantly improves system availability and reliability, and reduces the cost of system operations. Design for testability （DFT） developed concurrently with system design is an important way to improve PHM capability. Testability modeling and analysis are the foundation of DFT. This paper proposes a novel approach of testability modeling and analysis based on failure evolution mechanisms. At the component level, the fault progression-related information of each unit under test （UUT） in a system is obtained by means of failure modes, evolution mechanisms, effects and criticality analysis （FMEMECA）, and then the failure-symptom dependency can be generated. At the system level, the dynamic attributes of UUTs are assigned by using the bond graph methodology, and then the symptom-test dependency can be obtained by means of the functional flow method. Based on the failure-symptom and symptom-test dependencies, testability analysis for PHM systems can be realized. A shunt motor is used to verify the application of the approach proposed in this paper. Experimental results show that this approach is able to be applied to testability modeling and analysis for PHM systems very well, and the analysis results can provide a guide for engineers to design for testability in order to improve PHM performance.
基金National Natural Science Foundation of China (51175502)
文摘Sensor selection and optimization is one of the important parts in design for testability. To address the problems that the traditional sensor optimization selection model does not take the requirements of prognostics and health management especially fault prognostics for testability into account and does not consider the impacts of sensor actual attributes on fault detectability, a novel sensor optimization selection model is proposed. Firstly, a universal architecture for sensor selection and optimization is provided. Secondly, a new testability index named fault predictable rate is defined to describe fault prognostics requirements for testability. Thirdly, a sensor selection and optimization model for prognostics and health management is constructed, which takes sensor cost as objective function and the defined testability indexes as constraint conditions. Due to NP-hard property of the model, a generic algorithm is designed to obtain the optimal solution. At last, a case study is presented to demonstrate the sensor selection approach for a stable tracking servo platform. The application results and comparison analysis show the proposed model and algorithm are effective and feasible. This approach can be used to select sensors for prognostics and health management of any system.
基金Supported by the National High Technology Research and Development Program of China (2006AA01Z226)
文摘In this paper, an Ethernet controller SoC solution and its low power design for testability （DFT） for information appliances are presented. On a single chip, an enhanced one-cycle 8-bit micro controller unit （MCU）, media access control （MAC） circuit and embedded memories such as static random access memory （SRAM）, read only memory （ROM） and flash are all integrated together. In order to achieve high fault coverage, at the same time with low test power, different DFT techniques are adopted for different circuits： the scan circuit that reduces switching activity is implemented for digital logic circuits; BIST-based method is employed for the on-chip SRAM and ROM. According to the fault-modeling of embedded flash, we resort to a March-like method for flash built in self test （BIST）. By all means above, the result shows that the fault coverage may reach 97%, and the SoC chip is implemented successfully by using 0.25 μm two-poly four-metal mixed signal complementary metal oxide semiconductor （CMOS） technology, the die area is 4.8×4.6 mm^2. Test results show that the maximum throughput of Ethemet packets may reach 7Mb·s^1.
文摘In view of the low level testability of armored equipment,the important significance of armored equipment testability growth is discussed in this paper.The failure mode effects and criticality analysis( FMECA) method to realize testability growth is introduced.Centering on the testability growth demands of new armored equipment,the deficiencies of traditional FMECA are analyzed.And an enhanced FMECA( EFMECA) method is proposed.The method increases the analysis contents,combines the information before the failure occurrence and impending failure modes together organically.Then the failure symptoms is analyzed,the failure modes and effects is determined,and the state development trend is predicted.Finally,the application of EFMECA method is illustrated by the example of the failure mode of typical armored equipment engine.
文摘This paper proposes a non-scan design-for-testability method for register-transfer level circuits where a circuit consists of a controller and a data path. It achieves complete fault efficiency with low hardware overhead and at-speed testing.
文摘This paper presents a new BIST method for RTL data paths based on single-control testability, a new concept of testability. The BIST method adopts hierarchical test. Test pattern generators are placed only on primary inputs and test patterns are propagated to and fed into each module. Test responses are similarly propagated to response analyzers placed only on primary outputs. For the propagation of test patterns and test responses paths existing in the data path are utilized. The DFT method for the single-control testability is also proposed. The advantages of the proposed method are high fault coverage (for single Stuck-at faults), low hardware overhead and capability of at-speed test. Moreover, test patterns generated by test pattern generators can be fed into each module at consecutive system clocks, and thus, the BIST can also detect some faults of other fault models (e.g., transition faults and delay faults) that require consecutive application of test patterns at speed of system clock.
文摘Frameworks are time-tested highly reusable architectural skeleton structures. They are designed ‘abstract’ and ‘inco- mplete’ and are designed with predefined points of variability, known as hot spots, to be customized later at the time of framework reuse. Frameworks are reusable entities thus demand stricter and rigorous testing in comparison to one- time use application. The overall cost of framework development may be reduced by designing frameworks with high testability. This paper aims at discussing a few metric models for testability analysis of object-oriented frameworks in an attempt to having quantitative data on testability to be used to plan and monitor framework testing activities so that the framework testing effort and hence the overall framework development effort may be brought down.
文摘Nowadays, application model systems for decision-making based on non-classical logic such as Paraconsistent Logic are used successfully in the treatment of uncertainties. The method presented in this paper is based on the fundamental concepts of Paraconsistent Annotated Logic with annotation of 2 values (PAL2v). In this study, two algorithms based on PAL2v are presented gradually, to extract the effects of the contradiction in signals of information from a database of uncertain knowledge. The Paraconsistent Extractors Algorithms of Contradiction Effect-Para Extrctr is applied to filters of networks of analyses (PANets) of signal information, where uncertain and contradictory signals may be found. Software test case scenarios are subordinated to an application model of Paraconsistent decision-making, which provides an analysis using Paraconsistent Logic in the treatment of uncertainties for design software testing strategies. This quality-quantity criterion to evaluate the software product quality is based on the characteristics of software testability analysis. The Para consistent reasoning application model system presented in this case study, reveals itself to be more efficient than the traditional methods because it has the potential to offer an appropriate treatment to different originally contradicting source information.
