In this paper,a 16-bit 1MSPS foreground calibration successive approximation register analog-to-digital converter(SAR ADC)is developed by the CMOS 0.25μm process.An on-chip all-digital foreground weights calibration ...In this paper,a 16-bit 1MSPS foreground calibration successive approximation register analog-to-digital converter(SAR ADC)is developed by the CMOS 0.25μm process.An on-chip all-digital foreground weights calibration technique integrating self-calibration weight measurement with PN port auto-balance technique is designed to improve the performance and lower the costs of the developed SAR ADC.The SAR ADC has a chip area of 2.7×2.4 mm^2,and consumes only 100μW at the 2.5 V supply voltage with 100 KSPS.The INL and DNL are both less than 0.5 LSB.展开更多
Digital calibration techniques are widely developed to cancel the non-idealities of the pipelined Analog-to-Digital Converters (ADCs). This letter presents a fast foreground digital calibration technique based on the ...Digital calibration techniques are widely developed to cancel the non-idealities of the pipelined Analog-to-Digital Converters (ADCs). This letter presents a fast foreground digital calibration technique based on the analysis of error sources which influence the resolution of pipelined ADCs. This method estimates the gain error of the ADC prototype quickly and calibrates the ADC simultaneously in the operation time. Finally, a 10 bit, 100 Ms/s pipelined ADC is implemented and calibrated. The simulation results show that the digital calibration technique has its efficiency with fewer operation cycles.展开更多
This paper describes a fast digital calibration scheme for pipelined analog-to-digital converters（ADCs）. The proposed method corrects the nonlinearity caused by finite opamp gain and capacitor mismatch in multiplyin...This paper describes a fast digital calibration scheme for pipelined analog-to-digital converters（ADCs）. The proposed method corrects the nonlinearity caused by finite opamp gain and capacitor mismatch in multiplying digital-to-analog converters（MDACs）.The considered calibration technique takes the advantages of both foreground and background calibration schemes.In this combination calibration algorithm,a novel parallel background calibration with signal-shifted correlation is proposed,and its calibration cycle is very short.The details of this technique are described in the example of a 14-bit 100 Msample/s pipelined ADC.The high convergence speed of this background calibration is achieved by three means.First,a modified 1.5-bit stage is proposed in order to allow the injection of a large pseudo-random dithering without missing code.Second,before correlating the signal,it is shifted according to the input signal so that the correlation error converges quickly.Finally,the front pipeline stages are calibrated simultaneously rather than stage by stage to reduce the calibration tracking constants.Simulation results confirm that the combination calibration has a fast startup process and a short background calibration cycle of 2×2^（21） conversions.展开更多
This paper presents a 12-bit column-parallel successive approximation register analog-to-digital con- verter （SAR ADC） for high-speed CMOS image sensors. A segmented binary-weighted switched capacitor digital- to-an...This paper presents a 12-bit column-parallel successive approximation register analog-to-digital con- verter （SAR ADC） for high-speed CMOS image sensors. A segmented binary-weighted switched capacitor digital- to-analog converter （CDAC） and a staggered structure MOM unit capacitor is used to reduce the ADC area and to make its layout fit double pixel pitches. An electrical field shielding layout method is proposed to eliminate the parasitic capacitance on the top plate of the unit capacitor. A dynamic power control technique is proposed to reduce the power consumption of a single channel during readout. An off-chip foreground digital calibration is adopted to compensate for the nonlinearity due to the mismatch of unit capacitors among the CDAC. The prototype SAR ADC is fabricated in a 0.18 μm 1P5M CIS process. A single SAR ADC occupies 20 × 2020μm2. Sampling at 833 kS/s, the measured differential nonlinearity, integral nonlinearity and effective number of bits of SAR ADC with calibration are 0.9/-1 LSB, 1/-1.1 LSB and 11.24 bits, respectively; the power consumption is only 0.26 mW under a 1.8-W supply and decreases linearly as the frame rate decreases.展开更多
A single-channel 2 GS/s 8-bit analog-to-digital converter in 90 nm CMOS process technology is pre- sented. It utilizes cascade folding architecture, which incorporates an additional inter-stage sample-and-hold ampli- ...A single-channel 2 GS/s 8-bit analog-to-digital converter in 90 nm CMOS process technology is pre- sented. It utilizes cascade folding architecture, which incorporates an additional inter-stage sample-and-hold ampli- fier between the folding circuits to enhance the quantization time. It also uses the foreground on-chip digital-assisted calibration circuit to improve the linearity of the circuit. The post simulation results demonstrate that it has a dif- ferential nonlinearity 〈 4-0.3 LSB and an integral nonlinearity 〈 ±0.25 LSB at the Nyquist frequency. Moreover, 7.338 effective numbers of bits can be achieved at 2 GSPS. The whole chip area is 0.88 × 0.88 mm2 with the pad. It consumes 210 mW from a 1.2 V single supply.展开更多
文摘In this paper,a 16-bit 1MSPS foreground calibration successive approximation register analog-to-digital converter(SAR ADC)is developed by the CMOS 0.25μm process.An on-chip all-digital foreground weights calibration technique integrating self-calibration weight measurement with PN port auto-balance technique is designed to improve the performance and lower the costs of the developed SAR ADC.The SAR ADC has a chip area of 2.7×2.4 mm^2,and consumes only 100μW at the 2.5 V supply voltage with 100 KSPS.The INL and DNL are both less than 0.5 LSB.
文摘Digital calibration techniques are widely developed to cancel the non-idealities of the pipelined Analog-to-Digital Converters (ADCs). This letter presents a fast foreground digital calibration technique based on the analysis of error sources which influence the resolution of pipelined ADCs. This method estimates the gain error of the ADC prototype quickly and calibrates the ADC simultaneously in the operation time. Finally, a 10 bit, 100 Ms/s pipelined ADC is implemented and calibrated. The simulation results show that the digital calibration technique has its efficiency with fewer operation cycles.
基金supported by the National Key Project,China(No.2008zx010200001)
文摘This paper describes a fast digital calibration scheme for pipelined analog-to-digital converters（ADCs）. The proposed method corrects the nonlinearity caused by finite opamp gain and capacitor mismatch in multiplying digital-to-analog converters（MDACs）.The considered calibration technique takes the advantages of both foreground and background calibration schemes.In this combination calibration algorithm,a novel parallel background calibration with signal-shifted correlation is proposed,and its calibration cycle is very short.The details of this technique are described in the example of a 14-bit 100 Msample/s pipelined ADC.The high convergence speed of this background calibration is achieved by three means.First,a modified 1.5-bit stage is proposed in order to allow the injection of a large pseudo-random dithering without missing code.Second,before correlating the signal,it is shifted according to the input signal so that the correlation error converges quickly.Finally,the front pipeline stages are calibrated simultaneously rather than stage by stage to reduce the calibration tracking constants.Simulation results confirm that the combination calibration has a fast startup process and a short background calibration cycle of 2×2^（21） conversions.
基金Project supported by the National Natural Science Foundation of China(No.61234003)the Special Funds for Major State Basic Research Project of China(No.2011CB932902)
文摘This paper presents a 12-bit column-parallel successive approximation register analog-to-digital con- verter （SAR ADC） for high-speed CMOS image sensors. A segmented binary-weighted switched capacitor digital- to-analog converter （CDAC） and a staggered structure MOM unit capacitor is used to reduce the ADC area and to make its layout fit double pixel pitches. An electrical field shielding layout method is proposed to eliminate the parasitic capacitance on the top plate of the unit capacitor. A dynamic power control technique is proposed to reduce the power consumption of a single channel during readout. An off-chip foreground digital calibration is adopted to compensate for the nonlinearity due to the mismatch of unit capacitors among the CDAC. The prototype SAR ADC is fabricated in a 0.18 μm 1P5M CIS process. A single SAR ADC occupies 20 × 2020μm2. Sampling at 833 kS/s, the measured differential nonlinearity, integral nonlinearity and effective number of bits of SAR ADC with calibration are 0.9/-1 LSB, 1/-1.1 LSB and 11.24 bits, respectively; the power consumption is only 0.26 mW under a 1.8-W supply and decreases linearly as the frame rate decreases.
基金Project supported by National Basic Research Program of China(No.2010CB327400)the Natural Science Foundation of Shandong Province,China(No.ZR2013FL007)
文摘A single-channel 2 GS/s 8-bit analog-to-digital converter in 90 nm CMOS process technology is pre- sented. It utilizes cascade folding architecture, which incorporates an additional inter-stage sample-and-hold ampli- fier between the folding circuits to enhance the quantization time. It also uses the foreground on-chip digital-assisted calibration circuit to improve the linearity of the circuit. The post simulation results demonstrate that it has a dif- ferential nonlinearity 〈 4-0.3 LSB and an integral nonlinearity 〈 ±0.25 LSB at the Nyquist frequency. Moreover, 7.338 effective numbers of bits can be achieved at 2 GSPS. The whole chip area is 0.88 × 0.88 mm2 with the pad. It consumes 210 mW from a 1.2 V single supply.
