This study proposes a new generation of floating gate transistors(FGT)with a novel built-in security feature.The new device has applications in guarding the IC chips against the current reverse engineering techniques,...This study proposes a new generation of floating gate transistors(FGT)with a novel built-in security feature.The new device has applications in guarding the IC chips against the current reverse engineering techniques,including scanning capacitance microscopy(SCM).The SCM measures the change in the C–V characteristic of the device as a result of placing a minute amount of charge on the floating gate,even in nano-meter scales.The proposed design only adds a simple processing step to the conventional FGT by adding an oppositely doped implanted layer to the substrate.This new structure was first analyzed theoretically and then a two-dimensional model was extracted to represent its C–V characteristic.Furthermore,this model was verified with a simulation.In addition,the C–V characteristics relevant to the SCM measurement of both conventional and the new designed FGT were compared to discuss the effectiveness of the added layer in masking the state of the transistor.The effect of change in doping concentration of the implanted layer on the C–V characteristics was also investigated.Finally,the feasibility of the proposed design was examined by comparing its I–V characteristics with the traditional FGT.展开更多
As a typical in-memory computing hardware design, nonvolatile ternary content-addressable memories(TCAMs) enable the logic operation and data storage for high throughout in parallel big data processing. However,TCAM c...As a typical in-memory computing hardware design, nonvolatile ternary content-addressable memories(TCAMs) enable the logic operation and data storage for high throughout in parallel big data processing. However,TCAM cells based on conventional silicon-based devices suffer from structural complexity and large footprintlimitations. Here, we demonstrate an ultrafast nonvolatile TCAM cell based on the MoTe2/hBN/multilayergraphene (MLG) van der Waals heterostructure using a top-gated partial floating-gate field-effect transistor(PFGFET) architecture. Based on its ambipolar transport properties, the carrier type in the source/drain andcentral channel regions of the MoTe2 channel can be efficiently tuned by the control gate and top gate, respectively,enabling the reconfigurable operation of the device in either memory or FET mode. When working inthe memory mode, it achieves an ultrafast 60 ns programming/erase speed with a current on-off ratio of ∼105,excellent retention capability, and robust endurance. When serving as a reconfigurable transistor, unipolar p-typeand n-type FETs are obtained by adopting ultrafast 60 ns control-gate voltage pulses with different polarities.The monolithic integration of memory and logic within a single device enables the content-addressable memory(CAM) functionality. Finally, by integrating two PFGFETs in parallel, a TCAM cell with a high current ratioof ∼10^(5) between the match and mismatch states is achieved without requiring additional peripheral circuitry.These results provide a promising route for the design of high-performance TCAM devices for future in-memorycomputing applications.展开更多
Recently,the biologically inspired intelligent artificial visual neural system has aroused enormous interest.However,there are still significant obstacles in pursuing large-scale parallel and efficient visual memory a...Recently,the biologically inspired intelligent artificial visual neural system has aroused enormous interest.However,there are still significant obstacles in pursuing large-scale parallel and efficient visual memory and recognition.In this study,we demonstrate a 28×28 synaptic devices array for the artificial visual neuromorphic system,within the size of 0.7×0.7 cm 2,which integrates sensing,memory,and processing functions.The highly uniform floating-gate synaptic transistors array were constructed by the wafer-scale grown monolayer molybdenum disulfide with Au nanoparticles(NPs)acting as the electrons capture layers.Various synaptic plasticity behaviors have been achieved owing to the switchable electronic storage performance.The excellent optical/electrical coordination capabilities were implemented by paralleled processing both the optical and electrical signals the synaptic array of 784 devices,enabling to realize the badges and letters writing and erasing process.Finally,the established artificial visual convolutional neural network(CNN)through optical/electrical signal modulation can reach the high digit recognition accuracy of 96.5%.Therefore,our results provide a feasible route for future large-scale integrated artificial visual neuromorphic system.展开更多
文摘This study proposes a new generation of floating gate transistors(FGT)with a novel built-in security feature.The new device has applications in guarding the IC chips against the current reverse engineering techniques,including scanning capacitance microscopy(SCM).The SCM measures the change in the C–V characteristic of the device as a result of placing a minute amount of charge on the floating gate,even in nano-meter scales.The proposed design only adds a simple processing step to the conventional FGT by adding an oppositely doped implanted layer to the substrate.This new structure was first analyzed theoretically and then a two-dimensional model was extracted to represent its C–V characteristic.Furthermore,this model was verified with a simulation.In addition,the C–V characteristics relevant to the SCM measurement of both conventional and the new designed FGT were compared to discuss the effectiveness of the added layer in masking the state of the transistor.The effect of change in doping concentration of the implanted layer on the C–V characteristics was also investigated.Finally,the feasibility of the proposed design was examined by comparing its I–V characteristics with the traditional FGT.
基金supported by the National Key Research&Development Projects of China(Grant No.2022YFA1204100)National Natural Science Foundation of China(Grant No.62488201)+1 种基金CAS Project for Young Scientists in Basic Research(YSBR-003)the Innovation Program of Quantum Science and Technology(2021ZD0302700)。
文摘As a typical in-memory computing hardware design, nonvolatile ternary content-addressable memories(TCAMs) enable the logic operation and data storage for high throughout in parallel big data processing. However,TCAM cells based on conventional silicon-based devices suffer from structural complexity and large footprintlimitations. Here, we demonstrate an ultrafast nonvolatile TCAM cell based on the MoTe2/hBN/multilayergraphene (MLG) van der Waals heterostructure using a top-gated partial floating-gate field-effect transistor(PFGFET) architecture. Based on its ambipolar transport properties, the carrier type in the source/drain andcentral channel regions of the MoTe2 channel can be efficiently tuned by the control gate and top gate, respectively,enabling the reconfigurable operation of the device in either memory or FET mode. When working inthe memory mode, it achieves an ultrafast 60 ns programming/erase speed with a current on-off ratio of ∼105,excellent retention capability, and robust endurance. When serving as a reconfigurable transistor, unipolar p-typeand n-type FETs are obtained by adopting ultrafast 60 ns control-gate voltage pulses with different polarities.The monolithic integration of memory and logic within a single device enables the content-addressable memory(CAM) functionality. Finally, by integrating two PFGFETs in parallel, a TCAM cell with a high current ratioof ∼10^(5) between the match and mismatch states is achieved without requiring additional peripheral circuitry.These results provide a promising route for the design of high-performance TCAM devices for future in-memorycomputing applications.
基金supported by National Natural Science Foundation of China(NSFC,Grand No.62127810,61804009)State Key Laboratory of Explosion Science and Safety Protection(QNKT24-03),Xiaomi Young Scholar,Beijing Institute of Technology Research Fund Program for Young Scholars and Analysis&Testing Center,Beijing Institute of Technology.
文摘Recently,the biologically inspired intelligent artificial visual neural system has aroused enormous interest.However,there are still significant obstacles in pursuing large-scale parallel and efficient visual memory and recognition.In this study,we demonstrate a 28×28 synaptic devices array for the artificial visual neuromorphic system,within the size of 0.7×0.7 cm 2,which integrates sensing,memory,and processing functions.The highly uniform floating-gate synaptic transistors array were constructed by the wafer-scale grown monolayer molybdenum disulfide with Au nanoparticles(NPs)acting as the electrons capture layers.Various synaptic plasticity behaviors have been achieved owing to the switchable electronic storage performance.The excellent optical/electrical coordination capabilities were implemented by paralleled processing both the optical and electrical signals the synaptic array of 784 devices,enabling to realize the badges and letters writing and erasing process.Finally,the established artificial visual convolutional neural network(CNN)through optical/electrical signal modulation can reach the high digit recognition accuracy of 96.5%.Therefore,our results provide a feasible route for future large-scale integrated artificial visual neuromorphic system.
