This article presents a low voltage low power configuration of current differencing transconductance amplifier（CDTA）based on floating gate MOSFET.The proposed CDTA variant operates at lower supply voltage±1.4 V...This article presents a low voltage low power configuration of current differencing transconductance amplifier（CDTA）based on floating gate MOSFET.The proposed CDTA variant operates at lower supply voltage±1.4 V with total static power dissipation of 2.60 mW due to the low voltage feature of floating gate MOSFET.High transconductance up to 6.21 mA/V is achieved with extended linear range of the circuit i.e.±130μA.Two applications are illustrated to demonstrate the effectiveness of the proposed active block.A quadrature oscillator is realized using FGMOS based CDTA,two capacitors,and a resistor.The resistor is implemented using two NMOSFETs to provide high linearity and tunablility.Another application is the Schmitt trigger circuit based on the proposed CDTA variant.All circuits are simulated by using SPICE and TSMC 130 nm technology.展开更多
With technology scaling,stability,power dissipation,and device variability,the impact of process,voltage and temperature(PVT)variations has become dominant for static random access memory(SRAM)analysis for productivit...With technology scaling,stability,power dissipation,and device variability,the impact of process,voltage and temperature(PVT)variations has become dominant for static random access memory(SRAM)analysis for productivity and failure.In this paper,ten-transistors(10T)and low power eight-transistors SRAM cells are redesigned using floating-gate MOS transistors(FGMOS).Power centric parameters viz.read power,write power,hold power and delay are the performance analysis metrics.Further,the stochastic parameter variation to study the variability tolerance of the redesigned cell,PVT variations and Monte Carlo simulations have been carried out for 10T FGMOS SRAM cell.Stability has been illustrated with the conventional butterfly method giving read static noise margin(RSNM)and write static noise margin(WSNM)metrics for read stability and write ability,respectively.A comparative analysis with standard six-transistor SRAM cell is carried out.HSPICE simulative analysis has been carried out for 32 nm technology node.The redesigned FGMOS SRAM cells provide improved performance.Also,these are robust and reliability efficient with comparable stability.展开更多
文摘This article presents a low voltage low power configuration of current differencing transconductance amplifier（CDTA）based on floating gate MOSFET.The proposed CDTA variant operates at lower supply voltage±1.4 V with total static power dissipation of 2.60 mW due to the low voltage feature of floating gate MOSFET.High transconductance up to 6.21 mA/V is achieved with extended linear range of the circuit i.e.±130μA.Two applications are illustrated to demonstrate the effectiveness of the proposed active block.A quadrature oscillator is realized using FGMOS based CDTA,two capacitors,and a resistor.The resistor is implemented using two NMOSFETs to provide high linearity and tunablility.Another application is the Schmitt trigger circuit based on the proposed CDTA variant.All circuits are simulated by using SPICE and TSMC 130 nm technology.
文摘With technology scaling,stability,power dissipation,and device variability,the impact of process,voltage and temperature(PVT)variations has become dominant for static random access memory(SRAM)analysis for productivity and failure.In this paper,ten-transistors(10T)and low power eight-transistors SRAM cells are redesigned using floating-gate MOS transistors(FGMOS).Power centric parameters viz.read power,write power,hold power and delay are the performance analysis metrics.Further,the stochastic parameter variation to study the variability tolerance of the redesigned cell,PVT variations and Monte Carlo simulations have been carried out for 10T FGMOS SRAM cell.Stability has been illustrated with the conventional butterfly method giving read static noise margin(RSNM)and write static noise margin(WSNM)metrics for read stability and write ability,respectively.A comparative analysis with standard six-transistor SRAM cell is carried out.HSPICE simulative analysis has been carried out for 32 nm technology node.The redesigned FGMOS SRAM cells provide improved performance.Also,these are robust and reliability efficient with comparable stability.
