In this paper,a high precision vernier delay line(VDL) TDC(Time-to-Digital Convertor) in an actel flash-based Field-Programmable-Gate-Arrays A3PE1500 is implemented,achieving a resolution of 16.4-ps root mean square v...In this paper,a high precision vernier delay line(VDL) TDC(Time-to-Digital Convertor) in an actel flash-based Field-Programmable-Gate-Arrays A3PE1500 is implemented,achieving a resolution of 16.4-ps root mean square value or 42-ps averaged bin size.The TDC has a dead time of about 200 ns while the dynamic range is 655.36 μs.The double delay lines method is employed to cut the dead time in half to improve its performance.As the bin size of the TDC is dependent on temperature,a compensation algorithm is adopted as temperature drift correction,and the TDC shows satisfying performance in a temperature range from –5℃ to +55℃.展开更多
With extensive use of flash-based field-programmable gate arrays(FPGAs) in military and aerospace applications, single-event effects(SEEs) of FPGAs induced by radiations have been a major concern. In this paper, we pr...With extensive use of flash-based field-programmable gate arrays(FPGAs) in military and aerospace applications, single-event effects(SEEs) of FPGAs induced by radiations have been a major concern. In this paper, we present SEE experimental study of a flash-based FPGA from Microsemi Pro ASIC3 product family. The relation between the cross section and different linear energy transfer(LET) values for the logic tiles and embedded RAM blocks is obtained. The results show that the sequential logic cross section depends not too much on operating frequency of the device. And the relationship between 0 →1 upsets(zeros) and 1 →0 upsets(ones) is different for different kinds of D-flip-flops. The devices are not sensitive to SEL up to a LET of 99.0 Me V cm2/mg.Post-beam tests show that the programming module is damaged due to the high-LET ions.展开更多
基金Supported by State Key Program of National Natural Science of China under Grant No.11079003Fundamental Research Funds for the Central Universities(No.WK2030040023,and WK2030040015)
文摘In this paper,a high precision vernier delay line(VDL) TDC(Time-to-Digital Convertor) in an actel flash-based Field-Programmable-Gate-Arrays A3PE1500 is implemented,achieving a resolution of 16.4-ps root mean square value or 42-ps averaged bin size.The TDC has a dead time of about 200 ns while the dynamic range is 655.36 μs.The double delay lines method is employed to cut the dead time in half to improve its performance.As the bin size of the TDC is dependent on temperature,a compensation algorithm is adopted as temperature drift correction,and the TDC shows satisfying performance in a temperature range from –5℃ to +55℃.
基金the National Natural Science Foundation of China(Nos.11079045,11179003 and 11305233)
文摘With extensive use of flash-based field-programmable gate arrays(FPGAs) in military and aerospace applications, single-event effects(SEEs) of FPGAs induced by radiations have been a major concern. In this paper, we present SEE experimental study of a flash-based FPGA from Microsemi Pro ASIC3 product family. The relation between the cross section and different linear energy transfer(LET) values for the logic tiles and embedded RAM blocks is obtained. The results show that the sequential logic cross section depends not too much on operating frequency of the device. And the relationship between 0 →1 upsets(zeros) and 1 →0 upsets(ones) is different for different kinds of D-flip-flops. The devices are not sensitive to SEL up to a LET of 99.0 Me V cm2/mg.Post-beam tests show that the programming module is damaged due to the high-LET ions.
