In this paper,a high precision vernier delay line(VDL) TDC(Time-to-Digital Convertor) in an actel flash-based Field-Programmable-Gate-Arrays A3PE1500 is implemented,achieving a resolution of 16.4-ps root mean square v...In this paper,a high precision vernier delay line(VDL) TDC(Time-to-Digital Convertor) in an actel flash-based Field-Programmable-Gate-Arrays A3PE1500 is implemented,achieving a resolution of 16.4-ps root mean square value or 42-ps averaged bin size.The TDC has a dead time of about 200 ns while the dynamic range is 655.36 μs.The double delay lines method is employed to cut the dead time in half to improve its performance.As the bin size of the TDC is dependent on temperature,a compensation algorithm is adopted as temperature drift correction,and the TDC shows satisfying performance in a temperature range from –5℃ to +55℃.展开更多
With extensive use of flash-based field-programmable gate arrays(FPGAs) in military and aerospace applications, single-event effects(SEEs) of FPGAs induced by radiations have been a major concern. In this paper, we pr...With extensive use of flash-based field-programmable gate arrays(FPGAs) in military and aerospace applications, single-event effects(SEEs) of FPGAs induced by radiations have been a major concern. In this paper, we present SEE experimental study of a flash-based FPGA from Microsemi Pro ASIC3 product family. The relation between the cross section and different linear energy transfer(LET) values for the logic tiles and embedded RAM blocks is obtained. The results show that the sequential logic cross section depends not too much on operating frequency of the device. And the relationship between 0 →1 upsets(zeros) and 1 →0 upsets(ones) is different for different kinds of D-flip-flops. The devices are not sensitive to SEL up to a LET of 99.0 Me V cm2/mg.Post-beam tests show that the programming module is damaged due to the high-LET ions.展开更多
针对在现场可编程门阵列(Field Programmable Gate Array,FPGA)上实现基于极化敏感阵列的多重信号分类(Multiple Signal Classification,MUSIC)算法进行二维波达方向(Direction of Arrival,DOA)和二维极化参数联合估计时,硬件资源占用...针对在现场可编程门阵列(Field Programmable Gate Array,FPGA)上实现基于极化敏感阵列的多重信号分类(Multiple Signal Classification,MUSIC)算法进行二维波达方向(Direction of Arrival,DOA)和二维极化参数联合估计时,硬件资源占用大、运行时间长的问题,提出了一种基于极化MUSIC算法的四维参数联合估计FPGA实现架构。该架构包括信号协方差矩阵计算模块、Jacobi旋转模块、噪声子空间提取模块、两级空间谱搜索模块和极化参数计算模块。Jacobi旋转模块被拆分为多个可复用模块,并采用查找表模块生成旋转矩阵。一级空间谱搜索模块通过二维DOA搜索初步确定信源的角度信息。二级空间谱搜索模块根据一级搜索的角度结果确定二级搜索区域各点的极化信息,并计算该区域的四维空间谱,区域内最小值对应的四维参数信息即为最终估计的信源方向角、俯仰角、极化辅助角和极化相位角。仿真结果表明,与传统极化MUSIC算法的四维搜索算法相比,该架构避免了大量四维空间谱计算,同时保证了四维参数估计的精度,显著减少了运行时间和硬件资源消耗。展开更多
针对水下目标方位(Direction of Arrival,DOA)估计准确性实时性的要求,理论分析了互质阵列模型、压缩感知DOA估计的原理,设计实现了基于FPGA的互质阵列压缩感知算法DOA估计系统。首先介绍了系统开发环境,包括平台选择、开发流程等;其次...针对水下目标方位(Direction of Arrival,DOA)估计准确性实时性的要求,理论分析了互质阵列模型、压缩感知DOA估计的原理,设计实现了基于FPGA的互质阵列压缩感知算法DOA估计系统。首先介绍了系统开发环境,包括平台选择、开发流程等;其次,介绍了硬件系统的整体框架,重点说明了PS与PL之间的数据传递流程和硬件各模块实现过程,并仿真验证了该系统的正确性。在Xilinx FPGA平台上进行了湖试数据的处理,完成了数据运算参数的统计收集,验证了DOA估计的有效性,并计算了运算耗时。结果表明,所设计的系统能够正确完成DOA估计并满足实时性要求。展开更多
基金Supported by State Key Program of National Natural Science of China under Grant No.11079003Fundamental Research Funds for the Central Universities(No.WK2030040023,and WK2030040015)
文摘In this paper,a high precision vernier delay line(VDL) TDC(Time-to-Digital Convertor) in an actel flash-based Field-Programmable-Gate-Arrays A3PE1500 is implemented,achieving a resolution of 16.4-ps root mean square value or 42-ps averaged bin size.The TDC has a dead time of about 200 ns while the dynamic range is 655.36 μs.The double delay lines method is employed to cut the dead time in half to improve its performance.As the bin size of the TDC is dependent on temperature,a compensation algorithm is adopted as temperature drift correction,and the TDC shows satisfying performance in a temperature range from –5℃ to +55℃.
基金the National Natural Science Foundation of China(Nos.11079045,11179003 and 11305233)
文摘With extensive use of flash-based field-programmable gate arrays(FPGAs) in military and aerospace applications, single-event effects(SEEs) of FPGAs induced by radiations have been a major concern. In this paper, we present SEE experimental study of a flash-based FPGA from Microsemi Pro ASIC3 product family. The relation between the cross section and different linear energy transfer(LET) values for the logic tiles and embedded RAM blocks is obtained. The results show that the sequential logic cross section depends not too much on operating frequency of the device. And the relationship between 0 →1 upsets(zeros) and 1 →0 upsets(ones) is different for different kinds of D-flip-flops. The devices are not sensitive to SEL up to a LET of 99.0 Me V cm2/mg.Post-beam tests show that the programming module is damaged due to the high-LET ions.
文摘针对在现场可编程门阵列(Field Programmable Gate Array,FPGA)上实现基于极化敏感阵列的多重信号分类(Multiple Signal Classification,MUSIC)算法进行二维波达方向(Direction of Arrival,DOA)和二维极化参数联合估计时,硬件资源占用大、运行时间长的问题,提出了一种基于极化MUSIC算法的四维参数联合估计FPGA实现架构。该架构包括信号协方差矩阵计算模块、Jacobi旋转模块、噪声子空间提取模块、两级空间谱搜索模块和极化参数计算模块。Jacobi旋转模块被拆分为多个可复用模块,并采用查找表模块生成旋转矩阵。一级空间谱搜索模块通过二维DOA搜索初步确定信源的角度信息。二级空间谱搜索模块根据一级搜索的角度结果确定二级搜索区域各点的极化信息,并计算该区域的四维空间谱,区域内最小值对应的四维参数信息即为最终估计的信源方向角、俯仰角、极化辅助角和极化相位角。仿真结果表明,与传统极化MUSIC算法的四维搜索算法相比,该架构避免了大量四维空间谱计算,同时保证了四维参数估计的精度,显著减少了运行时间和硬件资源消耗。
文摘针对水下目标方位(Direction of Arrival,DOA)估计准确性实时性的要求,理论分析了互质阵列模型、压缩感知DOA估计的原理,设计实现了基于FPGA的互质阵列压缩感知算法DOA估计系统。首先介绍了系统开发环境,包括平台选择、开发流程等;其次,介绍了硬件系统的整体框架,重点说明了PS与PL之间的数据传递流程和硬件各模块实现过程,并仿真验证了该系统的正确性。在Xilinx FPGA平台上进行了湖试数据的处理,完成了数据运算参数的统计收集,验证了DOA估计的有效性,并计算了运算耗时。结果表明,所设计的系统能够正确完成DOA估计并满足实时性要求。
