With extensive use of flash-based field-programmable gate arrays(FPGAs) in military and aerospace applications, single-event effects(SEEs) of FPGAs induced by radiations have been a major concern. In this paper, we pr...With extensive use of flash-based field-programmable gate arrays(FPGAs) in military and aerospace applications, single-event effects(SEEs) of FPGAs induced by radiations have been a major concern. In this paper, we present SEE experimental study of a flash-based FPGA from Microsemi Pro ASIC3 product family. The relation between the cross section and different linear energy transfer(LET) values for the logic tiles and embedded RAM blocks is obtained. The results show that the sequential logic cross section depends not too much on operating frequency of the device. And the relationship between 0 →1 upsets(zeros) and 1 →0 upsets(ones) is different for different kinds of D-flip-flops. The devices are not sensitive to SEL up to a LET of 99.0 Me V cm2/mg.Post-beam tests show that the programming module is damaged due to the high-LET ions.展开更多
Upset errors in 90-nm 64 Mb NOR-type floating-gate Flash memory induced by accelerated ^（129）Xe and ^（209）Bi ions are investigated in detail. The linear energy transfer covers the range from 50 to 99.8 Me V/（mg/c...Upset errors in 90-nm 64 Mb NOR-type floating-gate Flash memory induced by accelerated ^（129）Xe and ^（209）Bi ions are investigated in detail. The linear energy transfer covers the range from 50 to 99.8 Me V/（mg/cm^2）. When the memory chips are powered off during heavy ions irradiation, single-event-latch-up and single-event-function-interruption are excluded,and only 0-〉1 upset errors in the memory array are observed. These error bit rates seem very difficult to achieve and cannot be simply recovered based on the power cycle. The number of error bits shows a strong dependence on the linear energy transfer（LET）. Under room-temperature annealing conditions, the upset errors can be reduced by about two orders of magnitude using rewrite/reprogram operations, but they subsequently increase once again in a few minutes after the power cycle. High-temperature annealing can diminish almost all error bits, which are affected by the lower LET ^（129）Xe ions. The percolation path between the floating-gate（FG） and the substrate contributes to the radiation-induced leakage current, and has been identified as the root cause of the upset errors of the Flash memory array in this work.展开更多
基金the National Natural Science Foundation of China(Nos.11079045,11179003 and 11305233)
文摘With extensive use of flash-based field-programmable gate arrays(FPGAs) in military and aerospace applications, single-event effects(SEEs) of FPGAs induced by radiations have been a major concern. In this paper, we present SEE experimental study of a flash-based FPGA from Microsemi Pro ASIC3 product family. The relation between the cross section and different linear energy transfer(LET) values for the logic tiles and embedded RAM blocks is obtained. The results show that the sequential logic cross section depends not too much on operating frequency of the device. And the relationship between 0 →1 upsets(zeros) and 1 →0 upsets(ones) is different for different kinds of D-flip-flops. The devices are not sensitive to SEL up to a LET of 99.0 Me V cm2/mg.Post-beam tests show that the programming module is damaged due to the high-LET ions.
基金Project supported by the National Natural Science Foundation of China(Grant No.616340084)the Youth Innovation Promotion Association of CAS(Grant No.2014101)+1 种基金the International Cooperation Project of CASthe Austrian-Chinese Cooperative R&D Projects(Grant No.172511KYSB20150006)
文摘Upset errors in 90-nm 64 Mb NOR-type floating-gate Flash memory induced by accelerated ^（129）Xe and ^（209）Bi ions are investigated in detail. The linear energy transfer covers the range from 50 to 99.8 Me V/（mg/cm^2）. When the memory chips are powered off during heavy ions irradiation, single-event-latch-up and single-event-function-interruption are excluded,and only 0-〉1 upset errors in the memory array are observed. These error bit rates seem very difficult to achieve and cannot be simply recovered based on the power cycle. The number of error bits shows a strong dependence on the linear energy transfer（LET）. Under room-temperature annealing conditions, the upset errors can be reduced by about two orders of magnitude using rewrite/reprogram operations, but they subsequently increase once again in a few minutes after the power cycle. High-temperature annealing can diminish almost all error bits, which are affected by the lower LET ^（129）Xe ions. The percolation path between the floating-gate（FG） and the substrate contributes to the radiation-induced leakage current, and has been identified as the root cause of the upset errors of the Flash memory array in this work.
