In this paper, the three-dimensional （3D） coupling effect is discussed for nanowire junctionless silicon-on-insulator （SOI） FinFETs. With fin width decreasing from 100 nm to 7 nm, the electric field induced by the...In this paper, the three-dimensional （3D） coupling effect is discussed for nanowire junctionless silicon-on-insulator （SOI） FinFETs. With fin width decreasing from 100 nm to 7 nm, the electric field induced by the lateral gates increases and therefore the influence of back gate on the threshold voltage weakens. For a narrow and tall fin, the lateral gates mainly control the channel and therefore the effect of back gate decreases. A simple two-dimensional （2D） potential model is proposed for the subthreshold region of junctionless SO1 FinFET. TCAD simulations validate our model. It can be used to extract the threshold voltage and doping concentration. In addition, the tuning of back gate on the threshold voltage can be predicted.展开更多
A 2D analytical electrostatics analysis for the cross-section of a FinFET (or tri-gate MOSFET) is performed to calculate the threshold voltage.The analysis results in a modified gate capacitance with a coefficient H i...A 2D analytical electrostatics analysis for the cross-section of a FinFET (or tri-gate MOSFET) is performed to calculate the threshold voltage.The analysis results in a modified gate capacitance with a coefficient H introduced to model the effect of tri-gates and its asymptotic behavior in 2D is that for double-gate MOSFET.The potential profile obtained analytically at the cross-section agrees well with numerical simulations.A compact threshold voltage model for FinFET,comprising quantum mechanical effects,is then proposed.It is concluded that both gate capacitance and threshold voltage will increase with a decreased height,or a decreased gate-oxide thickness of the top gate,which is a trend in FinFET design.展开更多
FinFET technologies are becoming the mainstream process as technology scales down. Based on a 28-nm bulk p- FinFET device, we have investigated the fin width and height dependence of bipolar amplification for heavy-io...FinFET technologies are becoming the mainstream process as technology scales down. Based on a 28-nm bulk p- FinFET device, we have investigated the fin width and height dependence of bipolar amplification for heavy-ion-irradiated FinFETs by 3D TCAD numerical simulation. Simulation results show that due to a well bipolar conduction mechanism rather than a channel （fin） conduction path, the transistors with narrower fins exhibit a diminished bipolar amplification effect, while the fin height presents a trivial effect on the bipolar amplification and charge collection. The results also indicate that the single event transient （SET） pulse width can be mitigated about 35% at least by optimizing the ratio of fin width and height, which can provide guidance for radiation-hardened applications in bulk FinFET technology.展开更多
The rapid development of by the device scaling down. encountered difficulties and CMOS technology is driven Classical MOS devices have challenges as scaling down to nanoscale [1], which seriously affects the device p...The rapid development of by the device scaling down. encountered difficulties and CMOS technology is driven Classical MOS devices have challenges as scaling down to nanoscale [1], which seriously affects the device performance and limits the further development of CMOS technology. Because of the excellent control over short-channel effects and high current drive capability, novel multi-gate MOS devices have been regarded for years as the most attractive devices to continue the CMOS technology development following ＂Moore＇s law＂ [2]. Among which FinFET, mainly proposed by Hisamoto et al.展开更多
We use an electro-thermal coupled Monte Carlo simulation framework to investigate the self-heating effect（SHE） in 14 nm bulk n Fin FETs with ambient temperature（TA） from 220 to 400 K. Based on this method, nonloca...We use an electro-thermal coupled Monte Carlo simulation framework to investigate the self-heating effect（SHE） in 14 nm bulk n Fin FETs with ambient temperature（TA） from 220 to 400 K. Based on this method, nonlocal heat generation can be achieved. Contact thermal resistances of Si/Metal and Si/Si O_2 are selected to ensure that the source and drain heat dissipation paths are the first two heat dissipation paths. The results are listed below：（i） not all input power（Q_（input） turns into heat generation in the device region and some is taken out by the thermal non-equilibrium carriers, owing to the serious non-equilibrium transport;（ii） a higher TA leads to a larger ratio of input power turning into heat generation in the device region at the same operating voltages;（iii） SHE can lead to serious degradation in the carrier transport, which will increase when TA increases;（iv） the current degradation can be 8.9% when Vds = 0.7 V, Vgs = 1 V and TA = 400 K;（v） device thermal resistance（Rth） increases with increasing of TA, which is seriously impacted by the non-equilibrium transport. Hence, the impact of TA should be carefully considered when investigating SHE in nanoscale devices.展开更多
A new simulation method and test instrument has been adopted to verify the traditional stress simulation in FinFET. First, a new algorithm named lattice kinetic Monte Carlo （LKMC） is used to simulate the SiGe epitax...A new simulation method and test instrument has been adopted to verify the traditional stress simulation in FinFET. First, a new algorithm named lattice kinetic Monte Carlo （LKMC） is used to simulate the SiGe epitaxy in source/drain regions and the stress distribution is consequently extracted after the LKMC simulation. Systematic comparison between the traditional polyhedron method and the LKMC method is carried out. The results confirm that extracted stress from both methods is consistent, which verifies the validity of traditional polyhedron method for the purpose of simulating stress in FinFET. In the following experiment, p-type FinFETs with SiGe stressors in source/drain regions are fabricated. The nano beam diffraction （NBD） method is employed to characterize the strain in Si fin. The strain value from the NBD test agrees well with the value extracted from traditional polyhedron simulation.展开更多
Sub-20 nm node bulk FinFET PMOS devices with an all-last high-k/metal gate （HK/MG） process are fabricated and the influence of a series of device parameters on the device scaling is investigated. The high and thin F...Sub-20 nm node bulk FinFET PMOS devices with an all-last high-k/metal gate （HK/MG） process are fabricated and the influence of a series of device parameters on the device scaling is investigated. The high and thin Fin structure with a tapered sidewall shows better performance than the normal Fin structure. The punch through stop layer （PTSL） and source drain extension （SDE） doping profiles are carefully optimized. The device without SDE annealing shows a larger drive current than that with SDE annealing due to better Si crystal regrowth in the amorphous Fin structure after source/drain implantation. The band-edged MG has a better short channel effect immunity, but the lower effective work function （EWF） MG shows a larger driveability. A tradeoff choice for different EWF MGs should be carefully designed for the device＇s scaling.展开更多
Nowadays FinFET devices have replaced the MOS devices almost in all complex integrated circuits of electronic gadgets like computer peripherals, tablets, and smartphones in portable electronics. The scaling of FinFET ...Nowadays FinFET devices have replaced the MOS devices almost in all complex integrated circuits of electronic gadgets like computer peripherals, tablets, and smartphones in portable electronics. The scaling of FinFET is ongoing and the analog/RF performance is most affected by increased SCEs(short channel effects) in sub22 nm technology nodes. This paper explores the analog/RF performance study and analysis of high performance device-D2(conventional Hf02 spacer SOI FinFET) and device-D3(source/drain extended Hf02 spacer SOI FinFET) over the device-D1(conventional Si3 N4 spacer SOI FinFET) at 20 nm technology node through the 3-D(dimensional) simulation process. The major performance parameters like I(ON current), I(OFF current), gm(transconductance), gd(output conductance), A(intrinsic gain), SS(sub-threshold slope), TGF = g/I(trans-conductance generation factor), VEA(early voltage), GTFP(gain trans-conductance frequency product), TFP(tansconductance frequency product), GFP(gain frequency product), and f(cut-off frequency) are studied for evaluating the analog/RF performance of different flavored SOI FinFET structures. For analog performance evaluation,device-D3 and D2 give better results in terms of gm, ID(drain current) and SS parameters, and for RF performance evaluation device-D1 is better in terms of f, GTFP, TFP, and GFP parameters both at low and high values of V=0.05 V and V=0.7 V respectively.展开更多
We investigate the influence of gate-source/drain （G-S/D） misalignment on the performance of bulk fin field effect transistors （FinFETs） through the three-dimensional （3D） full band Monte Carlo simulator. Severa...We investigate the influence of gate-source/drain （G-S/D） misalignment on the performance of bulk fin field effect transistors （FinFETs） through the three-dimensional （3D） full band Monte Carlo simulator. Several scat- tering mechanisms, such as acoustic and optical phonon scattering, ionized impurity scattering, impact ionization scattering and surface roughness scattering are considered in our simulator. The influence of G-S/D overlap and underlap on the on-states performance and carrier transport of bulk FinFETs are mainly discussed in our work. Our results show that the on-states currents increase with the increment of G-D/S overlap length and the positions of a potential barrier and average electron energy maximum vary with the G-D/S overlap length. The carrier transport phenomena in bulk FinFETs are due to the effect of scattering and the electric field in the overlap/underlap regime.展开更多
基金supported by the Research Program of the National University of Defense Technology(Grant No.JC 13-06-04)
文摘In this paper, the three-dimensional （3D） coupling effect is discussed for nanowire junctionless silicon-on-insulator （SOI） FinFETs. With fin width decreasing from 100 nm to 7 nm, the electric field induced by the lateral gates increases and therefore the influence of back gate on the threshold voltage weakens. For a narrow and tall fin, the lateral gates mainly control the channel and therefore the effect of back gate decreases. A simple two-dimensional （2D） potential model is proposed for the subthreshold region of junctionless SO1 FinFET. TCAD simulations validate our model. It can be used to extract the threshold voltage and doping concentration. In addition, the tuning of back gate on the threshold voltage can be predicted.
文摘A 2D analytical electrostatics analysis for the cross-section of a FinFET (or tri-gate MOSFET) is performed to calculate the threshold voltage.The analysis results in a modified gate capacitance with a coefficient H introduced to model the effect of tri-gates and its asymptotic behavior in 2D is that for double-gate MOSFET.The potential profile obtained analytically at the cross-section agrees well with numerical simulations.A compact threshold voltage model for FinFET,comprising quantum mechanical effects,is then proposed.It is concluded that both gate capacitance and threshold voltage will increase with a decreased height,or a decreased gate-oxide thickness of the top gate,which is a trend in FinFET design.
基金supported by the National Natural Science of China(Grant No.61376109)
文摘FinFET technologies are becoming the mainstream process as technology scales down. Based on a 28-nm bulk p- FinFET device, we have investigated the fin width and height dependence of bipolar amplification for heavy-ion-irradiated FinFETs by 3D TCAD numerical simulation. Simulation results show that due to a well bipolar conduction mechanism rather than a channel （fin） conduction path, the transistors with narrower fins exhibit a diminished bipolar amplification effect, while the fin height presents a trivial effect on the bipolar amplification and charge collection. The results also indicate that the single event transient （SET） pulse width can be mitigated about 35% at least by optimizing the ratio of fin width and height, which can provide guidance for radiation-hardened applications in bulk FinFET technology.
基金supported in part by the State Key Development Program for Basic Research of China (Grant No. 2016YFA0200404)
文摘The rapid development of by the device scaling down. encountered difficulties and CMOS technology is driven Classical MOS devices have challenges as scaling down to nanoscale [1], which seriously affects the device performance and limits the further development of CMOS technology. Because of the excellent control over short-channel effects and high current drive capability, novel multi-gate MOS devices have been regarded for years as the most attractive devices to continue the CMOS technology development following ＂Moore＇s law＂ [2]. Among which FinFET, mainly proposed by Hisamoto et al.
基金supported by the National Key Technology Research and Development Program of China(No.2016YFA0202101)the National Natural Science Foundation of China(Nos.61421005,61604005)+1 种基金the National High-Tech R&D Program(863 Program)(No.2015AA016501)The simulation was carried out at National Supercomputer Center in Tianjin,with Tian He-1(A)
文摘We use an electro-thermal coupled Monte Carlo simulation framework to investigate the self-heating effect（SHE） in 14 nm bulk n Fin FETs with ambient temperature（TA） from 220 to 400 K. Based on this method, nonlocal heat generation can be achieved. Contact thermal resistances of Si/Metal and Si/Si O_2 are selected to ensure that the source and drain heat dissipation paths are the first two heat dissipation paths. The results are listed below：（i） not all input power（Q_（input） turns into heat generation in the device region and some is taken out by the thermal non-equilibrium carriers, owing to the serious non-equilibrium transport;（ii） a higher TA leads to a larger ratio of input power turning into heat generation in the device region at the same operating voltages;（iii） SHE can lead to serious degradation in the carrier transport, which will increase when TA increases;（iv） the current degradation can be 8.9% when Vds = 0.7 V, Vgs = 1 V and TA = 400 K;（v） device thermal resistance（Rth） increases with increasing of TA, which is seriously impacted by the non-equilibrium transport. Hence, the impact of TA should be carefully considered when investigating SHE in nanoscale devices.
基金supported by the"National S&T Major Project 02"the Opening Project of Microelectronics Devices & Bulk Si FinFET Integrated Technology,Institute of Microelectronics,Chinese Academy of Sciences(No.2013ZX02303007-001)
文摘A new simulation method and test instrument has been adopted to verify the traditional stress simulation in FinFET. First, a new algorithm named lattice kinetic Monte Carlo （LKMC） is used to simulate the SiGe epitaxy in source/drain regions and the stress distribution is consequently extracted after the LKMC simulation. Systematic comparison between the traditional polyhedron method and the LKMC method is carried out. The results confirm that extracted stress from both methods is consistent, which verifies the validity of traditional polyhedron method for the purpose of simulating stress in FinFET. In the following experiment, p-type FinFETs with SiGe stressors in source/drain regions are fabricated. The nano beam diffraction （NBD） method is employed to characterize the strain in Si fin. The strain value from the NBD test agrees well with the value extracted from traditional polyhedron simulation.
基金supported by the National 02 IC Projectsthe Opening Project of Key Laboratory of Microelectronics Devices & Integrated Technology,Institute of Microelectronics,Chinese Academy of Sciences
文摘Sub-20 nm node bulk FinFET PMOS devices with an all-last high-k/metal gate （HK/MG） process are fabricated and the influence of a series of device parameters on the device scaling is investigated. The high and thin Fin structure with a tapered sidewall shows better performance than the normal Fin structure. The punch through stop layer （PTSL） and source drain extension （SDE） doping profiles are carefully optimized. The device without SDE annealing shows a larger drive current than that with SDE annealing due to better Si crystal regrowth in the amorphous Fin structure after source/drain implantation. The band-edged MG has a better short channel effect immunity, but the lower effective work function （EWF） MG shows a larger driveability. A tradeoff choice for different EWF MGs should be carefully designed for the device＇s scaling.
文摘Nowadays FinFET devices have replaced the MOS devices almost in all complex integrated circuits of electronic gadgets like computer peripherals, tablets, and smartphones in portable electronics. The scaling of FinFET is ongoing and the analog/RF performance is most affected by increased SCEs(short channel effects) in sub22 nm technology nodes. This paper explores the analog/RF performance study and analysis of high performance device-D2(conventional Hf02 spacer SOI FinFET) and device-D3(source/drain extended Hf02 spacer SOI FinFET) over the device-D1(conventional Si3 N4 spacer SOI FinFET) at 20 nm technology node through the 3-D(dimensional) simulation process. The major performance parameters like I(ON current), I(OFF current), gm(transconductance), gd(output conductance), A(intrinsic gain), SS(sub-threshold slope), TGF = g/I(trans-conductance generation factor), VEA(early voltage), GTFP(gain trans-conductance frequency product), TFP(tansconductance frequency product), GFP(gain frequency product), and f(cut-off frequency) are studied for evaluating the analog/RF performance of different flavored SOI FinFET structures. For analog performance evaluation,device-D3 and D2 give better results in terms of gm, ID(drain current) and SS parameters, and for RF performance evaluation device-D1 is better in terms of f, GTFP, TFP, and GFP parameters both at low and high values of V=0.05 V and V=0.7 V respectively.
基金Project supported by the National Fundamental Basic Research Program of China(No.2011CBA00604)
文摘We investigate the influence of gate-source/drain （G-S/D） misalignment on the performance of bulk fin field effect transistors （FinFETs） through the three-dimensional （3D） full band Monte Carlo simulator. Several scat- tering mechanisms, such as acoustic and optical phonon scattering, ionized impurity scattering, impact ionization scattering and surface roughness scattering are considered in our simulator. The influence of G-S/D overlap and underlap on the on-states performance and carrier transport of bulk FinFETs are mainly discussed in our work. Our results show that the on-states currents increase with the increment of G-D/S overlap length and the positions of a potential barrier and average electron energy maximum vary with the G-D/S overlap length. The carrier transport phenomena in bulk FinFETs are due to the effect of scattering and the electric field in the overlap/underlap regime.
