The advanced fin-shaped field-effect transistor(FinFET)technology offers higher integration density and stronger channel control capabilities,however,more complex process effects are also introduced which have signifi...The advanced fin-shaped field-effect transistor(FinFET)technology offers higher integration density and stronger channel control capabilities,however,more complex process effects are also introduced which have significant influence on device performance.To address these issues,we complete a design-technology co-optimization(DTCO)focused on FinFET,including both process-induced effect during gate formation and corresponding digital unit optimization design.The 14 nm Fin-FET complementary metal oxide semiconductor(CMOS)technology is used to illustrate the sensitivity of transistor perfor-mance to process-induced effect,specifically the poly pitch effect(PPE)and cut poly effect(CPE).Predictive technology com-puter aided design(TCAD)simulations have been carried out to evaluate the transistor performance in advance.Based on the results,optimizations in digital unit design is proposed.Fall delay of the digital unit inverter is decreased by 0.7%,and the rise delay is decreased by 2.1%.For multiple selector(MUX2NV),the delay decreases by 4.64%for rise and 3.56%for drop,respec-tively.展开更多
A CMOS FinFET fabricated on bulk silicon substrate is demonstrated.Besides owning a FinFET structure similar to the original FinFET on SOI,the device combines a grooved planar MOSFET in the Si substrate and the fabric...A CMOS FinFET fabricated on bulk silicon substrate is demonstrated.Besides owning a FinFET structure similar to the original FinFET on SOI,the device combines a grooved planar MOSFET in the Si substrate and the fabrication processes are fully compatible with conventional CMOS process,including salicide technology.The CMOS device,inverter,and CMOS ring oscillator of this structure with normal poly silicon and W/TiN gate electrode are fabricated respectively.Driving current and sub threshold characteristics of CMOS FinFET on Si substrate with actual gate length of 110nm are studied.The inverter operates correctly and minimum per stage delay of 201 stage ring oscillator is 146ps at V d=3V.The result indicates the device is a promising candidate for the application of future VLSI circuit.展开更多
An SOI MOSFET with FINFET structure is simulated using a 3 D simulator. I V characteristics and sub threshold characteristics,as well as the short channel effect(SCE) are carefully investigated.SCE can be well c...An SOI MOSFET with FINFET structure is simulated using a 3 D simulator. I V characteristics and sub threshold characteristics,as well as the short channel effect(SCE) are carefully investigated.SCE can be well controlled by reducing fin height.Good performance can be achieved with thin height,so fin height is considered as a key parameter in device design.Simulation results show that FINFETs present performance superior to conventional single gate devices.展开更多
基金supported by the National Natural Science Foundation of China (623B2028).
文摘The advanced fin-shaped field-effect transistor(FinFET)technology offers higher integration density and stronger channel control capabilities,however,more complex process effects are also introduced which have significant influence on device performance.To address these issues,we complete a design-technology co-optimization(DTCO)focused on FinFET,including both process-induced effect during gate formation and corresponding digital unit optimization design.The 14 nm Fin-FET complementary metal oxide semiconductor(CMOS)technology is used to illustrate the sensitivity of transistor perfor-mance to process-induced effect,specifically the poly pitch effect(PPE)and cut poly effect(CPE).Predictive technology com-puter aided design(TCAD)simulations have been carried out to evaluate the transistor performance in advance.Based on the results,optimizations in digital unit design is proposed.Fall delay of the digital unit inverter is decreased by 0.7%,and the rise delay is decreased by 2.1%.For multiple selector(MUX2NV),the delay decreases by 4.64%for rise and 3.56%for drop,respec-tively.
文摘A CMOS FinFET fabricated on bulk silicon substrate is demonstrated.Besides owning a FinFET structure similar to the original FinFET on SOI,the device combines a grooved planar MOSFET in the Si substrate and the fabrication processes are fully compatible with conventional CMOS process,including salicide technology.The CMOS device,inverter,and CMOS ring oscillator of this structure with normal poly silicon and W/TiN gate electrode are fabricated respectively.Driving current and sub threshold characteristics of CMOS FinFET on Si substrate with actual gate length of 110nm are studied.The inverter operates correctly and minimum per stage delay of 201 stage ring oscillator is 146ps at V d=3V.The result indicates the device is a promising candidate for the application of future VLSI circuit.
文摘An SOI MOSFET with FINFET structure is simulated using a 3 D simulator. I V characteristics and sub threshold characteristics,as well as the short channel effect(SCE) are carefully investigated.SCE can be well controlled by reducing fin height.Good performance can be achieved with thin height,so fin height is considered as a key parameter in device design.Simulation results show that FINFETs present performance superior to conventional single gate devices.
