In the process of programmable networks simplifying network management and increasing network flexibility through custom packet behavior,security incidents caused by human logic errors are seriously threatening their ...In the process of programmable networks simplifying network management and increasing network flexibility through custom packet behavior,security incidents caused by human logic errors are seriously threatening their safe operation,robust verificationmethods are required to ensure their correctness.As one of the formalmethods,symbolic execution offers a viable approach for verifying programmable networks by systematically exploring all possible paths within a program.However,its application in this field encounters scalability issues due to path explosion and complex constraint-solving.Therefore,in this paper,we propose NetVerifier,a scalable verification system for programmable networks.Tomitigate the path explosion issue,we developmultiple pruning strategies that strategically eliminate irrelevant execution paths while preserving verification integrity by precisely identifying the execution paths related to the verification purpose.To address the complex constraint-solving problem,we introduce an execution results reuse solution to avoid redundant computation of the same constraints.To apply these solutions intelligently,a matching algorithm is implemented to automatically select appropriate solutions based on the characteristics of the verification requirement.Moreover,Language Aided Verification(LAV),an assertion language,is designed to express verification intentions in a concise form.Experimental results on diverse open-source programs of varying scales demonstrate NetVerifier’s improvement in scalability and effectiveness in identifying potential network errors.In the best scenario,compared with ASSERT-P4,NetVerifier reduced the execution path,verification time,and memory occupation of the verification process by 99.92%,94.76%,and 65.19%,respectively.展开更多
The von Neumann bottleneck in conventional computing architectures presents a significant challenge for data-inten-sive artificial intelligence applications.A promising approach involves designing specialized hardware...The von Neumann bottleneck in conventional computing architectures presents a significant challenge for data-inten-sive artificial intelligence applications.A promising approach involves designing specialized hardware with on-chip parameter tunability,which directly accelerates machine learning functions.This work demonstrates a continuously tunable mixed-kernel function physically realized within a van der Waals heterostructure.We designed and fabricated a MoTe_(2)/MoS_(2)type-Ⅱvertical heterojunction phototransistor,which exhibits a non-monotonic,Gaussian-like optoelectronic response owing to its unique inter-layer charge transfer mechanism.This intrinsic physical behavior directly maps to a mixed-kernel function combining Gaussian and Sigmoid characteristics.Furthermore,the hardware kernel can be continuously modulated by in-situ tuning of external opti-cal stimuli.The mixed-kernel exhibited exceptional performance,achieving precision,accuracy,and area under the curve(AUC)values of 95.8%,96%,and 0.9986,respectively,significantly outperforming conventional kernels.By successfully embedding a complex,adaptable mathematical function into the intrinsic physical properties of a single device,this work pioneers a novel pathway toward next-generation,energy-efficient intelligent systems with hardware-level adaptability.展开更多
The rapid growth of distributed data-centric applications and AI workloads increases demand for low-latency,high-throughput communication,necessitating frequent and flexible updates to network routing configurations.H...The rapid growth of distributed data-centric applications and AI workloads increases demand for low-latency,high-throughput communication,necessitating frequent and flexible updates to network routing configurations.However,maintaining consistent forwarding states during these updates is challenging,particularly when rerouting multiple flows simultaneously.Existing approaches pay little attention to multi-flow update,where improper update sequences across data plane nodes may construct deadlock dependencies.Moreover,these methods typically involve excessive control-data plane interactions,incurring significant resource overhead and performance degradation.This paper presents P4LoF,an efficient loop-free update approach that enables the controller to reroute multiple flows through minimal interactions.P4LoF first utilizes a greedy-based algorithm to generate the shortest update dependency chain for the single-flow update.These chains are then dynamically merged into a dependency graph and resolved as a Shortest Common Super-sequence(SCS)problem to produce the update sequence of multi-flow update.To address deadlock dependencies in multi-flow updates,P4LoF builds a deadlock-fix forwarding model that leverages the flexible packet processing capabilities of the programmable data plane.Experimental results show that P4LoF reduces control-data plane interactions by at least 32.6%with modest overhead,while effectively guaranteeing loop-free consistency.展开更多
Ceramic 4D printing,which integrates dynamic deformation with additive manufacturing,demonstrates significant potential in intelligent manufacturing,on-demand shaping of complex structures,and multifunctional device d...Ceramic 4D printing,which integrates dynamic deformation with additive manufacturing,demonstrates significant potential in intelligent manufacturing,on-demand shaping of complex structures,and multifunctional device development.Its core advantage lies in endowing materials with environmentally responsive dynamic deformation capabilities.However,current technologies still face limitations in responsiveness,reversibility,and mechanical performance.To address these challenges,this study proposes a programmable ceramic precursor system based on synergistic reinforcement of phase-separating hydrogels and shape memory polymers,combined with a nano-ceramic particle enhancement strategy.Using stereolithography 3D printing,high-precision fabrication of complex structures was achieved.By adjusting precursor composition,programming time,and structural thickness,the phase-separation kinetics-driven delayed recovery mechanism was elucidated,enabling precise control over recovery onset time.Furthermore,the thermal response mechanism of the precursor materials is explored,along with their potential for multi-shape transformation in biomedical applications,which is further extended to shape memory polymer systems.By employing a layered printing strategy,the autonomous reversible deformation of ceramic precursors is realized,providing new possibilities for specific applications.展开更多
In order to obtain variable characteristics,the digital filter's type,number of taps and coefficients should be changed constantly such that the desired frequency-domain characteristics can be obtained.This paper ...In order to obtain variable characteristics,the digital filter's type,number of taps and coefficients should be changed constantly such that the desired frequency-domain characteristics can be obtained.This paper proposes a method for self-programmable variable digital filter(VDF) design based on field programmable gate array(FPGA).We implement a digital filter system by using custom embedded micro-processor,programmable finite impulse response(P-FIR) macro module,coefficient-loader,clock manager and analog/digital(A/D) or digital/analog(D/A) controller and other modules.The self-programmable VDF can provide the best solution for realization of digital filter algorithms,which are the low-pass,high-pass,band-pass and band-stop filter algorithms with variable frequency domain characteristics.The design examples with minimum 1 to maximum 32 taps FIR filter,based on Modelsim post-routed simulation and onboard running on XUPV5-LX110T,are provided to demonstrate the effectiveness of the proposed method.展开更多
A high-performance digital servo system built on the platform of a field programmable gate array (FPGA),a fully digitized hardware design scheme of a direct torque control (DTC) and a low speed permanent magnet synchr...A high-performance digital servo system built on the platform of a field programmable gate array (FPGA),a fully digitized hardware design scheme of a direct torque control (DTC) and a low speed permanent magnet synchronous motor (PMSM) is proposed. The DTC strategy of PMSM is described with Verilog hardware description language and is employed on-chip FPGA in accordance with the electronic design automation design methodology. Due to large torque ripples in low speed PMSM,the hysteresis controller in a conventional PMSM DTC was replaced by a fuzzy controller. This FPGA scheme integrates the direct torque controller strategy,the time speed measurement algorithm,the fuzzy regulating technique and the space vector pulse width modulation principle. Experimental results indicate the fuzzy controller can provide a controllable speed at 20 r min-1 and torque at 330 N m with satisfactory dynamic and static performance. Furthermore,the results show that this new control strategy decreases the torque ripple drastically and enhances control performance.展开更多
In this paper, the design of a coarse-fine interpolation Time-to-Digital Converter (TDC) is implemented in an ALTERA’s Cyclone FPGA. The carry-select chain performs as the tapped delay line. The Logic Array Block (LA...In this paper, the design of a coarse-fine interpolation Time-to-Digital Converter (TDC) is implemented in an ALTERA’s Cyclone FPGA. The carry-select chain performs as the tapped delay line. The Logic Array Block (LAB) having a propagation delay of 165 ps in the chain is synthesized as delay cell. Coarse counters triggered by the global clock count the more significant bits of the time data. This clock is also fed through the delay line, and LABs create the copies. The replicas are latched by the tested event signal, and the less significant bits are encoded from the latched binary bits. Single-shot resolution of the TDC can be 60 ps. The worst Differential Nonlinearity (DNL) is about 0.2 Least Significant Bit (LSB, 165 ps in this TDC module), and the Integral Nonlinearity (INL) is 0.6 LSB. In comparison with other architectures using the synchronous global clock to sample the taps, this architecture consumed less electric power and logic cells, and is more stable.展开更多
An intelligent fuzzy logic inference pipeline for the control of a dc-dc buck-boost converter was designed and built using a semi-custom VLSI chip. The fuzzy linguistics describing the switching topologies of the conv...An intelligent fuzzy logic inference pipeline for the control of a dc-dc buck-boost converter was designed and built using a semi-custom VLSI chip. The fuzzy linguistics describing the switching topologies of the converter was mapped into a look-up table that was synthesized into a set of Boolean equations. A VLSI chip–a field programmable gate array (FPGA) was used to implement the Boolean equations. Features include the size of RAM chip independent of number of rules in the knowledge base, on-chip fuzzification and defuzzification, faster response with speeds over giga fuzzy logic inferences per sec (FLIPS), and an inexpensive VLSI chip. The key application areas are: 1) on-chip integrated controllers;and 2) on-chip co-integration for entire system of sensors, circuits, controllers, and detectors for building complete instrument systems.展开更多
Piezoelectric resonators are widely used in frequency reference devices, mass sensors, resonant sensors(such as gyros and accelerometers), etc. Piezoelectric resonators usually work in a special resonant mode. Obtaini...Piezoelectric resonators are widely used in frequency reference devices, mass sensors, resonant sensors(such as gyros and accelerometers), etc. Piezoelectric resonators usually work in a special resonant mode. Obtaining working resonant mode with high quality is key to improve the performance of piezoelectric resonators. In this paper, the resonance characteristics of a rectangular lead zirconium titanate(PZT) piezoelectric resonator are studied. On the basis of the field-programmable gate array(FPGA) embedded system, direct digital synthesizer(DDS) and automatic gain controller(AGC) are used to generate the driving signals with precisely adjustable frequency and amplitude. The driving signals are used to excite the piezoelectric resonator to the working vibration mode. The influence of the connection of driving electrodes and voltage amplitude on the vibration of the resonator is studied. The quality factor and vibration linearity of the resonator are studied with various driving methods mentioned in this paper. The resonator reaches resonant mode at 330 kHz by different driving methods.The relationship between resonant amplitude and driving signal amplitude is linear. The quality factor reaches over 150 by different driving methods. The results provide a theoretical reference for the efficient excitation of the piezoelectric resonator.展开更多
A programmable low-profile array antenna based on nematic liquid crystals(NLCs)is proposed.Each antenna unit comprises a square patch radiating structure and a tunable NLC-based phase shifter capable of achieving a ph...A programmable low-profile array antenna based on nematic liquid crystals(NLCs)is proposed.Each antenna unit comprises a square patch radiating structure and a tunable NLC-based phase shifter capable of achieving a phase shift exceeding 360°with high linearity.First,the above 64 antenna units are periodically arranged into an 8×8 NLC-based antenna array,and the bias voltage of the NLC-based phase shifter loaded on the antenna unit is adjusted through the control of the field-programmable gate array(FPGA)programming sequences.This configuration enables precise phase changes for all 64 channels.Numerical simulation,sample processing,and experimental measurements of the antenna array are conducted to validate the performance of the antenna.The numerical and experimental results demonstrate that the proposed antenna performs well within the frequency range of 19.5-20.5 GHz,with a 3 dB relative bandwidth of 10%and a maximum main lobe gain of 14.1 dBi.A maximum scanning angle of±34°is achieved through the adjustment of the FPGA programming sequence.This NLC-based programmable array antenna shows promising potential for applications in satellite communication.展开更多
We present a fractional-order three-dimensional chaotic system, which can generate four-wing chaotic attractor. Dy- namics of the fractional-order system is investigated by numerical simulations. To rigorously verify ...We present a fractional-order three-dimensional chaotic system, which can generate four-wing chaotic attractor. Dy- namics of the fractional-order system is investigated by numerical simulations. To rigorously verify the chaos properties of this system, the existence of horseshoe in the four-wing attractor is presented. Firstly, a Poincar6 section is selected properly, and a first-return Poincar6 map is established. Then, a one-dimensional tensile horseshoe is discovered, which verifies the chaos existence of the system in mathematical view. Finally, the fractional-order chaotic attractor is imple- mented physically with a field-programmable gate array （FPGA） chip, which is useful in further engineering applications of information encryption and secure communications.展开更多
In order to solve the current high failure rate of warship equipment field programmable gate array( FPGA) software,fault detection is not timely enough and FPGA detection equipment is expensive and so on. After in-dep...In order to solve the current high failure rate of warship equipment field programmable gate array( FPGA) software,fault detection is not timely enough and FPGA detection equipment is expensive and so on. After in-depth research,this paper proposes a warship equipment FPGA software based on Xilinx integrated development environment( ISE) and ModelSim software.Functional simulation and timing simulation to verify the correctness of the logic design of the FPGA,this method is very convenient to view the signal waveform inside the FPGA program to help FPGA test engineers to achieve FPGA fault prediction and diagnosis. This test method has important engineering significance for the upgrading of warship equipment.展开更多
High performance computer is often required by model predictive control(MPC) systems due to the heavy online computation burden.To extend MPC to more application cases with low-cost computation facilities, the impleme...High performance computer is often required by model predictive control(MPC) systems due to the heavy online computation burden.To extend MPC to more application cases with low-cost computation facilities, the implementation of MPC controller on field programmable gate array(FPGA) system is studied.For the dynamic matrix control(DMC) algorithm,the main design idea and the implemental strategy of DMC controller are introduced based on a FPGA’s embedded system.The performance tests show that both the computation efficiency and the accuracy of the proposed controller can be satisfied due to the parallel computing capability of FPGA.展开更多
The drive towards shorter design cycles for analog integrated circuits has given impetus to the development of Field Programmable Analog Arrays(FPAAs),which are the analogue counterparts of Field Programmable Gate Arr...The drive towards shorter design cycles for analog integrated circuits has given impetus to the development of Field Programmable Analog Arrays(FPAAs),which are the analogue counterparts of Field Programmable Gate Arrays(FPGAs).In this paper,we present a new design methodology which using FPAA as a powerful analog front-end processing platform in the smart sensory microsystem.The proposed FPAA contains 16 homogeneous mixed-grained Configurable Analog Blocks(CABs) which house a variety of processing elements especially the proposed fine-grained Core Configurable Amplifiers(CCAs).The high flexible CABs allow the FPAA operating in both continuous-time and discrete-time approaches suitable to support variety of sensors.To reduce the nonideal parasitic effects and save area,the fat-tree interconnection network is adopted in this FPAA.The functionality of this FPAA is demonstrated through embedding of voltage and capacitive sensor signal readout circuits and a configurable band pass filter.The minimal detectable voltage and capacitor achieves 38 uV and 8.3 aF respectively within 100 Hz sensor bandwidth.The power consumption comparison of CCA in three applications shows that the FPAA has high power efficiency.And the simulation results also show that the FPAA has good tolerance with wide PVT variations.展开更多
Persistent flows are defined as network flows that persist over multiple time intervals and continue to exhibit activity over extended periods,which are critical for identifying long-term behaviors and subtle security...Persistent flows are defined as network flows that persist over multiple time intervals and continue to exhibit activity over extended periods,which are critical for identifying long-term behaviors and subtle security threats.Programmable switches provide line-rate packet processing to meet the requirements of high-speed network environments,yet they are fundamentally limited in computational and memory resources.Accurate and memoryefficient persistent flow detection on programmable switches is therefore essential.However,existing approaches often rely on fixed-window sketches or multiple sketches instances,which either suffer from insufficient temporal precision or incur substantial memory overhead,making them ineffective on programmable switches.To address these challenges,we propose SP-Sketch,an innovative sliding-window-based sketch that leverages a probabilistic update mechanism to emulate slot expiration without maintaining multiple sketch instances.This innovative design significantly reduces memory consumption while preserving high detection accuracy across multiple time intervals.We provide rigorous theoretical analyses of the estimation errors,deriving precise error bounds for the proposed method,and validate our approach through comprehensive implementations on both P4 hardware switches(with Intel Tofino ASIC)and software switches(i.e.,BMv2).Experimental evaluations using real-world traffic traces demonstrate that SP-Sketch outperforms traditional methods,improving accuracy by up to 20%over baseline sliding window approaches and enhancing recall by 5%compared to non-sliding alternatives.Furthermore,SP-Sketch achieves a significant reduction in memory utilization,reducing memory consumption by up to 65%compared to traditional methods,while maintaining a robust capability to accurately track persistent flow behavior over extended time periods.展开更多
Kirigami,through introducing cuts into a thin sheet,can greatly improve the stretchability of structures and also generate complex patterns,showing potentials in various applications.Interestingly,even with the same c...Kirigami,through introducing cuts into a thin sheet,can greatly improve the stretchability of structures and also generate complex patterns,showing potentials in various applications.Interestingly,even with the same cutting pattern,the mechanical response of kirigami metamaterials can exhibit significant differences depending on the cutting angles in respect to the loading direction.In this work,we investigate the structural deformation of kirigami metamaterials with square domains and varied cutting angles of 0°and 45°.We further introduce a second level of cutting on the basis of the first cutting pattern.By combining experiments and finite element simulations,it is found that,compared to the commonly used 0°cuts,the two-level kirigami metamaterials with 45°cuts exhibit a unique alternating arrangement phenomenon of expanded/unexpanded states in the loading process,which also results in distinct stress–strain response.Through tuning the cutting patterns of metamaterials with 45°cuts,precise control of the rotation of the kirigami unit is realized,leading to kirigami metamaterials with encryption properties.The current work demonstrates the programmability of structural deformation in hierarchical kirigami metamaterials through controlling the local cutting modes.展开更多
This article presents an integrated current mode configurable analog block(CAB)system for field-programmable analog array(FPAA).The proposed architecture is based on the complementary metal-oxide semiconductor(CMOS)tr...This article presents an integrated current mode configurable analog block(CAB)system for field-programmable analog array(FPAA).The proposed architecture is based on the complementary metal-oxide semiconductor(CMOS)transistor level design where MOSFET transistors operating in the saturation region are adopted.The proposed CAB architecture is designed to implement six of thewidely used current mode operations in analog processing systems:addition,subtraction,integration,multiplication,division,and pass operation.The functionality of the proposed CAB is demonstrated through these six operations,where each operation is chosen based on the user’s selection in the CAB interface system.The architecture of the CAB system proposes an optimized way of designing and integrating only three functional cells with the interface circuitry to achieve the six operations.Furthermore,optimized programming and digital tuning circuitry are implemented in the architecture to control and interface with the functional cells.Moreover,these designed programming and tuning circuitries play an essential role in optimizing the performance of the proposed design.Simulation of the proposed CMOS Transistor Based CAB system is carried out using Tanner EDA Tools in 0.35μm standard CMOS technology.The design uses a±1.5 V power supply and results in maximum 3 dB bandwidth of 34.9 MHz and an approximate size of 0.0537 mm2.This demonstrates the advantages of the design over the current state-of-the-art designs presented for comparison in this article.Consequently,the proposed design has a clear aspect of simplicity,low power consumption,and high bandwidth operation,which makes it a suitable candidate for mobile telecommunications applications.展开更多
Shenzhen,a major city in southern China,has experienced rapid advancements in Unmanned Aerial Vehicle(UAV)technology,resulting in extensive logistics networks with thousands of daily flights.However,frequent disruptio...Shenzhen,a major city in southern China,has experienced rapid advancements in Unmanned Aerial Vehicle(UAV)technology,resulting in extensive logistics networks with thousands of daily flights.However,frequent disruptions due to its subtropical monsoon climate,including typhoons and gusty winds,present ongoing challenges.Despite the growing focus on operational costs and third-party risks,research on low-altitude urban wind fields remains scarce.This study addresses this gap by integrating wind field analysis into UAV path planning,introducing key innovations to the classical model.First,UAV wind resistance and turbulence constraints are analyzed,mapping high-wind-speed and turbulence-prone zones in the airspace.Second,wind dynamics are incorporated into path planning by considering airspeed and groundspeed variation,optimizing waypoint selection and flight speed adjustments to improve overall energy efficiency.Additionally,a wind-aware Theta*algorithm is proposed,leveraging wind vectors to expedite search process,while Computational Fluid Dynamics(CFD)techniques are employed to calculate wind fields.A case study of Shenzhen,examining wind patterns over the past decade,demonstrates a 6.23%improvement in groundspeed and a 7.69%reduction in energy consumption compared to wind-agnostic models.This framework advances UAV logistics by enhancing route safety and energy efficiency,contributing to more cost-effective operations.展开更多
Chiral metamaterials are manmade structures with extraordinary mechanical properties derived from their special geometric design instead of chemical composition.To make the mechanical deformation programmable,the non-...Chiral metamaterials are manmade structures with extraordinary mechanical properties derived from their special geometric design instead of chemical composition.To make the mechanical deformation programmable,the non-uniform rational B-spline(NURBS)curves are taken to replace the traditional ligament boundaries of the chiral structure.The Neural networks are innovatively inserted into the calculation of mechanical properties of the chiral structure instead of finite element methods to improve computational efficiency.For the problem of finding structure configuration with specified mechanical properties,such as Young’s modulus,Poisson’s ratio or deformation,an inverse design method using the Neural network-based proxy model is proposed to build the relationship between mechanical properties and geometric configuration.To satisfy some more complex deformation requirements,a non-homogeneous inverse design method is proposed and verified through simulation and experiments.Numerical and test results reveal the high computational efficiency and accuracy of the proposed method in the design of chiral metamaterials.展开更多
基金supported by the National Key Research and Development Program of China under Grant 2023YFB2903902in part by the Science and Technology Innovation Leading Talents Subsidy Project of Central Plains under Grant 244200510038.
文摘In the process of programmable networks simplifying network management and increasing network flexibility through custom packet behavior,security incidents caused by human logic errors are seriously threatening their safe operation,robust verificationmethods are required to ensure their correctness.As one of the formalmethods,symbolic execution offers a viable approach for verifying programmable networks by systematically exploring all possible paths within a program.However,its application in this field encounters scalability issues due to path explosion and complex constraint-solving.Therefore,in this paper,we propose NetVerifier,a scalable verification system for programmable networks.Tomitigate the path explosion issue,we developmultiple pruning strategies that strategically eliminate irrelevant execution paths while preserving verification integrity by precisely identifying the execution paths related to the verification purpose.To address the complex constraint-solving problem,we introduce an execution results reuse solution to avoid redundant computation of the same constraints.To apply these solutions intelligently,a matching algorithm is implemented to automatically select appropriate solutions based on the characteristics of the verification requirement.Moreover,Language Aided Verification(LAV),an assertion language,is designed to express verification intentions in a concise form.Experimental results on diverse open-source programs of varying scales demonstrate NetVerifier’s improvement in scalability and effectiveness in identifying potential network errors.In the best scenario,compared with ASSERT-P4,NetVerifier reduced the execution path,verification time,and memory occupation of the verification process by 99.92%,94.76%,and 65.19%,respectively.
基金co-supported by the National Natural Science Foundation of China(Grant Nos.62222404,T2450054,62304084,62504087,62361136587 and 92248304)the National Key Research and Development Plan of China(Grant No.2021YFB3601200)+3 种基金the Major Program of Hubei Province(Grant No.2023BAA009)the Research Grants Council of Hong Kong Postdoctoral Fellowship Scheme(Grant No.PDFS2223-4S06)the China Postdoctoral Science Foundation funded project(Grant No.2025M770530)the Postdoctoral Fellowship Program of CPSF(Grant No.GZB20250136).
文摘The von Neumann bottleneck in conventional computing architectures presents a significant challenge for data-inten-sive artificial intelligence applications.A promising approach involves designing specialized hardware with on-chip parameter tunability,which directly accelerates machine learning functions.This work demonstrates a continuously tunable mixed-kernel function physically realized within a van der Waals heterostructure.We designed and fabricated a MoTe_(2)/MoS_(2)type-Ⅱvertical heterojunction phototransistor,which exhibits a non-monotonic,Gaussian-like optoelectronic response owing to its unique inter-layer charge transfer mechanism.This intrinsic physical behavior directly maps to a mixed-kernel function combining Gaussian and Sigmoid characteristics.Furthermore,the hardware kernel can be continuously modulated by in-situ tuning of external opti-cal stimuli.The mixed-kernel exhibited exceptional performance,achieving precision,accuracy,and area under the curve(AUC)values of 95.8%,96%,and 0.9986,respectively,significantly outperforming conventional kernels.By successfully embedding a complex,adaptable mathematical function into the intrinsic physical properties of a single device,this work pioneers a novel pathway toward next-generation,energy-efficient intelligent systems with hardware-level adaptability.
基金supported by the National Key Research and Development Program of China under Grant 2022YFB2901501in part by the Science and Technology Innovation leading Talents Subsidy Project of Central Plains under Grant 244200510038.
文摘The rapid growth of distributed data-centric applications and AI workloads increases demand for low-latency,high-throughput communication,necessitating frequent and flexible updates to network routing configurations.However,maintaining consistent forwarding states during these updates is challenging,particularly when rerouting multiple flows simultaneously.Existing approaches pay little attention to multi-flow update,where improper update sequences across data plane nodes may construct deadlock dependencies.Moreover,these methods typically involve excessive control-data plane interactions,incurring significant resource overhead and performance degradation.This paper presents P4LoF,an efficient loop-free update approach that enables the controller to reroute multiple flows through minimal interactions.P4LoF first utilizes a greedy-based algorithm to generate the shortest update dependency chain for the single-flow update.These chains are then dynamically merged into a dependency graph and resolved as a Shortest Common Super-sequence(SCS)problem to produce the update sequence of multi-flow update.To address deadlock dependencies in multi-flow updates,P4LoF builds a deadlock-fix forwarding model that leverages the flexible packet processing capabilities of the programmable data plane.Experimental results show that P4LoF reduces control-data plane interactions by at least 32.6%with modest overhead,while effectively guaranteeing loop-free consistency.
基金supported by the National Natural Science Foundation of China(Grant Nos.52025053 and 52235006)the Jilin Provincial Scientific and Technological Development Program(20220204119YY)the Natural Science Foundation of Shandong Province(ZR2023ME154)。
文摘Ceramic 4D printing,which integrates dynamic deformation with additive manufacturing,demonstrates significant potential in intelligent manufacturing,on-demand shaping of complex structures,and multifunctional device development.Its core advantage lies in endowing materials with environmentally responsive dynamic deformation capabilities.However,current technologies still face limitations in responsiveness,reversibility,and mechanical performance.To address these challenges,this study proposes a programmable ceramic precursor system based on synergistic reinforcement of phase-separating hydrogels and shape memory polymers,combined with a nano-ceramic particle enhancement strategy.Using stereolithography 3D printing,high-precision fabrication of complex structures was achieved.By adjusting precursor composition,programming time,and structural thickness,the phase-separation kinetics-driven delayed recovery mechanism was elucidated,enabling precise control over recovery onset time.Furthermore,the thermal response mechanism of the precursor materials is explored,along with their potential for multi-shape transformation in biomedical applications,which is further extended to shape memory polymer systems.By employing a layered printing strategy,the autonomous reversible deformation of ceramic precursors is realized,providing new possibilities for specific applications.
基金Science &Technology Plan Foundation of Hunan Province,China(No.2010F3102)Science Research Foundation of Hunan Province,China(No.08C392)
文摘In order to obtain variable characteristics,the digital filter's type,number of taps and coefficients should be changed constantly such that the desired frequency-domain characteristics can be obtained.This paper proposes a method for self-programmable variable digital filter(VDF) design based on field programmable gate array(FPGA).We implement a digital filter system by using custom embedded micro-processor,programmable finite impulse response(P-FIR) macro module,coefficient-loader,clock manager and analog/digital(A/D) or digital/analog(D/A) controller and other modules.The self-programmable VDF can provide the best solution for realization of digital filter algorithms,which are the low-pass,high-pass,band-pass and band-stop filter algorithms with variable frequency domain characteristics.The design examples with minimum 1 to maximum 32 taps FIR filter,based on Modelsim post-routed simulation and onboard running on XUPV5-LX110T,are provided to demonstrate the effectiveness of the proposed method.
基金the Natural Science Foundation of Hubei Province (No.2005ABA301)
文摘A high-performance digital servo system built on the platform of a field programmable gate array (FPGA),a fully digitized hardware design scheme of a direct torque control (DTC) and a low speed permanent magnet synchronous motor (PMSM) is proposed. The DTC strategy of PMSM is described with Verilog hardware description language and is employed on-chip FPGA in accordance with the electronic design automation design methodology. Due to large torque ripples in low speed PMSM,the hysteresis controller in a conventional PMSM DTC was replaced by a fuzzy controller. This FPGA scheme integrates the direct torque controller strategy,the time speed measurement algorithm,the fuzzy regulating technique and the space vector pulse width modulation principle. Experimental results indicate the fuzzy controller can provide a controllable speed at 20 r min-1 and torque at 330 N m with satisfactory dynamic and static performance. Furthermore,the results show that this new control strategy decreases the torque ripple drastically and enhances control performance.
基金Supported by National Natural Science Foundation of China (No. 10405023)Knowledge Innovation Program of The Chinese Academy of Sciences (KJCX2-YW-N27)
文摘In this paper, the design of a coarse-fine interpolation Time-to-Digital Converter (TDC) is implemented in an ALTERA’s Cyclone FPGA. The carry-select chain performs as the tapped delay line. The Logic Array Block (LAB) having a propagation delay of 165 ps in the chain is synthesized as delay cell. Coarse counters triggered by the global clock count the more significant bits of the time data. This clock is also fed through the delay line, and LABs create the copies. The replicas are latched by the tested event signal, and the less significant bits are encoded from the latched binary bits. Single-shot resolution of the TDC can be 60 ps. The worst Differential Nonlinearity (DNL) is about 0.2 Least Significant Bit (LSB, 165 ps in this TDC module), and the Integral Nonlinearity (INL) is 0.6 LSB. In comparison with other architectures using the synchronous global clock to sample the taps, this architecture consumed less electric power and logic cells, and is more stable.
文摘An intelligent fuzzy logic inference pipeline for the control of a dc-dc buck-boost converter was designed and built using a semi-custom VLSI chip. The fuzzy linguistics describing the switching topologies of the converter was mapped into a look-up table that was synthesized into a set of Boolean equations. A VLSI chip–a field programmable gate array (FPGA) was used to implement the Boolean equations. Features include the size of RAM chip independent of number of rules in the knowledge base, on-chip fuzzification and defuzzification, faster response with speeds over giga fuzzy logic inferences per sec (FLIPS), and an inexpensive VLSI chip. The key application areas are: 1) on-chip integrated controllers;and 2) on-chip co-integration for entire system of sensors, circuits, controllers, and detectors for building complete instrument systems.
文摘Piezoelectric resonators are widely used in frequency reference devices, mass sensors, resonant sensors(such as gyros and accelerometers), etc. Piezoelectric resonators usually work in a special resonant mode. Obtaining working resonant mode with high quality is key to improve the performance of piezoelectric resonators. In this paper, the resonance characteristics of a rectangular lead zirconium titanate(PZT) piezoelectric resonator are studied. On the basis of the field-programmable gate array(FPGA) embedded system, direct digital synthesizer(DDS) and automatic gain controller(AGC) are used to generate the driving signals with precisely adjustable frequency and amplitude. The driving signals are used to excite the piezoelectric resonator to the working vibration mode. The influence of the connection of driving electrodes and voltage amplitude on the vibration of the resonator is studied. The quality factor and vibration linearity of the resonator are studied with various driving methods mentioned in this paper. The resonator reaches resonant mode at 330 kHz by different driving methods.The relationship between resonant amplitude and driving signal amplitude is linear. The quality factor reaches over 150 by different driving methods. The results provide a theoretical reference for the efficient excitation of the piezoelectric resonator.
基金The National Natural Science Foundation of China(No.62401168,62401139,62401170)China Postdoctoral Science Foundation(No.2023MD744197)+2 种基金Postdoctoral Fellowship Program of CPSF(No.GZC20230631)Project for Enhancing Young and Middle-aged Teacher’s Research Basis Ability in Colleges of Guangxi(No.2023KY0218)Guangxi Key Laboratory Foundation of Optoelectronic Information Processing(No.GD23102)。
文摘A programmable low-profile array antenna based on nematic liquid crystals(NLCs)is proposed.Each antenna unit comprises a square patch radiating structure and a tunable NLC-based phase shifter capable of achieving a phase shift exceeding 360°with high linearity.First,the above 64 antenna units are periodically arranged into an 8×8 NLC-based antenna array,and the bias voltage of the NLC-based phase shifter loaded on the antenna unit is adjusted through the control of the field-programmable gate array(FPGA)programming sequences.This configuration enables precise phase changes for all 64 channels.Numerical simulation,sample processing,and experimental measurements of the antenna array are conducted to validate the performance of the antenna.The numerical and experimental results demonstrate that the proposed antenna performs well within the frequency range of 19.5-20.5 GHz,with a 3 dB relative bandwidth of 10%and a maximum main lobe gain of 14.1 dBi.A maximum scanning angle of±34°is achieved through the adjustment of the FPGA programming sequence.This NLC-based programmable array antenna shows promising potential for applications in satellite communication.
基金Project supported by the National Natural Science Foundation of China(Grant Nos.61502340 and 61374169)the Application Base and Frontier Technology Research Project of Tianjin,China(Grant No.15JCYBJC51800)the South African National Research Foundation Incentive Grants(Grant No.81705)
文摘We present a fractional-order three-dimensional chaotic system, which can generate four-wing chaotic attractor. Dy- namics of the fractional-order system is investigated by numerical simulations. To rigorously verify the chaos properties of this system, the existence of horseshoe in the four-wing attractor is presented. Firstly, a Poincar6 section is selected properly, and a first-return Poincar6 map is established. Then, a one-dimensional tensile horseshoe is discovered, which verifies the chaos existence of the system in mathematical view. Finally, the fractional-order chaotic attractor is imple- mented physically with a field-programmable gate array （FPGA） chip, which is useful in further engineering applications of information encryption and secure communications.
文摘In order to solve the current high failure rate of warship equipment field programmable gate array( FPGA) software,fault detection is not timely enough and FPGA detection equipment is expensive and so on. After in-depth research,this paper proposes a warship equipment FPGA software based on Xilinx integrated development environment( ISE) and ModelSim software.Functional simulation and timing simulation to verify the correctness of the logic design of the FPGA,this method is very convenient to view the signal waveform inside the FPGA program to help FPGA test engineers to achieve FPGA fault prediction and diagnosis. This test method has important engineering significance for the upgrading of warship equipment.
基金the National Science Foundation of China(Nos.60934007 and 61074060)the Postdoctoral Science Foundation of China(No.20090460627)+2 种基金the Postdoctoral Scientific Program of Shanghai (No.10R21414600)the Specialized Research Fund for the Doctoral Program of Higher Education (No.20070248004)the China Postdoctoral Science Foundation Special Support(No.201003272)
文摘High performance computer is often required by model predictive control(MPC) systems due to the heavy online computation burden.To extend MPC to more application cases with low-cost computation facilities, the implementation of MPC controller on field programmable gate array(FPGA) system is studied.For the dynamic matrix control(DMC) algorithm,the main design idea and the implemental strategy of DMC controller are introduced based on a FPGA’s embedded system.The performance tests show that both the computation efficiency and the accuracy of the proposed controller can be satisfied due to the parallel computing capability of FPGA.
基金Supported by the CAS/SAFEA International Partnership Program for Creative Research Teams,National High Technology Research and Develop Program of China(2012AA012301)National Science and Technology Major Project of China(2013ZX03006004)
文摘The drive towards shorter design cycles for analog integrated circuits has given impetus to the development of Field Programmable Analog Arrays(FPAAs),which are the analogue counterparts of Field Programmable Gate Arrays(FPGAs).In this paper,we present a new design methodology which using FPAA as a powerful analog front-end processing platform in the smart sensory microsystem.The proposed FPAA contains 16 homogeneous mixed-grained Configurable Analog Blocks(CABs) which house a variety of processing elements especially the proposed fine-grained Core Configurable Amplifiers(CCAs).The high flexible CABs allow the FPAA operating in both continuous-time and discrete-time approaches suitable to support variety of sensors.To reduce the nonideal parasitic effects and save area,the fat-tree interconnection network is adopted in this FPAA.The functionality of this FPAA is demonstrated through embedding of voltage and capacitive sensor signal readout circuits and a configurable band pass filter.The minimal detectable voltage and capacitor achieves 38 uV and 8.3 aF respectively within 100 Hz sensor bandwidth.The power consumption comparison of CCA in three applications shows that the FPAA has high power efficiency.And the simulation results also show that the FPAA has good tolerance with wide PVT variations.
基金supported by the National Undergraduate Innovation and Entrepreneurship Training Program of China(Project No.202510559076)at Jinan University,a nationwide initiative administered by the Ministry of Educationthe National Natural Science Foundation of China(NSFC)under Grant No.62172189.
文摘Persistent flows are defined as network flows that persist over multiple time intervals and continue to exhibit activity over extended periods,which are critical for identifying long-term behaviors and subtle security threats.Programmable switches provide line-rate packet processing to meet the requirements of high-speed network environments,yet they are fundamentally limited in computational and memory resources.Accurate and memoryefficient persistent flow detection on programmable switches is therefore essential.However,existing approaches often rely on fixed-window sketches or multiple sketches instances,which either suffer from insufficient temporal precision or incur substantial memory overhead,making them ineffective on programmable switches.To address these challenges,we propose SP-Sketch,an innovative sliding-window-based sketch that leverages a probabilistic update mechanism to emulate slot expiration without maintaining multiple sketch instances.This innovative design significantly reduces memory consumption while preserving high detection accuracy across multiple time intervals.We provide rigorous theoretical analyses of the estimation errors,deriving precise error bounds for the proposed method,and validate our approach through comprehensive implementations on both P4 hardware switches(with Intel Tofino ASIC)and software switches(i.e.,BMv2).Experimental evaluations using real-world traffic traces demonstrate that SP-Sketch outperforms traditional methods,improving accuracy by up to 20%over baseline sliding window approaches and enhancing recall by 5%compared to non-sliding alternatives.Furthermore,SP-Sketch achieves a significant reduction in memory utilization,reducing memory consumption by up to 65%compared to traditional methods,while maintaining a robust capability to accurately track persistent flow behavior over extended time periods.
基金supported by the National Natural Science Foundation of China(Grant Nos.12102392 and 12272341)the Zhejiang Provincial Natural Science Foundation of China(Grant No.LQ21A020008).
文摘Kirigami,through introducing cuts into a thin sheet,can greatly improve the stretchability of structures and also generate complex patterns,showing potentials in various applications.Interestingly,even with the same cutting pattern,the mechanical response of kirigami metamaterials can exhibit significant differences depending on the cutting angles in respect to the loading direction.In this work,we investigate the structural deformation of kirigami metamaterials with square domains and varied cutting angles of 0°and 45°.We further introduce a second level of cutting on the basis of the first cutting pattern.By combining experiments and finite element simulations,it is found that,compared to the commonly used 0°cuts,the two-level kirigami metamaterials with 45°cuts exhibit a unique alternating arrangement phenomenon of expanded/unexpanded states in the loading process,which also results in distinct stress–strain response.Through tuning the cutting patterns of metamaterials with 45°cuts,precise control of the rotation of the kirigami unit is realized,leading to kirigami metamaterials with encryption properties.The current work demonstrates the programmability of structural deformation in hierarchical kirigami metamaterials through controlling the local cutting modes.
基金This work was supported in part by the Geran Galakan Penyelidik Muda Grant(GGPM),Universiti Kebangsaan Malaysia,Selangor,Malaysia under grant GGPM-2021-055.
文摘This article presents an integrated current mode configurable analog block(CAB)system for field-programmable analog array(FPAA).The proposed architecture is based on the complementary metal-oxide semiconductor(CMOS)transistor level design where MOSFET transistors operating in the saturation region are adopted.The proposed CAB architecture is designed to implement six of thewidely used current mode operations in analog processing systems:addition,subtraction,integration,multiplication,division,and pass operation.The functionality of the proposed CAB is demonstrated through these six operations,where each operation is chosen based on the user’s selection in the CAB interface system.The architecture of the CAB system proposes an optimized way of designing and integrating only three functional cells with the interface circuitry to achieve the six operations.Furthermore,optimized programming and digital tuning circuitry are implemented in the architecture to control and interface with the functional cells.Moreover,these designed programming and tuning circuitries play an essential role in optimizing the performance of the proposed design.Simulation of the proposed CMOS Transistor Based CAB system is carried out using Tanner EDA Tools in 0.35μm standard CMOS technology.The design uses a±1.5 V power supply and results in maximum 3 dB bandwidth of 34.9 MHz and an approximate size of 0.0537 mm2.This demonstrates the advantages of the design over the current state-of-the-art designs presented for comparison in this article.Consequently,the proposed design has a clear aspect of simplicity,low power consumption,and high bandwidth operation,which makes it a suitable candidate for mobile telecommunications applications.
基金supported by the National Natural Science Foundation of China(No.U2433214)。
文摘Shenzhen,a major city in southern China,has experienced rapid advancements in Unmanned Aerial Vehicle(UAV)technology,resulting in extensive logistics networks with thousands of daily flights.However,frequent disruptions due to its subtropical monsoon climate,including typhoons and gusty winds,present ongoing challenges.Despite the growing focus on operational costs and third-party risks,research on low-altitude urban wind fields remains scarce.This study addresses this gap by integrating wind field analysis into UAV path planning,introducing key innovations to the classical model.First,UAV wind resistance and turbulence constraints are analyzed,mapping high-wind-speed and turbulence-prone zones in the airspace.Second,wind dynamics are incorporated into path planning by considering airspeed and groundspeed variation,optimizing waypoint selection and flight speed adjustments to improve overall energy efficiency.Additionally,a wind-aware Theta*algorithm is proposed,leveraging wind vectors to expedite search process,while Computational Fluid Dynamics(CFD)techniques are employed to calculate wind fields.A case study of Shenzhen,examining wind patterns over the past decade,demonstrates a 6.23%improvement in groundspeed and a 7.69%reduction in energy consumption compared to wind-agnostic models.This framework advances UAV logistics by enhancing route safety and energy efficiency,contributing to more cost-effective operations.
基金supported by the National Natural Science Foundation of China(grant numbers 11972287 and 12072266)the State Key Laboratory of Structural Analysis,Optimization and CAE Software for Industrial Equipment(GZ23106)+1 种基金the National Key Laboratory of Aircraft Configuration Design(No.2023-JCJQ-LB-070)the Fundamental Research Funds for the Central Universities.
文摘Chiral metamaterials are manmade structures with extraordinary mechanical properties derived from their special geometric design instead of chemical composition.To make the mechanical deformation programmable,the non-uniform rational B-spline(NURBS)curves are taken to replace the traditional ligament boundaries of the chiral structure.The Neural networks are innovatively inserted into the calculation of mechanical properties of the chiral structure instead of finite element methods to improve computational efficiency.For the problem of finding structure configuration with specified mechanical properties,such as Young’s modulus,Poisson’s ratio or deformation,an inverse design method using the Neural network-based proxy model is proposed to build the relationship between mechanical properties and geometric configuration.To satisfy some more complex deformation requirements,a non-homogeneous inverse design method is proposed and verified through simulation and experiments.Numerical and test results reveal the high computational efficiency and accuracy of the proposed method in the design of chiral metamaterials.
