In order to obtain variable characteristics,the digital filter's type,number of taps and coefficients should be changed constantly such that the desired frequency-domain characteristics can be obtained.This paper ...In order to obtain variable characteristics,the digital filter's type,number of taps and coefficients should be changed constantly such that the desired frequency-domain characteristics can be obtained.This paper proposes a method for self-programmable variable digital filter(VDF) design based on field programmable gate array(FPGA).We implement a digital filter system by using custom embedded micro-processor,programmable finite impulse response(P-FIR) macro module,coefficient-loader,clock manager and analog/digital(A/D) or digital/analog(D/A) controller and other modules.The self-programmable VDF can provide the best solution for realization of digital filter algorithms,which are the low-pass,high-pass,band-pass and band-stop filter algorithms with variable frequency domain characteristics.The design examples with minimum 1 to maximum 32 taps FIR filter,based on Modelsim post-routed simulation and onboard running on XUPV5-LX110T,are provided to demonstrate the effectiveness of the proposed method.展开更多
An intelligent fuzzy logic inference pipeline for the control of a dc-dc buck-boost converter was designed and built using a semi-custom VLSI chip. The fuzzy linguistics describing the switching topologies of the conv...An intelligent fuzzy logic inference pipeline for the control of a dc-dc buck-boost converter was designed and built using a semi-custom VLSI chip. The fuzzy linguistics describing the switching topologies of the converter was mapped into a look-up table that was synthesized into a set of Boolean equations. A VLSI chip–a field programmable gate array (FPGA) was used to implement the Boolean equations. Features include the size of RAM chip independent of number of rules in the knowledge base, on-chip fuzzification and defuzzification, faster response with speeds over giga fuzzy logic inferences per sec (FLIPS), and an inexpensive VLSI chip. The key application areas are: 1) on-chip integrated controllers;and 2) on-chip co-integration for entire system of sensors, circuits, controllers, and detectors for building complete instrument systems.展开更多
A novel test approach for interconnect resources(IRs)in field programmable gate arrays(FPGA)has been proposed.In the test approach,SBs(switch boxes)of IRs in FPGA has been utilized to test IRs.Furthermore,configurable...A novel test approach for interconnect resources(IRs)in field programmable gate arrays(FPGA)has been proposed.In the test approach,SBs(switch boxes)of IRs in FPGA has been utilized to test IRs.Furthermore,configurable logic blocks(CLBs)in FPGA have also been employed to enhance driving capability and the position of fault IR can be determined by monitoring the IRs associated SBs.As a result,IRs can be scanned maximally with minimum configuration patterns.In the experiment,an in-house developed FPGA test system based on system-on-chip(SoC)hardware/software verification technology has been applied to test XC4000E family of Xilinx.The experiment results revealed that the IRs in FPGA can be tested by 6 test patterns.展开更多
In this paper, the design of a coarse-fine interpolation Time-to-Digital Converter (TDC) is implemented in an ALTERA’s Cyclone FPGA. The carry-select chain performs as the tapped delay line. The Logic Array Block (LA...In this paper, the design of a coarse-fine interpolation Time-to-Digital Converter (TDC) is implemented in an ALTERA’s Cyclone FPGA. The carry-select chain performs as the tapped delay line. The Logic Array Block (LAB) having a propagation delay of 165 ps in the chain is synthesized as delay cell. Coarse counters triggered by the global clock count the more significant bits of the time data. This clock is also fed through the delay line, and LABs create the copies. The replicas are latched by the tested event signal, and the less significant bits are encoded from the latched binary bits. Single-shot resolution of the TDC can be 60 ps. The worst Differential Nonlinearity (DNL) is about 0.2 Least Significant Bit (LSB, 165 ps in this TDC module), and the Integral Nonlinearity (INL) is 0.6 LSB. In comparison with other architectures using the synchronous global clock to sample the taps, this architecture consumed less electric power and logic cells, and is more stable.展开更多
Piezoelectric resonators are widely used in frequency reference devices, mass sensors, resonant sensors(such as gyros and accelerometers), etc. Piezoelectric resonators usually work in a special resonant mode. Obtaini...Piezoelectric resonators are widely used in frequency reference devices, mass sensors, resonant sensors(such as gyros and accelerometers), etc. Piezoelectric resonators usually work in a special resonant mode. Obtaining working resonant mode with high quality is key to improve the performance of piezoelectric resonators. In this paper, the resonance characteristics of a rectangular lead zirconium titanate(PZT) piezoelectric resonator are studied. On the basis of the field-programmable gate array(FPGA) embedded system, direct digital synthesizer(DDS) and automatic gain controller(AGC) are used to generate the driving signals with precisely adjustable frequency and amplitude. The driving signals are used to excite the piezoelectric resonator to the working vibration mode. The influence of the connection of driving electrodes and voltage amplitude on the vibration of the resonator is studied. The quality factor and vibration linearity of the resonator are studied with various driving methods mentioned in this paper. The resonator reaches resonant mode at 330 kHz by different driving methods.The relationship between resonant amplitude and driving signal amplitude is linear. The quality factor reaches over 150 by different driving methods. The results provide a theoretical reference for the efficient excitation of the piezoelectric resonator.展开更多
In order to solve the current high failure rate of warship equipment field programmable gate array( FPGA) software,fault detection is not timely enough and FPGA detection equipment is expensive and so on. After in-dep...In order to solve the current high failure rate of warship equipment field programmable gate array( FPGA) software,fault detection is not timely enough and FPGA detection equipment is expensive and so on. After in-depth research,this paper proposes a warship equipment FPGA software based on Xilinx integrated development environment( ISE) and ModelSim software.Functional simulation and timing simulation to verify the correctness of the logic design of the FPGA,this method is very convenient to view the signal waveform inside the FPGA program to help FPGA test engineers to achieve FPGA fault prediction and diagnosis. This test method has important engineering significance for the upgrading of warship equipment.展开更多
High performance computer is often required by model predictive control(MPC) systems due to the heavy online computation burden.To extend MPC to more application cases with low-cost computation facilities, the impleme...High performance computer is often required by model predictive control(MPC) systems due to the heavy online computation burden.To extend MPC to more application cases with low-cost computation facilities, the implementation of MPC controller on field programmable gate array(FPGA) system is studied.For the dynamic matrix control(DMC) algorithm,the main design idea and the implemental strategy of DMC controller are introduced based on a FPGA’s embedded system.The performance tests show that both the computation efficiency and the accuracy of the proposed controller can be satisfied due to the parallel computing capability of FPGA.展开更多
大规模双馈风电场作为实现我国“双碳”目标的陆上风电主力,其高比例电力电子设备的接入对电力系统电磁暂态高精度仿真技术提出日益严苛的要求,面向上百台发电单元的双馈场站全拓扑精细化微秒级仿真研究仍相对空白。基于现场可编程门阵...大规模双馈风电场作为实现我国“双碳”目标的陆上风电主力,其高比例电力电子设备的接入对电力系统电磁暂态高精度仿真技术提出日益严苛的要求,面向上百台发电单元的双馈场站全拓扑精细化微秒级仿真研究仍相对空白。基于现场可编程门阵列(field programmable gate array,FPGA)微秒级小步长并行仿真能力,提出一种面向双馈风电场站的发电单元FPGA并行仿真方法。首先,进行双馈感应电机微秒级高并行度离散化建模与换流器受控源建模;接着,对节点导纳矩阵分块降维以实现发电单元内部分网并行,并从整体电路解算层面提出单元级并行仿真框架;最后,考虑实时数字仿真器(real time digital simulator,RTDS)与FPGA仿真平台特点,分配发电单元的微秒级小步长仿真任务并搭建联合仿真硬件框架;通过对比RTDS标准模型与RTDS+FPGA联合仿真模型,验证所提并行仿真方法的准确性。展开更多
基金Science &Technology Plan Foundation of Hunan Province,China(No.2010F3102)Science Research Foundation of Hunan Province,China(No.08C392)
文摘In order to obtain variable characteristics,the digital filter's type,number of taps and coefficients should be changed constantly such that the desired frequency-domain characteristics can be obtained.This paper proposes a method for self-programmable variable digital filter(VDF) design based on field programmable gate array(FPGA).We implement a digital filter system by using custom embedded micro-processor,programmable finite impulse response(P-FIR) macro module,coefficient-loader,clock manager and analog/digital(A/D) or digital/analog(D/A) controller and other modules.The self-programmable VDF can provide the best solution for realization of digital filter algorithms,which are the low-pass,high-pass,band-pass and band-stop filter algorithms with variable frequency domain characteristics.The design examples with minimum 1 to maximum 32 taps FIR filter,based on Modelsim post-routed simulation and onboard running on XUPV5-LX110T,are provided to demonstrate the effectiveness of the proposed method.
文摘An intelligent fuzzy logic inference pipeline for the control of a dc-dc buck-boost converter was designed and built using a semi-custom VLSI chip. The fuzzy linguistics describing the switching topologies of the converter was mapped into a look-up table that was synthesized into a set of Boolean equations. A VLSI chip–a field programmable gate array (FPGA) was used to implement the Boolean equations. Features include the size of RAM chip independent of number of rules in the knowledge base, on-chip fuzzification and defuzzification, faster response with speeds over giga fuzzy logic inferences per sec (FLIPS), and an inexpensive VLSI chip. The key application areas are: 1) on-chip integrated controllers;and 2) on-chip co-integration for entire system of sensors, circuits, controllers, and detectors for building complete instrument systems.
基金supported by the Key Techniques of FPGA Architecture under Grant No.9140A08010106QT9201
文摘A novel test approach for interconnect resources(IRs)in field programmable gate arrays(FPGA)has been proposed.In the test approach,SBs(switch boxes)of IRs in FPGA has been utilized to test IRs.Furthermore,configurable logic blocks(CLBs)in FPGA have also been employed to enhance driving capability and the position of fault IR can be determined by monitoring the IRs associated SBs.As a result,IRs can be scanned maximally with minimum configuration patterns.In the experiment,an in-house developed FPGA test system based on system-on-chip(SoC)hardware/software verification technology has been applied to test XC4000E family of Xilinx.The experiment results revealed that the IRs in FPGA can be tested by 6 test patterns.
基金Supported by National Natural Science Foundation of China (No. 10405023)Knowledge Innovation Program of The Chinese Academy of Sciences (KJCX2-YW-N27)
文摘In this paper, the design of a coarse-fine interpolation Time-to-Digital Converter (TDC) is implemented in an ALTERA’s Cyclone FPGA. The carry-select chain performs as the tapped delay line. The Logic Array Block (LAB) having a propagation delay of 165 ps in the chain is synthesized as delay cell. Coarse counters triggered by the global clock count the more significant bits of the time data. This clock is also fed through the delay line, and LABs create the copies. The replicas are latched by the tested event signal, and the less significant bits are encoded from the latched binary bits. Single-shot resolution of the TDC can be 60 ps. The worst Differential Nonlinearity (DNL) is about 0.2 Least Significant Bit (LSB, 165 ps in this TDC module), and the Integral Nonlinearity (INL) is 0.6 LSB. In comparison with other architectures using the synchronous global clock to sample the taps, this architecture consumed less electric power and logic cells, and is more stable.
文摘Piezoelectric resonators are widely used in frequency reference devices, mass sensors, resonant sensors(such as gyros and accelerometers), etc. Piezoelectric resonators usually work in a special resonant mode. Obtaining working resonant mode with high quality is key to improve the performance of piezoelectric resonators. In this paper, the resonance characteristics of a rectangular lead zirconium titanate(PZT) piezoelectric resonator are studied. On the basis of the field-programmable gate array(FPGA) embedded system, direct digital synthesizer(DDS) and automatic gain controller(AGC) are used to generate the driving signals with precisely adjustable frequency and amplitude. The driving signals are used to excite the piezoelectric resonator to the working vibration mode. The influence of the connection of driving electrodes and voltage amplitude on the vibration of the resonator is studied. The quality factor and vibration linearity of the resonator are studied with various driving methods mentioned in this paper. The resonator reaches resonant mode at 330 kHz by different driving methods.The relationship between resonant amplitude and driving signal amplitude is linear. The quality factor reaches over 150 by different driving methods. The results provide a theoretical reference for the efficient excitation of the piezoelectric resonator.
文摘In order to solve the current high failure rate of warship equipment field programmable gate array( FPGA) software,fault detection is not timely enough and FPGA detection equipment is expensive and so on. After in-depth research,this paper proposes a warship equipment FPGA software based on Xilinx integrated development environment( ISE) and ModelSim software.Functional simulation and timing simulation to verify the correctness of the logic design of the FPGA,this method is very convenient to view the signal waveform inside the FPGA program to help FPGA test engineers to achieve FPGA fault prediction and diagnosis. This test method has important engineering significance for the upgrading of warship equipment.
基金the National Science Foundation of China(Nos.60934007 and 61074060)the Postdoctoral Science Foundation of China(No.20090460627)+2 种基金the Postdoctoral Scientific Program of Shanghai (No.10R21414600)the Specialized Research Fund for the Doctoral Program of Higher Education (No.20070248004)the China Postdoctoral Science Foundation Special Support(No.201003272)
文摘High performance computer is often required by model predictive control(MPC) systems due to the heavy online computation burden.To extend MPC to more application cases with low-cost computation facilities, the implementation of MPC controller on field programmable gate array(FPGA) system is studied.For the dynamic matrix control(DMC) algorithm,the main design idea and the implemental strategy of DMC controller are introduced based on a FPGA’s embedded system.The performance tests show that both the computation efficiency and the accuracy of the proposed controller can be satisfied due to the parallel computing capability of FPGA.
文摘大规模双馈风电场作为实现我国“双碳”目标的陆上风电主力,其高比例电力电子设备的接入对电力系统电磁暂态高精度仿真技术提出日益严苛的要求,面向上百台发电单元的双馈场站全拓扑精细化微秒级仿真研究仍相对空白。基于现场可编程门阵列(field programmable gate array,FPGA)微秒级小步长并行仿真能力,提出一种面向双馈风电场站的发电单元FPGA并行仿真方法。首先,进行双馈感应电机微秒级高并行度离散化建模与换流器受控源建模;接着,对节点导纳矩阵分块降维以实现发电单元内部分网并行,并从整体电路解算层面提出单元级并行仿真框架;最后,考虑实时数字仿真器(real time digital simulator,RTDS)与FPGA仿真平台特点,分配发电单元的微秒级小步长仿真任务并搭建联合仿真硬件框架;通过对比RTDS标准模型与RTDS+FPGA联合仿真模型,验证所提并行仿真方法的准确性。
