Static Random Access Memory(SRAM) based Field Programmable Gate Array(FPGA) is widely applied in the field of aerospace, whose anti-SEU(Single Event Upset) capability becomes more and more important. To improve anti-F...Static Random Access Memory(SRAM) based Field Programmable Gate Array(FPGA) is widely applied in the field of aerospace, whose anti-SEU(Single Event Upset) capability becomes more and more important. To improve anti-FPGA SEU capability, the registers of the circuit netlist are tripled and divided into three categories in this study. By the packing algorithm, the registers of triple modular redundancy are loaded into different configurable logic block. At the same time, the packing algorithm considers the effect of large fan-out nets. The experimental results show that the algorithm successfully realize the packing of the register of Triple Modular Redundancy(TMR). Comparing with Timing Versatile PACKing(TVPACK), the algorithm in this study is able to obtain a 11% reduction of the number of the nets in critical path, and a 12% reduction of the time delay in critical path on average when TMR is not considered. Especially, some critical path delay of circuit can be improved about 33%.展开更多
A transformer-in-package(TiP)isolated direct current-direct current(DC-DC)converter using glass-based fan-out wafer-level packaging(FOWLP)is proposed.By using 3-layer redistribution layers(RDLs),both the transformer a...A transformer-in-package(TiP)isolated direct current-direct current(DC-DC)converter using glass-based fan-out wafer-level packaging(FOWLP)is proposed.By using 3-layer redistribution layers(RDLs),both the transformer and interconnections are built without an additional transformer chip,and the converter only has 2 dies:a transmitter(TX)chip and a receiver(RX)chip.The proposed solution results in a significant reduction in the cost and makes major improvements in the form factor and power density.Moreover,the transformer built by the RDLs achieves a high quality factor(Q)and high coupling factor(k),and the efficiency of the converter is thus improved.The TX and RX chips were implemented in a 0.18μm Biopolar CMOS DMOS(BCD)process and embedded in a compact package with a size of 5 mm×5 mm.With an output capacitance of 10μF,the converter achieves a peak efficiency of 46.5%at 0.3 W output power and a maximum delivery power of 1.25 W,achieving a maximum power density of 50 mW/mm2.展开更多
在充满挑战的半导体商业环境中,封测代工(outsourced semiconductor assembly and test)工业能被预见到会有一个稳定的,在许多产品细分上强有力的增长。整个半导体行业兼并收购的活动进行得如火如荼,这对封测代工厂来说意味着越来越少...在充满挑战的半导体商业环境中,封测代工(outsourced semiconductor assembly and test)工业能被预见到会有一个稳定的,在许多产品细分上强有力的增长。整个半导体行业兼并收购的活动进行得如火如荼,这对封测代工厂来说意味着越来越少的客户群。中国的封测代工生意任道而重远,扩张兼并的脚步仍在大踏步前行。展开更多
In the post-Moore era,advanced packaging is becoming more critical to meet the everlasting demands of elec-tronic products with smaller size,more powerful performance and lower cost.In this paper,developments in advan...In the post-Moore era,advanced packaging is becoming more critical to meet the everlasting demands of elec-tronic products with smaller size,more powerful performance and lower cost.In this paper,developments in advanced packaging have been discussed,such as 3D IC packaging,fan-out packaging,and chiplet packaging.Insights on the major advantages and challenges have also been briefly introduced.Our prospects about the solu-tions to some fundamental issues in sustainable development of advanced packaging have also been elucidated.The critical aspects and opportunities lie in standardization,co-design tools,new handling technologies,as well as multi-scale modeling and simulation.展开更多
基金Supported by the National Natural Science Foundation of China(No.61106033)
文摘Static Random Access Memory(SRAM) based Field Programmable Gate Array(FPGA) is widely applied in the field of aerospace, whose anti-SEU(Single Event Upset) capability becomes more and more important. To improve anti-FPGA SEU capability, the registers of the circuit netlist are tripled and divided into three categories in this study. By the packing algorithm, the registers of triple modular redundancy are loaded into different configurable logic block. At the same time, the packing algorithm considers the effect of large fan-out nets. The experimental results show that the algorithm successfully realize the packing of the register of Triple Modular Redundancy(TMR). Comparing with Timing Versatile PACKing(TVPACK), the algorithm in this study is able to obtain a 11% reduction of the number of the nets in critical path, and a 12% reduction of the time delay in critical path on average when TMR is not considered. Especially, some critical path delay of circuit can be improved about 33%.
基金supported in part by the National Natural Science Foundation of China(62104220)in part by the National Key Research and Development Program of China(2019YFB2204800).
文摘A transformer-in-package(TiP)isolated direct current-direct current(DC-DC)converter using glass-based fan-out wafer-level packaging(FOWLP)is proposed.By using 3-layer redistribution layers(RDLs),both the transformer and interconnections are built without an additional transformer chip,and the converter only has 2 dies:a transmitter(TX)chip and a receiver(RX)chip.The proposed solution results in a significant reduction in the cost and makes major improvements in the form factor and power density.Moreover,the transformer built by the RDLs achieves a high quality factor(Q)and high coupling factor(k),and the efficiency of the converter is thus improved.The TX and RX chips were implemented in a 0.18μm Biopolar CMOS DMOS(BCD)process and embedded in a compact package with a size of 5 mm×5 mm.With an output capacitance of 10μF,the converter achieves a peak efficiency of 46.5%at 0.3 W output power and a maximum delivery power of 1.25 W,achieving a maximum power density of 50 mW/mm2.
文摘在充满挑战的半导体商业环境中,封测代工(outsourced semiconductor assembly and test)工业能被预见到会有一个稳定的,在许多产品细分上强有力的增长。整个半导体行业兼并收购的活动进行得如火如荼,这对封测代工厂来说意味着越来越少的客户群。中国的封测代工生意任道而重远,扩张兼并的脚步仍在大踏步前行。
基金funded by National Natural Science Foundation of China(62274122 and 62004144)Guangdong Basic and Applied Basic Research Foundation(2021A1515010651)Hubei Provincial Natural Science Foundation of China(2020CFA032).
文摘In the post-Moore era,advanced packaging is becoming more critical to meet the everlasting demands of elec-tronic products with smaller size,more powerful performance and lower cost.In this paper,developments in advanced packaging have been discussed,such as 3D IC packaging,fan-out packaging,and chiplet packaging.Insights on the major advantages and challenges have also been briefly introduced.Our prospects about the solu-tions to some fundamental issues in sustainable development of advanced packaging have also been elucidated.The critical aspects and opportunities lie in standardization,co-design tools,new handling technologies,as well as multi-scale modeling and simulation.
